Fix files with multiple newlines at the end.

Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
microserver
Martin Roth 5 years ago
parent fa1d383f93
commit 467a87abce
  1. 1
      .checkpatch.conf
  2. 1
      src/arch/x86/include/arch/pirq_routing.h
  3. 1
      src/cpu/amd/agesa/family14/romstage.c
  4. 1
      src/lib/gnat/COPYING.RUNTIME
  5. 1
      src/mainboard/asus/p5gc-mx/Makefile.inc
  6. 1
      src/mainboard/elmex/pcm205400/buildOpts.c
  7. 1
      src/mainboard/google/reef/variants/coral/mainboard.c
  8. 1
      src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h
  9. 1
      src/mainboard/intel/leafhill/Kconfig.name
  10. 1
      src/mainboard/intel/minnow3/gpio.c
  11. 1
      src/mainboard/lenovo/x1_carbon_gen1/mainboard.c
  12. 2
      src/mainboard/pcengines/apu2/mainboard.c
  13. 1
      src/mainboard/purism/librem13v2/Makefile.inc
  14. 1
      src/soc/intel/apollolake/xdci.c
  15. 1
      src/soc/intel/cannonlake/bootblock/cpu.c
  16. 1
      src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
  17. 1
      src/soc/intel/cannonlake/romstage/power_state.c
  18. 1
      src/soc/intel/common/block/cse/Kconfig
  19. 1
      src/soc/intel/common/block/include/intelblocks/msr.h
  20. 1
      src/soc/intel/common/block/include/intelblocks/xhci.h
  21. 1
      src/soc/intel/common/block/sata/Kconfig
  22. 1
      src/soc/intel/common/block/smbus/Makefile.inc

@ -28,4 +28,3 @@
# Exclude the vendorcode directory
--exclude src/vendorcode

@ -63,4 +63,3 @@ unsigned long write_pirq_routing_table(unsigned long start);
void pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]);
#endif /* ARCH_PIRQ_ROUTING_H */

@ -75,4 +75,3 @@ void agesa_postcar(struct sysinfo *cb)
post_code(0x62);
}
}

@ -70,4 +70,3 @@ consistent with the licensing of the Independent Modules.
The availability of this Exception does not imply any general
presumption that third-party software is unaffected by the copyleft
requirements of the license of GCC.

@ -1,3 +1,2 @@
ramstage-y += cstates.c
romstage-y += gpio.c

@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

@ -29,4 +29,3 @@ void variant_nhlt_oem_overrides(const char **oem_id,
*oem_table_id = CONFIG_VARIANT_DIR;
*oem_revision = variant_board_sku();
}

@ -218,4 +218,3 @@ static const struct pad_config early_gpio_table[] = {
#endif
#endif

@ -1,3 +1,2 @@
config BOARD_INTEL_LEAFHILL
bool "Leafhill"

@ -348,4 +348,3 @@ const struct pad_config *sleep_gpio_table(size_t *num)
*num = ARRAY_SIZE(sleep_gpio_table_config);
return sleep_gpio_table_config;
}

@ -34,4 +34,3 @@ struct chip_operations mainboard_ops = {
void h8_mainboard_init_dock (void)
{
}

@ -231,5 +231,3 @@ const char *smbios_mainboard_sku(void)
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

@ -18,4 +18,3 @@ romstage-y += pei_data.c
ramstage-y += pei_data.c
ramstage-y += ramstage.c
ramstage-y += hda_verb.c

@ -89,4 +89,3 @@ void soc_xdci_init(struct device *dev)
{
configure_host_mode_port0(dev);
}

@ -25,4 +25,3 @@ void bootblock_cpu_init(void)
IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
fast_spi_cache_bios_region();
}

@ -249,4 +249,3 @@
#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)
#endif

@ -29,4 +29,3 @@ struct chipset_power_state *fill_power_state(void)
return ps;
}

@ -4,4 +4,3 @@ config SOC_INTEL_COMMON_BLOCK_CSE
help
Driver for communication with Converged Security Engine (CSE)
over Host Embedded Controller Interface (HECI)

@ -133,4 +133,3 @@
#define SGX_SUPPORTED (1<<2)
#endif /* SOC_INTEL_COMMON_MSR_H */

@ -19,4 +19,3 @@
void soc_xhci_init(struct device *dev);
#endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */

@ -2,4 +2,3 @@ config SOC_INTEL_COMMON_BLOCK_SATA
bool
help
Intel Processor common SATA support

@ -6,4 +6,3 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus.c

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