92 lines
2.6 KiB
C
92 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <intelblocks/xdci.h>
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#include <soc/pci_devs.h>
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#include <timer.h>
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#define DUAL_ROLE_CFG0 0x80d8
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# define DRD_CONFIG_MASK (0x3 << 0)
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# define DRD_CONFIG_DYNAMIC (0x0 << 0)
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# define DRD_CONFIG_HOST (0x1 << 0)
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# define DRD_CONFIG_DEVICE (0x2 << 0)
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# define SW_VBUS_VALID_MASK (1 << 24)
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# define SW_VBUS_DEASSERT_VALID (0 << 24)
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# define SW_VBUS_ASSERT_VALID (1 << 24)
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# define SW_IDPIN_EN_MASK (1 << 21)
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# define SW_IDPIN_DIS (0 << 21)
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# define SW_IDPIN_EN (1 << 21)
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# define SW_IDPIN_MASK (1 << 20)
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# define SW_IDPIN_HOST (0 << 20)
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# define SW_IDPIN_DEVICE (1 << 20)
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#define DUAL_ROLE_CFG1 0x80dc
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# define DRD_MODE_MASK (1 << 29)
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# define DRD_MODE_DEVICE (0 << 29)
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# define DRD_MODE_HOST (1 << 29)
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static void configure_host_mode_port0(struct device *dev)
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{
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uint32_t *cfg0;
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uint32_t *cfg1;
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const struct resource *res;
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uint32_t reg;
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struct stopwatch sw;
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struct device *xdci_dev = PCH_DEV_XDCI;
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/*
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* Only default to host mode if the xdci device is present and
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* enabled. If it's disabled assume the switch was already done
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* in FSP.
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*/
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if (!dev->enabled || !xdci_dev->enabled)
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return;
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printk(BIOS_INFO, "Putting port 0 into host mode.\n");
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res = find_resource(xdci_dev, PCI_BASE_ADDRESS_0);
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cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0);
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cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1);
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reg = read32(cfg0);
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reg &= ~(DRD_CONFIG_MASK | SW_IDPIN_EN_MASK | SW_IDPIN_MASK);
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reg &= ~(SW_VBUS_VALID_MASK);
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reg |= DRD_CONFIG_DYNAMIC | SW_IDPIN_EN | SW_IDPIN_HOST;
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reg |= SW_VBUS_DEASSERT_VALID;
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write32(cfg0, reg);
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stopwatch_init_msecs_expire(&sw, 10);
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/* Wait for the host mode status bit. */
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while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_INFO, "Timed out waiting for host mode.\n");
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break;
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}
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}
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printk(BIOS_INFO, "XDCI port 0 host switch over took %lu ms\n",
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stopwatch_duration_msecs(&sw));
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}
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void soc_xdci_init(struct device *dev)
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{
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configure_host_mode_port0(dev);
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}
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