221 lines
9.9 KiB
C
221 lines
9.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef _GPIORVP7_H
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#define _GPIORVP7_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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/* TCA6424A I/O Expander */
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#define IO_EXPANDER_BUS 4
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#define IO_EXPANDER_0_ADDR 0x22
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#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */
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#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */
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#define IO_EXPANDER_P1CONF 0x0D
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#define IO_EXPANDER_P1DOUT 0x05
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#define IO_EXPANDER_P2CONF 0x0E
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#define IO_EXPANDER_P2DOUT 0x06
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#define IO_EXPANDER_1_ADDR 0x23
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/* GPE_EC_WAKE */
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#define GPE_EC_WAKE GPE0_LAN_WAK
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/* CHROMEEC in RVP */
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#define EC_SCI_GPI GPP_E16
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#define EC_SMI_GPI GPP_E15
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/*
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* Gpio based irq for touchpad, 18th index in North Bank
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* MAX_DIRECT_IRQ + GPSW_SIZE + 19
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*/
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#define KBLRVP_TOUCHPAD_IRQ 33
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#define KBLRVP_TOUCH_IRQ 31
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#define BOARD_TOUCHPAD_NAME "touchpad"
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#define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ
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#define BOARD_TOUCHPAD_I2C_BUS 0
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#define BOARD_TOUCHPAD_I2C_ADDR 0x20
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#define BOARD_TOUCHSCREEN_NAME "touchscreen"
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#define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ
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#define BOARD_TOUCHSCREEN_I2C_BUS 0
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#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c
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#ifndef __ACPI__
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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/* PM_SLP_S0ix_R_N*/ PAD_CFG_GPO(GPP_A7, 1, DEEP),
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/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* PCH_CLK_PCI_TPM */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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/* PCH_LPC_CLK */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP),
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/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 1, RSMRST),
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/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
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/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
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/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
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/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
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/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
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/* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP),
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/* ISH_GP5 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP),
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/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
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/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
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/* HSJ_MIC_DET */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
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/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
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/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP),
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/* SRCCLKREQ0# */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP),
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/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* GPP_B_14_SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP),
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/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, PLTRST, YES),
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/* TBT_CIO_PLUG_EVT */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PU, PLTRST, YES),
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/* PCH_SLOT1_WAKE_N */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, PLTRST, YES),
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/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
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/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
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/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
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/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
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/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP),
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/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
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/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP),
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/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, DEEP),
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/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
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/* USB_CTL */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1),
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/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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/* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
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/* EN_PP3300_KEPLER */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
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/* PCH_MEM_CFG0 */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
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/* PCH_MEM_CFG1 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
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/* PCH_MEM_CFG2 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
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/* PCH_MEM_CFG3 */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
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/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
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/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
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/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
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/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
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/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
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/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
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/* TCH_PNL_PWREN */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
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/* SPI_WP_STATUS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
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/* ITCH_SPI_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
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/* ITCH_SPI_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
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/* ITCH_SPI_MISO_1 */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
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/* ITCH_SPI_MISO_0 */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
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/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
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/* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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/* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
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PAD_CFG_GPI(GPP_D9, NONE, DEEP),
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/* SD_D3_WAKE */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),
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/* USB_A1_ILIM_SEL */ PAD_CFG_GPI(GPP_D11, NONE, DEEP),
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/* EN_PP3300_DX_CAM */ PAD_CFG_GPI(GPP_D12, NONE, DEEP),
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/* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
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/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
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/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1),
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/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1),
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/* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
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/* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
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/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
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/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP),
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/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
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/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
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/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, RSMRST),
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/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
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/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
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/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
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/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
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/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
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/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, YES),
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/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
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/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
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/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
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/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
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/* PCH_CODEC_IRQ */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
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/* TCH_PNL_RST */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP),
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/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
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/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
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/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
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/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
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/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
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/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
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/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
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/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
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/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
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/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
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/* AUDIO_IRQ */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2),
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/* I2C5_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2),
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/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* WWAN_UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP),
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/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
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/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
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/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
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/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
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/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
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/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
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/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
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/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
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/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
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/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
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/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
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/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
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/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
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/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
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/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPD7, NONE, DEEP, NF1),
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/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
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/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
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/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
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/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
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};
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/* Early pad configuration in romstage. */
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static const struct pad_config early_gpio_table[] = {
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/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
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/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
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};
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#endif
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#endif
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