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nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMIC 

Change-Id: I4ec59cea256a39a94b05cdeb8f914830ac0bd3f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-02-10 19:22:31 +02:00
parent b8b41338aa
commit 11c6b8b531
8 changed files with 12 additions and 16 deletions
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3
src/northbridge/intel/haswell/Kconfig
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@ -25,6 +25,9 @@ config HASWELL_VBOOT_IN_BOOTBLOCK
binary is used meaning a jump is made from RW to the RO region binary is used meaning a jump is made from RW to the RO region
and back to the RW region after the binary is done. and back to the RW region after the binary is done.
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK

4
src/northbridge/intel/haswell/northbridge.c
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@ -14,7 +14,6 @@
#include <boot/tables.h> #include <boot/tables.h>
#include <security/intel/txt/txt_register.h> #include <security/intel/txt/txt_register.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "chip.h" #include "chip.h"
#include "haswell.h" #include "haswell.h"
@ -336,9 +335,6 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
if (CONFIG(CHROMEOS_RAMOOPS))
chromeos_reserve_ram_oops(dev, index++);
*resource_cnt = index; *resource_cnt = index;
} }

3
src/northbridge/intel/sandybridge/Kconfig
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@ -32,6 +32,9 @@ config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
binary is used meaning a jump is made from RW to the RO region binary is used meaning a jump is made from RW to the RO region
and back to the RW region after the binary is done. and back to the RW region after the binary is done.
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK

4
src/northbridge/intel/sandybridge/northbridge.c
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@ -14,7 +14,6 @@
#include "chip.h" #include "chip.h"
#include "sandybridge.h" #include "sandybridge.h"
#include <cpu/intel/smm_reloc.h> #include <cpu/intel/smm_reloc.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* IGD UMA memory */ /* IGD UMA memory */
static uint64_t uma_memory_base = 0; static uint64_t uma_memory_base = 0;
@ -68,9 +67,6 @@ static void add_fixed_resources(struct device *dev, int index)
reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
if (CONFIG(CHROMEOS_RAMOOPS))
chromeos_reserve_ram_oops(dev, index++);
if (is_sandybridge()) { if (is_sandybridge()) {
/* Required for SandyBridge sighting 3715511 */ /* Required for SandyBridge sighting 3715511 */
bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);

3
src/soc/intel/baytrail/Kconfig
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@ -37,6 +37,9 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_HAS_L2_ENABLE_MSR select CPU_HAS_L2_ENABLE_MSR
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE select VBOOT_STARTS_IN_ROMSTAGE

4
src/soc/intel/baytrail/northcluster.c
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@ -10,7 +10,6 @@
#include <soc/iosf.h> #include <soc/iosf.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* /*
* Host Memory Map: * Host Memory Map:
@ -119,9 +118,6 @@ static void nc_read_resources(struct device *dev)
*/ */
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
if (CONFIG(CHROMEOS_RAMOOPS))
chromeos_reserve_ram_oops(dev, index++);
} }
static void nc_generate_ssdt(const struct device *dev) static void nc_generate_ssdt(const struct device *dev)

3
src/soc/intel/braswell/Kconfig
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@ -52,6 +52,9 @@ config DCACHE_BSP_STACK_SIZE
The amount of anticipated stack usage in CAR by bootblock and The amount of anticipated stack usage in CAR by bootblock and
other stages. other stages.
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE select VBOOT_STARTS_IN_ROMSTAGE

4
src/soc/intel/braswell/northcluster.c
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@ -13,7 +13,6 @@
#include <soc/iosf.h> #include <soc/iosf.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <stddef.h> #include <stddef.h>
/* /*
@ -145,9 +144,6 @@ static void nc_read_resources(struct device *dev)
base_k = RES_IN_KiB(LAPIC_DEFAULT_BASE); base_k = RES_IN_KiB(LAPIC_DEFAULT_BASE);
size_k = RES_IN_KiB(0x00100000); size_k = RES_IN_KiB(0x00100000);
mmio_resource(dev, index++, base_k, size_k); mmio_resource(dev, index++, base_k, size_k);
if (CONFIG(CHROMEOS_RAMOOPS))
chromeos_reserve_ram_oops(dev, index++);
} }
static void nc_generate_ssdt(const struct device *dev) static void nc_generate_ssdt(const struct device *dev)