170 lines
4.3 KiB
Plaintext
170 lines
4.3 KiB
Plaintext
## SPDX-License-Identifier: GPL-2.0-only
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config NORTHBRIDGE_INTEL_SANDYBRIDGE
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bool
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select CACHE_MRC_SETTINGS
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select CPU_INTEL_MODEL_206AX
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select HAVE_DEBUG_RAM_SETUP
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select INTEL_GMA_ACPI
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if NORTHBRIDGE_INTEL_SANDYBRIDGE
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config SANDYBRIDGE_VBOOT_IN_ROMSTAGE
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bool
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default n
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help
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Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE.
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config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
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depends on VBOOT
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depends on !SANDYBRIDGE_VBOOT_IN_ROMSTAGE
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bool "Start verstage in bootblock"
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default y
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_SEPARATE_VERSTAGE
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help
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Sandy Bridge can either start verstage in a separate stage
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right after the bootblock has run or it can start it
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after romstage for compatibility reasons.
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Sandy Bridge however uses a mrc.bin to initialize memory which
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needs to be located at a fixed offset. Therefore even with
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a separate verstage starting after the bootblock that same
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binary is used meaning a jump is made from RW to the RO region
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and back to the RW region after the binary is done.
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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config VBOOT
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select VBOOT_MUST_REQUEST_DISPLAY
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select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
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config USE_NATIVE_RAMINIT
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bool "Use native raminit"
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default y
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help
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Select if you want to use coreboot implementation of raminit rather than
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System Agent/MRC.bin. You should answer Y.
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config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
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bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
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default n
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depends on USE_NATIVE_RAMINIT
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help
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Ignore the mainboard's vendor programmed fuses that might limit the
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maximum DRAM frequency. By selecting this option the fuses will be
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ignored and the only limits on DRAM frequency are set by RAM's SPD and
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hard fuses in southbridge's clockgen.
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Disabled by default as it might causes system instability.
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Handle with care!
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config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS
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bool "Ignore XMP profile max DIMMs per channel"
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default n
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depends on USE_NATIVE_RAMINIT
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help
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Ignore the max DIMMs per channel restriciton defined in XMP profiles.
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Disabled by default as it might cause system instability.
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Handle with care!
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config NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE
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bool "Ignore XMP profile requested voltage"
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default n
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depends on USE_NATIVE_RAMINIT
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help
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Native raminit only supports 1.5V operation, but there are DIMMs
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which request 1.65V operation in XMP profiles. This option allows
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raminit to use these XMP profiles anyway, instead of falling back
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to non-XMP settings.
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Disabled by default because it allows forcing memory to run out of
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specification. Consider this to be an overclocking option.
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Handle with care!
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config CBFS_SIZE
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hex
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default 0x100000
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config VGA_BIOS_ID
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string
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default "8086,0106"
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config MMCONF_BASE_ADDRESS
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default 0xf0000000
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help
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The MRC blob requires it to be at 0xf0000000.
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config MMCONF_BUS_NUMBER
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int
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default 64
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config DCACHE_RAM_BASE
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hex
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default 0xfefe0000
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x10000
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help
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The amount of BSP stack anticipated in bootblock and
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other stages.
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if USE_NATIVE_RAMINIT
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config DCACHE_RAM_SIZE
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hex
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default 0x20000
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x0
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config RAMINIT_ALWAYS_ALLOW_DLL_OFF
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bool "Also enable memory DLL-off mode on desktops and servers"
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default n
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help
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If enabled, allow enabling DLL-off mode for platforms other than
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mobile. Saves power at the expense of higher exit latencies. Has
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no effect on mobile platforms, where DLL-off is always allowed.
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Power down is disabled for stability when running at high clocks.
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config RAMINIT_ENABLE_ECC
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bool "Enable ECC if supported"
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default y
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help
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Enable ECC if supported by both, host and RAM.
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endif # USE_NATIVE_RAMINIT
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if !USE_NATIVE_RAMINIT
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config DCACHE_RAM_SIZE
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hex
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default 0x17000
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config DCACHE_RAM_MRC_VAR_SIZE
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hex
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default 0x9000
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config MRC_FILE
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string "Intel System Agent path and filename"
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default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
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help
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The path and filename of the file to use as System Agent
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binary.
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endif # !USE_NATIVE_RAMINIT
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config INTEL_GMA_BCLV_OFFSET
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default 0x48254
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config FIXED_MCHBAR_MMIO_BASE
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default 0xfed10000
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config FIXED_DMIBAR_MMIO_BASE
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default 0xfed18000
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config FIXED_EPBAR_MMIO_BASE
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default 0xfed19000
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endif
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