431 lines
11 KiB
C
431 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <acpi/acpi.h>
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#include <commonlib/helpers.h>
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#include <device/pci_ops.h>
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#include <delay.h>
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#include <cpu/intel/model_206ax/model_206ax.h>
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <types.h>
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#include "chip.h"
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#include "sandybridge.h"
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#include <cpu/intel/smm_reloc.h>
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/* IGD UMA memory */
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static uint64_t uma_memory_base = 0;
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static uint64_t uma_memory_size = 0;
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bool is_sandybridge(void)
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{
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const uint16_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID);
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return (bridge_id & BASE_REV_MASK) == BASE_REV_SNB;
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}
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/* Reserve everything between A segment and 1MB:
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*
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* 0xa0000 - 0xbffff: legacy VGA
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* 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
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* 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
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*/
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static const int legacy_hole_base_k = 0xa0000 / 1024;
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static const int legacy_hole_size_k = 384;
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static const char *northbridge_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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switch (dev->path.pci.devfn) {
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case PCI_DEVFN(0, 0):
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return "MCHC";
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}
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return NULL;
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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.write_acpi_tables = northbridge_write_acpi_tables,
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.acpi_name = northbridge_acpi_name,
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};
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static void add_fixed_resources(struct device *dev, int index)
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{
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mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
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mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k);
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reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
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if (is_sandybridge()) {
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/* Required for SandyBridge sighting 3715511 */
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bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
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bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
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}
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/* Reserve IOMMU BARs */
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const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
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if (!(capid0_a & (1 << 23))) {
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mmio_resource(dev, index++, GFXVT_BASE >> 10, 4);
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mmio_resource(dev, index++, VTVC0_BASE >> 10, 4);
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}
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}
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static void mc_read_resources(struct device *dev)
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{
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uint64_t tom, me_base, touud;
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uint32_t tseg_base, uma_size, tolud;
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uint16_t ggc;
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unsigned long long tomk;
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unsigned long index = 3;
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pci_dev_read_resources(dev);
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mmconf_resource(dev, PCIEXBAR);
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/* Total Memory 2GB example:
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*
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* 00000000 0000MB-1992MB 1992MB RAM (writeback)
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* 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
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* 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
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* 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
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* 7f200000 2034MB TOLUD
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* 7f800000 2040MB MEBASE
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* 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
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* 80000000 2048MB TOM
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* 100000000 4096MB-4102MB 6MB RAM (writeback)
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*
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* Total Memory 4GB example:
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*
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* 00000000 0000MB-2768MB 2768MB RAM (writeback)
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* ad000000 2768MB-2776MB 8MB TSEG (SMRR)
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* ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
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* ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
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* afa00000 2810MB TOLUD
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* ff800000 4088MB MEBASE
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* ff800000 4088MB-4096MB 8MB ME UMA (uncached)
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* 100000000 4096MB TOM
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* 100000000 4096MB-5374MB 1278MB RAM (writeback)
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* 14fe00000 5368MB TOUUD
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*/
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/* Top of Upper Usable DRAM, including remap */
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touud = pci_read_config32(dev, TOUUD + 4);
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touud <<= 32;
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touud |= pci_read_config32(dev, TOUUD);
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/* Top of Lower Usable DRAM */
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tolud = pci_read_config32(dev, TOLUD);
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/* Top of Memory - does not account for any UMA */
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tom = pci_read_config32(dev, TOM + 4);
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tom <<= 32;
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tom |= pci_read_config32(dev, TOM);
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printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
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touud, tolud, tom);
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/* ME UMA needs excluding if total memory < 4GB */
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me_base = pci_read_config32(dev, MESEG_BASE + 4);
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me_base <<= 32;
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me_base |= pci_read_config32(dev, MESEG_BASE);
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printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base);
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uma_memory_base = tolud;
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tomk = tolud >> 10;
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if (me_base == tolud) {
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/* ME is from MEBASE-TOM */
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uma_size = (tom - me_base) >> 10;
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/* Increment TOLUD to account for ME as RAM */
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tolud += uma_size << 10;
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/* UMA starts at old TOLUD */
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uma_memory_base = tomk * 1024ULL;
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uma_memory_size = uma_size * 1024ULL;
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printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n",
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me_base, uma_size >> 10);
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}
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/* Graphics memory comes next */
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ggc = pci_read_config16(dev, GGC);
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if (!(ggc & 2)) {
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printk(BIOS_DEBUG, "IGD decoded, subtracting ");
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/* Graphics memory */
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uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
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printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10);
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tomk -= uma_size;
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uma_memory_base = tomk * 1024ULL;
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uma_memory_size += uma_size * 1024ULL;
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/* GTT Graphics Stolen Memory Size (GGMS) */
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uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
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tomk -= uma_size;
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uma_memory_base = tomk * 1024ULL;
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uma_memory_size += uma_size * 1024ULL;
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printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10);
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}
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/* Calculate TSEG size from its base which must be below GTT */
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tseg_base = pci_read_config32(dev, TSEGMB);
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uma_size = (uma_memory_base - tseg_base) >> 10;
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tomk -= uma_size;
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uma_memory_base = tomk * 1024ULL;
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uma_memory_size += uma_size * 1024ULL;
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printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
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printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10);
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/* Report the memory regions */
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ram_resource(dev, index++, 0, legacy_hole_base_k);
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ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k,
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(tomk - (legacy_hole_base_k + legacy_hole_size_k)));
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/*
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* If >= 4GB installed, then memory from TOLUD to 4GB is remapped above TOM.
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* TOUUD will account for both memory chunks.
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*/
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touud >>= 10; /* Convert to KB */
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if (touud > 4096 * 1024) {
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ram_resource(dev, index++, 4096 * 1024, touud - (4096 * 1024));
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printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096);
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}
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add_fixed_resources(dev, index++);
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}
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static void northbridge_dmi_init(struct device *dev)
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{
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const bool is_sandy = is_sandybridge();
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const u8 stepping = cpu_stepping();
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u32 reg32;
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/* Steps prior to DMI ASPM */
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if (is_sandy) {
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reg32 = DMIBAR32(0x250);
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reg32 &= ~(7 << 20);
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reg32 |= (2 << 20);
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DMIBAR32(0x250) = reg32;
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}
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reg32 = DMIBAR32(DMILLTC);
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reg32 |= (1 << 29);
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DMIBAR32(DMILLTC) = reg32;
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if (is_sandy && stepping == SNB_STEP_C0) {
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reg32 = DMIBAR32(0xbc8);
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reg32 &= ~(0xfff << 7);
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reg32 |= (0x7d3 << 7);
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DMIBAR32(0xbc8) = reg32;
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}
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if (!is_sandy || stepping >= SNB_STEP_D1) {
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reg32 = DMIBAR32(0x1f8);
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reg32 &= ~(1 << 26);
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reg32 |= (1 << 16);
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DMIBAR32(0x1f8) = reg32;
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reg32 = DMIBAR32(0x1fc);
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reg32 |= (1 << 12) | (1 << 23);
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DMIBAR32(0x1fc) = reg32;
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} else if (stepping >= SNB_STEP_D0) {
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reg32 = DMIBAR32(0x1f8);
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reg32 |= (1 << 16);
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DMIBAR32(0x1f8) = reg32;
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}
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/* Clear error status bits */
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DMIBAR32(DMIUESTS) = 0xffffffff;
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DMIBAR32(DMICESTS) = 0xffffffff;
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if (!is_sandy)
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DMIBAR32(0xc34) = 0xffffffff;
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/* Enable ASPM on SNB link, should happen before PCH link */
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if (is_sandy) {
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reg32 = DMIBAR32(0xd04);
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reg32 |= (1 << 4);
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DMIBAR32(0xd04) = reg32;
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}
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reg32 = DMIBAR32(DMILCTL);
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reg32 |= (1 << 1) | (1 << 0);
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DMIBAR32(DMILCTL) = reg32;
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}
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/* Disable unused PEG devices based on devicetree */
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static void disable_peg(void)
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{
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struct device *dev;
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u32 reg;
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dev = pcidev_on_root(0, 0);
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reg = pci_read_config32(dev, DEVEN);
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dev = pcidev_on_root(1, 2);
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if (!dev || !dev->enabled) {
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printk(BIOS_DEBUG, "Disabling PEG12.\n");
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reg &= ~DEVEN_PEG12;
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}
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dev = pcidev_on_root(1, 1);
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if (!dev || !dev->enabled) {
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printk(BIOS_DEBUG, "Disabling PEG11.\n");
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reg &= ~DEVEN_PEG11;
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}
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dev = pcidev_on_root(1, 0);
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if (!dev || !dev->enabled) {
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printk(BIOS_DEBUG, "Disabling PEG10.\n");
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reg &= ~DEVEN_PEG10;
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}
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dev = pcidev_on_root(2, 0);
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if (!dev || !dev->enabled) {
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printk(BIOS_DEBUG, "Disabling IGD.\n");
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reg &= ~DEVEN_IGD;
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}
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dev = pcidev_on_root(4, 0);
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if (!dev || !dev->enabled) {
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printk(BIOS_DEBUG, "Disabling Device 4.\n");
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reg &= ~DEVEN_D4EN;
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}
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dev = pcidev_on_root(6, 0);
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if (!dev || !dev->enabled) {
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printk(BIOS_DEBUG, "Disabling PEG60.\n");
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reg &= ~DEVEN_PEG60;
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}
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dev = pcidev_on_root(7, 0);
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if (!dev || !dev->enabled) {
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printk(BIOS_DEBUG, "Disabling Device 7.\n");
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reg &= ~DEVEN_D7EN;
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}
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dev = pcidev_on_root(0, 0);
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pci_write_config32(dev, DEVEN, reg);
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if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) {
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/*
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* Set the PEG clock gating bit. Disables the IO clock on all PEG devices.
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*
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* FIXME: Never clock gate on Ivy Bridge stepping A0!
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*/
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MCHBAR32_OR(PEGCTL, 1);
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printk(BIOS_DEBUG, "Disabling PEG IO clock.\n");
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} else {
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MCHBAR32_AND(PEGCTL, ~1);
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}
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}
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static void northbridge_init(struct device *dev)
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{
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u8 bios_reset_cpl;
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u32 bridge_type;
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northbridge_dmi_init(dev);
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bridge_type = MCHBAR32(SAPMTIMERS);
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bridge_type &= ~0xff;
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if (is_sandybridge()) {
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/* 20h for Sandybridge */
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bridge_type |= 0x20;
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} else {
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/* Enable Power Aware Interrupt Routing */
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u8 pair = MCHBAR8(INTRDIRCTL);
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pair &= ~0x0f; /* Clear 3:0 */
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pair |= 0x04; /* Fixed Priority */
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MCHBAR8(INTRDIRCTL) = pair;
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/* 30h for IvyBridge */
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bridge_type |= 0x30;
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}
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MCHBAR32(SAPMTIMERS) = bridge_type;
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/* Turn off unused devices. Has to be done before setting BIOS_RESET_CPL. */
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disable_peg();
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/*
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* Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
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* that BIOS has initialized memory and power management
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*/
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bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
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bios_reset_cpl |= 1;
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MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
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printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
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/* Configure turbo power limits 1ms after reset complete bit */
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mdelay(1);
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set_power_limits(28);
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/*
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* CPUs with configurable TDP also need power limits set in MCHBAR.
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* Use the same values from MSR_PKG_POWER_LIMIT.
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*/
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if (cpu_config_tdp_levels()) {
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msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT);
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MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = msr.lo;
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MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = msr.hi;
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}
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/* Set here before graphics PM init */
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MCHBAR32(PAVP_MSG) = 0x00100001;
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}
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void northbridge_write_smram(u8 smram)
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{
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pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram);
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}
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static struct device_operations mc_ops = {
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.read_resources = mc_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = northbridge_init,
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.ops_pci = &pci_dev_ops_pci,
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.acpi_fill_ssdt = generate_cpu_entries,
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};
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static const unsigned short pci_device_ids[] = {
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0x0100, 0x0104, 0x0108, /* Sandy Bridge */
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0x0150, 0x0154, 0x0158, /* Ivy Bridge */
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0
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};
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static const struct pci_driver mc_driver __pci_driver = {
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.ops = &mc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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static struct device_operations cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = mp_cpu_bus_init,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_intel_sandybridge_ops = {
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CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge")
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.enable_dev = enable_dev,
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};
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