sb/intel/common/pciehp: Replace HP dummy device with common code
Use the common PCIEXP_HOTPLUG code to generate a dummy device for PCIe ports supporting hotplug. This allows to have control over how much resources are allocated to hotplug ports. Tested on thinkpad X220: now hotplugging a dGPU via the expresscard slot sometimes works. Change-Id: I3eec5214c9d200ef97d1ccfdc00e8ea0ee7cfbc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph
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@ -65,4 +65,7 @@ config HIDE_MEI_ON_ERROR
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device will be hidden when ME is in an inoperable mode, e.g.
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device will be hidden when ME is in an inoperable mode, e.g.
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if me_cleaner was used.
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if me_cleaner was used.
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config PCIEXP_HOTPLUG
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default y
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endif
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endif
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@ -244,11 +244,11 @@ static void pch_pciexp_scan_bridge(struct device *dev)
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{
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{
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struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
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struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
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/* Normal PCIe Scan */
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if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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pciexp_scan_bridge(dev);
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pciexp_hotplug_scan_bridge(dev);
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} else {
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if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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/* Normal PCIe Scan */
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intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
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pciexp_scan_bridge(dev);
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}
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}
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/* Late Power Management init after bridge device enumeration */
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/* Late Power Management init after bridge device enumeration */
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@ -117,42 +117,3 @@ void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number)
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acpigen_pop_len();
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acpigen_pop_len();
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}
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}
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static void slot_dev_read_resources(struct device *dev)
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{
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struct resource *resource;
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resource = new_resource(dev, PCI_BASE_ADDRESS_0);
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resource->size = 1 << 23;
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resource->align = 22;
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resource->gran = 22;
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resource->limit = 0xffffffff;
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resource->flags |= IORESOURCE_MEM;
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resource = new_resource(dev, 0x14);
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resource->size = 1 << 23;
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resource->align = 22;
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resource->gran = 22;
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resource->limit = 0xffffffff;
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resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
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resource = new_resource(dev, 0x18);
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resource->size = 1 << 12;
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resource->align = 12;
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resource->gran = 12;
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resource->limit = 0xffff;
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resource->flags |= IORESOURCE_IO;
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}
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static struct device_operations slot_dev_ops = {
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.read_resources = slot_dev_read_resources,
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};
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/* Add a dummy device to reserve I/O space for hotpluggable devices. */
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void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus)
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{
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struct device *slot;
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struct device_path slot_path = { .type = DEVICE_PATH_NONE };
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slot = alloc_dev(bus, &slot_path);
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slot->ops = &slot_dev_ops;
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}
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@ -38,4 +38,7 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED
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bool
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bool
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default n
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default n
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config PCIEXP_HOTPLUG
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default y
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endif
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endif
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@ -63,11 +63,11 @@ static void pch_pciexp_scan_bridge(struct device *dev)
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{
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{
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struct southbridge_intel_i82801ix_config *config = dev->chip_info;
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struct southbridge_intel_i82801ix_config *config = dev->chip_info;
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/* Normal PCIe Scan */
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if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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pciexp_scan_bridge(dev);
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pciexp_hotplug_scan_bridge(dev);
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} else {
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if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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/* Normal PCIe Scan */
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intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
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pciexp_scan_bridge(dev);
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}
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}
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}
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}
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@ -39,4 +39,7 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED
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bool
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bool
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default n
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default n
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config PCIEXP_HOTPLUG
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default y
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endif
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endif
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@ -63,11 +63,11 @@ static void pch_pciexp_scan_bridge(struct device *dev)
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{
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{
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struct southbridge_intel_i82801jx_config *config = dev->chip_info;
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struct southbridge_intel_i82801jx_config *config = dev->chip_info;
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/* Normal PCIe Scan */
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if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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pciexp_scan_bridge(dev);
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pciexp_hotplug_scan_bridge(dev);
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} else {
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if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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/* Normal PCIe Scan */
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intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
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pciexp_scan_bridge(dev);
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}
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}
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}
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}
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