98 lines
2.8 KiB
C
98 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/pciexp.h>
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#include <device/pci_ids.h>
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#include <southbridge/intel/common/pciehp.h>
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#include "chip.h"
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static void pci_init(struct device *dev)
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{
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struct southbridge_intel_i82801ix_config *config = dev->chip_info;
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printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n");
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/* Enable Bus Master */
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
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/* Set Cache Line Size to 0x10 */
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// This has no effect but the OS might expect it
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pci_write_config8(dev, 0x0c, 0x10);
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pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
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/* Enable IO xAPIC on this PCIe port */
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pci_or_config32(dev, 0xd8, 1 << 7);
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/* Enable Backbone Clock Gating */
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pci_or_config32(dev, 0xe1, (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
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/* Set VC0 transaction class */
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pci_update_config32(dev, 0x114, ~0x000000ff, 1);
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/* Mask completion timeouts */
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pci_or_config32(dev, 0x148, 1 << 14);
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/* Lock R/WO Correctable Error Mask. */
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pci_update_config32(dev, 0x154, ~0, 0);
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/* Clear errors in status registers */
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pci_update_config16(dev, 0x06, ~0, 0);
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pci_update_config16(dev, 0x1e, ~0, 0);
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/* Get configured ASPM state */
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const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3;
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/* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
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if (apmc == PCIE_ASPM_BOTH)
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pci_or_config32(dev, 0xe8, 1 << 1);
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/* Enable expresscard hotplug events. */
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if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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pci_or_config32(dev, 0xd8, 1 << 30);
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pci_write_config16(dev, 0x42, 0x142);
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}
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}
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static void pch_pciexp_scan_bridge(struct device *dev)
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{
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struct southbridge_intel_i82801ix_config *config = dev->chip_info;
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if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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pciexp_hotplug_scan_bridge(dev);
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} else {
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/* Normal PCIe Scan */
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pciexp_scan_bridge(dev);
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}
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}
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static struct device_operations device_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = pci_init,
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.scan_bus = pch_pciexp_scan_bridge,
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.ops_pci = &pci_dev_ops_pci,
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};
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/* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_82801IB_PCIE1, /* Port 1 */
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PCI_DEVICE_ID_INTEL_82801IB_PCIE2, /* Port 2 */
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PCI_DEVICE_ID_INTEL_82801IB_PCIE3, /* Port 3 */
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PCI_DEVICE_ID_INTEL_82801IB_PCIE4, /* Port 4 */
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PCI_DEVICE_ID_INTEL_82801IB_PCIE5, /* Port 5 */
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PCI_DEVICE_ID_INTEL_82801IB_PCIE6, /* Port 6 */
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0
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};
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static const struct pci_driver ich9_pcie __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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