280 lines
6.6 KiB
C
280 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <device/pciexp.h>
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#include <device/pci_ids.h>
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#include <southbridge/intel/common/pciehp.h>
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#include <assert.h>
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#include "chip.h"
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#include "pch.h"
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static const char *pch_pcie_acpi_name(const struct device *dev)
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{
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ASSERT(dev);
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if (PCI_SLOT(dev->path.pci.devfn) == 0x1c) {
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static const char *names[] = { "RP01",
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"RP02",
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"RP03",
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"RP04",
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"RP05",
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"RP06",
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"RP07",
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"RP08"};
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return names[PCI_FUNC(dev->path.pci.devfn)];
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}
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return NULL;
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}
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static void pch_pcie_pm_early(struct device *dev)
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{
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u16 link_width_p0, link_width_p4;
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u8 slot_power_limit = 10; /* 10W for x1 */
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u32 reg32;
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u8 reg8;
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reg32 = RCBA32(RPC);
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/* Port 0-3 link aggregation from PCIEPCS1[1:0] soft strap */
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switch (reg32 & 3) {
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case 3:
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link_width_p0 = 4;
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break;
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case 1:
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case 2:
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link_width_p0 = 2;
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break;
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case 0:
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default:
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link_width_p0 = 1;
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}
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/* Port 4-7 link aggregation from PCIEPCS2[1:0] soft strap */
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switch ((reg32 >> 2) & 3) {
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case 3:
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link_width_p4 = 4;
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break;
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case 1:
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case 2:
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link_width_p4 = 2;
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break;
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case 0:
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default:
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link_width_p4 = 1;
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}
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/* Enable dynamic clock gating where needed */
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reg8 = pci_read_config8(dev, 0xe1);
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switch (PCI_FUNC(dev->path.pci.devfn)) {
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case 0: /* Port 0 */
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if (link_width_p0 == 4)
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slot_power_limit = 40; /* 40W for x4 */
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else if (link_width_p0 == 2)
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slot_power_limit = 20; /* 20W for x2 */
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reg8 |= 0x3f;
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break;
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case 4: /* Port 4 */
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if (link_width_p4 == 4)
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slot_power_limit = 40; /* 40W for x4 */
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else if (link_width_p4 == 2)
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slot_power_limit = 20; /* 20W for x2 */
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reg8 |= 0x3f;
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break;
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case 1: /* Port 1 only if Port 0 is x1 */
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if (link_width_p0 == 1)
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reg8 |= 0x3;
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break;
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case 2: /* Port 2 only if Port 0 is x1 or x2 */
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case 3: /* Port 3 only if Port 0 is x1 or x2 */
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if (link_width_p0 <= 2)
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reg8 |= 0x3;
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break;
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case 5: /* Port 5 only if Port 4 is x1 */
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if (link_width_p4 == 1)
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reg8 |= 0x3;
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break;
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case 6: /* Port 7 only if Port 4 is x1 or x2 */
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case 7: /* Port 7 only if Port 4 is x1 or x2 */
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if (link_width_p4 <= 2)
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reg8 |= 0x3;
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break;
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}
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pci_write_config8(dev, 0xe1, reg8);
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/* Set 0xE8[0] = 1 */
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pci_or_config32(dev, 0xe8, 1);
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/* Adjust Common Clock exit latency */
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reg32 = pci_read_config32(dev, 0xd8);
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reg32 &= ~(1 << 17);
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reg32 |= (1 << 16) | (1 << 15);
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reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */
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pci_write_config32(dev, 0xd8, reg32);
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/* Adjust ASPM L1 exit latency */
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reg32 = pci_read_config32(dev, 0x4c);
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reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15));
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if (RCBA32(CIR9) & (1 << 16)) {
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/* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */
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reg32 |= (1 << 17);
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} else {
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/* Else set ASPM L1 to 2-4us */
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reg32 |= (1 << 16);
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}
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pci_write_config32(dev, 0x4c, reg32);
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/* Set slot power limit as configured above */
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reg32 = pci_read_config32(dev, 0x54);
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reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */
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reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */
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reg32 |= (slot_power_limit << 7);
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pci_write_config32(dev, 0x54, reg32);
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}
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static void pch_pcie_pm_late(struct device *dev)
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{
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struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
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enum aspm_type apmc = 0;
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/* Set 0x314 = 0x743a361b */
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pci_write_config32(dev, 0x314, 0x743a361b);
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/* Set 0x318[31:16] = 0x1414 */
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pci_update_config32(dev, 0x318, 0x0000ffff, 0x14140000);
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/* Set 0x324[5] = 1 */
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pci_or_config32(dev, 0x324, 1 << 5);
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/* Set 0x330[7:0] = 0x40 */
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pci_update_config32(dev, 0x330, ~0xff, 0x40);
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/* Set 0x33C[24:0] = 0x854c74 */
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pci_update_config32(dev, 0x33c, 0xff000000, 0x00854c74);
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/* No IO-APIC, Disable EOI forwarding */
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pci_or_config32(dev, 0xd4, 1 << 1);
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/* Check for a rootport ASPM override */
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switch (PCI_FUNC(dev->path.pci.devfn)) {
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case 0:
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apmc = config->pcie_aspm_f0;
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break;
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case 1:
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apmc = config->pcie_aspm_f1;
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break;
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case 2:
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apmc = config->pcie_aspm_f2;
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break;
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case 3:
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apmc = config->pcie_aspm_f3;
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break;
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case 4:
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apmc = config->pcie_aspm_f4;
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break;
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case 5:
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apmc = config->pcie_aspm_f5;
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break;
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case 6:
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apmc = config->pcie_aspm_f6;
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break;
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case 7:
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apmc = config->pcie_aspm_f7;
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break;
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}
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/* Setup the override or get the real ASPM setting */
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if (apmc) {
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pci_or_config32(dev, 0xd4, (apmc << 2) | (1 << 4));
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} else {
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apmc = pci_read_config32(dev, 0x50) & 3;
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}
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/* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
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if (apmc == PCIE_ASPM_BOTH)
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pci_or_config32(dev, 0xe8, 1 << 1);
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}
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static void pci_init(struct device *dev)
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{
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u16 reg16;
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struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
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printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
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/* Enable Bus Master */
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
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/* Set Cache Line Size to 0x10 */
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// This has no effect but the OS might expect it
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pci_write_config8(dev, 0x0c, 0x10);
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pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY);
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/* Clear errors in status registers. FIXME: Do something? */
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reg16 = pci_read_config16(dev, 0x06);
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//reg16 |= 0xf900;
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pci_write_config16(dev, 0x06, reg16);
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reg16 = pci_read_config16(dev, 0x1e);
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//reg16 |= 0xf900;
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pci_write_config16(dev, 0x1e, reg16);
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/* Enable expresscard hotplug events. */
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if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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pci_or_config32(dev, 0xd8, 1 << 30);
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pci_write_config16(dev, 0x42, 0x142);
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}
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}
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static void pch_pcie_enable(struct device *dev)
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{
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/* Power Management init before enumeration */
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pch_pcie_pm_early(dev);
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}
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static void pch_pciexp_scan_bridge(struct device *dev)
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{
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struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
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if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
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pciexp_hotplug_scan_bridge(dev);
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} else {
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/* Normal PCIe Scan */
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pciexp_scan_bridge(dev);
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}
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/* Late Power Management init after bridge device enumeration */
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pch_pcie_pm_late(dev);
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}
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static struct device_operations device_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = pci_init,
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.enable = pch_pcie_enable,
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.scan_bus = pch_pciexp_scan_bridge,
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.acpi_name = pch_pcie_acpi_name,
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.ops_pci = &pci_dev_ops_pci,
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};
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static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16,
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0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
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0x1e10, 0x1e12, 0x1e14, 0x1e16,
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0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
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0 };
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static const struct pci_driver pch_pcie __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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