diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 812b6c052ee4..701c98bf152f 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -65,4 +65,7 @@ config HIDE_MEI_ON_ERROR
 	  device will be hidden when ME is in an inoperable mode, e.g.
 	  if me_cleaner was used.
 
+config PCIEXP_HOTPLUG
+	default y
+
 endif
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index f6bffbb3b9e9..851339082859 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -244,11 +244,11 @@ static void pch_pciexp_scan_bridge(struct device *dev)
 {
 	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 
-	/* Normal PCIe Scan */
-	pciexp_scan_bridge(dev);
-
-	if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
-		intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
+	if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
+		pciexp_hotplug_scan_bridge(dev);
+	} else {
+		/* Normal PCIe Scan */
+		pciexp_scan_bridge(dev);
 	}
 
 	/* Late Power Management init after bridge device enumeration */
diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c
index 247bf5df7fda..31fbb21c6359 100644
--- a/src/southbridge/intel/common/pciehp.c
+++ b/src/southbridge/intel/common/pciehp.c
@@ -117,42 +117,3 @@ void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number)
 	acpigen_pop_len();
 
 }
-
-static void slot_dev_read_resources(struct device *dev)
-{
-	struct resource *resource;
-
-	resource = new_resource(dev, PCI_BASE_ADDRESS_0);
-	resource->size = 1 << 23;
-	resource->align = 22;
-	resource->gran = 22;
-	resource->limit = 0xffffffff;
-	resource->flags |= IORESOURCE_MEM;
-
-	resource = new_resource(dev, 0x14);
-	resource->size = 1 << 23;
-	resource->align = 22;
-	resource->gran = 22;
-	resource->limit = 0xffffffff;
-	resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
-
-	resource = new_resource(dev, 0x18);
-	resource->size = 1 << 12;
-	resource->align = 12;
-	resource->gran = 12;
-	resource->limit = 0xffff;
-	resource->flags |= IORESOURCE_IO;
-}
-
-static struct device_operations slot_dev_ops = {
-	.read_resources   = slot_dev_read_resources,
-};
-
-/* Add a dummy device to reserve I/O space for hotpluggable devices.  */
-void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus)
-{
-	struct device *slot;
-	struct device_path slot_path = { .type = DEVICE_PATH_NONE };
-	slot = alloc_dev(bus, &slot_path);
-	slot->ops = &slot_dev_ops;
-}
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 3ee29430907c..992562f5b9a0 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -38,4 +38,7 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED
 	bool
 	default n
 
+config PCIEXP_HOTPLUG
+	default y
+
 endif
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index 3900e92bf55f..a20e7d6dc46b 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -63,11 +63,11 @@ static void pch_pciexp_scan_bridge(struct device *dev)
 {
 	struct southbridge_intel_i82801ix_config *config = dev->chip_info;
 
-	/* Normal PCIe Scan */
-	pciexp_scan_bridge(dev);
-
-	if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
-		intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
+	if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
+		pciexp_hotplug_scan_bridge(dev);
+	} else {
+		/* Normal PCIe Scan */
+		pciexp_scan_bridge(dev);
 	}
 }
 
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index 687cb4592483..fa469ce0ae7e 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -39,4 +39,7 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED
 	bool
 	default n
 
+config PCIEXP_HOTPLUG
+	default y
+
 endif
diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c
index 18d2c7232188..133d50235d7e 100644
--- a/src/southbridge/intel/i82801jx/pcie.c
+++ b/src/southbridge/intel/i82801jx/pcie.c
@@ -63,11 +63,11 @@ static void pch_pciexp_scan_bridge(struct device *dev)
 {
 	struct southbridge_intel_i82801jx_config *config = dev->chip_info;
 
-	/* Normal PCIe Scan */
-	pciexp_scan_bridge(dev);
-
-	if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
-		intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
+	if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
+		pciexp_hotplug_scan_bridge(dev);
+	} else {
+		/* Normal PCIe Scan */
+		pciexp_scan_bridge(dev);
 	}
 }