This makes the headers visible to the Zephyr build.
BUG=b:173798264
BRANCH=none
TEST=buildall
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I3b6d27c1234b3924ee8902a86eec5fdb2ccd9998
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2571897
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
To further improve the time to enter alternate modes, limit the number
of SOP' DiscID retries that are performed before a contract is in place.
This ensures interoperability with captive cable devices that cannot
respond to SOP' until a contract is established.
BUG=b:169741906, b:166650426
BRANCH=firmware-volteer-13521.B-master
TEST=Connect TBT3 loopack device and verify TBT mode is entered.
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I007780df567cd0e66236b2c3067d065eecf07fe1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2550307
Reviewed-by: Diana Z <dzigterman@chromium.org>
BUG=b:169532537
TEST=amon; ensure the report current is accurate comapres to the
power meter
BRANCH=none
Change-Id: I43f98db84f362f0331b128475c9cea955c18f163
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2569082
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
A pre-processing CL for the charger_get_input_current API.
BUG=b:169532537
TEST=make buildall
BRANCH=none
Change-Id: Iec7baeb32e0d8f7f6c7260fada8a78d920cc325e
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2569081
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Add support for "Revision 2 add-in card" to enable Chrome EC,
on AlderLake reference platform.
BRANCH=None
BUG=b:174290307
TEST=Build, flash and boot the Alderlake RVP platform to OS
make BOARD=adlrvpp_ite -j;
sudo util/flash_ec --board=adlrvpp_ite --image=<path>
Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com>
Change-Id: I314ed281b12f41c1539afb9716301af6fd7ede26
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2544294
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
When running 'fakedisconnect' command on ServoV4, CC_DETACH bit is
going to be set. Detach is done by calling pd_power_supply_reset()
which disables VBUS (set DUT_CHG_EN to 0) and requests 5 volts from
charger. Next step is disable PD communication by calling
pd_comm_enable() and set RP to RP_RESERVED value (pd_set_rp_rd()
function).
Setting RP to RP_RESERVED (just disconnect all resistors on CC1 and CC2)
actually is a trick to make PD_C1 task think that DUT is disconnected.
TCPM stack checks voltage on CC lines and when voltage on active CC line
indicates that we are open it changes state to SRC_DISCONNECTED.
Changing state to SRC_DISCONNECTED triggers pd_power_supply_reset()
which was already run in do_cc() function as a result of 'fakedisconnect'
command. Calling this once again causes weird behaviour - communication
issues and finally Hard Reset, eg:
> fakedisconnect 100 1000
Fake disconnect for 1000 ms starting in 100 ms.
C0 Req [1] 5000mV 3000mA
[210.470350 CL: p0 s0 i500 v15000]
[210.472703 PD TMOUT RX 1/1]
RXERR1 Preamble
C1 srcCAP>-1
C1 srcCAP>-1
C1 st14 SRC_DISCONNECTED
[210.473835 PD TMOUT RX 467/1]
RXERR0 Preamble
C0 REQ>1
C0 st6 SNK_REQUESTED
C0 st34 HARD_RESET_SEND
C0 st35 HARD_RESET_EXECUTE
C0 HARD RST TX
Hard Reset in PD_C0 task can cause additional delay when C1 gets
connected and DUT requests higher voltage. As a result DUT sends Hard
Reset due to timeout. Hard Reset on port 1 causes PDTrySrc to fail
because of timeout waiting for 'fakedisconnect' command.
This was fixed by removing one voltage change request. In other words in
do_cc() function we are not calling pd_power_supply_reset(), but
disabling VBUS only. Eventually pd_power_supply_reset() will be called during
transition to SRC_DISCONNECT state.
BUG=b:162254118
BRANCH=none
TEST=Run FAFT_PD test suite. All tests should pass except PDVbusRequest
(depends on charger connected to ServoV4).
TEST=Call 'fakedisconnect' command on ServoV4 console and check if there
is no Hard Reset on port 0.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I657dd1ce2dc3a2f4914e975387eeebb037e1ada5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2569652
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Note that this CL update DB FW_CONFIG according to crrev.com/c/2548269
since lantis's EC image was initialed with drawcia's EC image.
BUG=b:171742626
BRANCH=dedede
TEST=Load on lantis and confirm correct number of PD ports up.
Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com>
Change-Id: I373fd0bd6bcd31e6355734a354d9be1ce9fe3aa9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2562917
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Devin Lu <Devin.Lu@quantatw.com>
BRANCH=None
BUG=b:169551130
TEST=PWM fan is able to run
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: Ie042402803e5cd18780951b2efe89eae033126aa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563422
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: Sooraj Govindan <sooraj.govindan@intel.com>
Both 3.3A & 5VA rail come up or go down together by EC_DS4 signal
hence removed PP5000 rail config.
BRANCH=None
BUG=b:169551130
TEST=make build all; Tested on ADLRVP
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: I7c3a66b53ada616071998d111bf822a5b7fbcc81
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563425
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: Sooraj Govindan <sooraj.govindan@intel.com>
The line board_get_version() inside board_hibernate_late() fails if it
is the first board_get_version() call, because ADC (or some function
related to it) is not usable at that time.
To fix this, cache board id to ensure board_hibernate_late() never need to
access ADC.
Also replace #include <...> to #include "..." for consistency.
BUG=b:163963220
TEST=hibernate successful in G3
BRANCH=none
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I0c277cccd081906d6f87793e8e4f1980a4e55c3a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567458
Tested-by: Ting Shen <phoenixshen@chromium.org>
Auto-Submit: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Commit-Queue: Eric Yilun Lin <yllin@chromium.org>
If we fail to enter z-state, this likely indicates that the z-state
circuitry is in a state from which wake sources will not work. This
would mean the EC would hibernate until a refresh+power sequence is run.
Instead, choose to reset the system with the AP off. The battery will
drain more quickly, but will be able to turn on when the power button is
pressed normally.
BRANCH=dedede
BUG=b:166476907
TEST=on drawcia, remove C1 interrupt line sharing and wedge line low.
Ensure "hibernate" run on the EC console from both S0 and G3 results in
a reset with the AP off, and the system can be turned on with a power
button press. Run with normal C1 interrupt line sharing in place and
verify "hibernate" enters z-state as expected in S0 and G3.
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I8408522dd1b0bbbce6f4e2bf6d0c550febd27bbf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567582
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
According to some experiments, the current delays are not enough on
some boards. Add larger margin to the value. Also do the same on the
power-off sequence delay.
BRANCH=Trogdor
BUG=b:163613549
TEST=Made DUT transit to DEV mode and the next auto-boot worked fine.
Change-Id: Ia72c725fe1e8ff795e637e1b4b99b097478bcc1a
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2565635
Commit-Queue: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
BUG=b:174106425
BRANCH=firmware-volteer-13521.B
TEST=make BOARD=delbin
make BOARD=delbin_npcx796fc
Change-Id: I516994793db07f544ac64065aa05e7adacf6a39d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567067
Reviewed-by: YH Lin <yueherngl@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
This reverts commit 09a4117708.
BUG=b:174106425
BRANCH=firmware-volteer-13521.B
TEST=make buildall
Change-Id: Icc898a720cbdb79d4c08fca7d2da42d4dc96786d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567066
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
As most of the peripherals were not implemented to support switching to
16-MHz HSI (e.g. high speed serial port requires a clock input > 24
Mhz), implement a simpler clock scheme than the dynamic between HSI and
PLL used other platforms:
- the PLL is disabled only when entering the low-power idle and the PLL
locking time is added to wake-up time.
- when the host is running (not suspended) we stay in a high power mode
(~20mW).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, on bloonchipper, check we can still capture fingerprint.
read the MCU power consumption: pp3300_dx_mcu_mw is 2.367 mW.
BRANCH=fpmcu-bloonchipper
Change-Id: Ic1fe015b2501bdea9779a2f63fab296f8812c315
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2555162
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Implement a low power idle mode using the STM32F4 STOP mode.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, on bloonchipper, check we can still capture fingerprint.
read the MCU power consumption.
BRANCH=fpmcu-bloonchipper
Change-Id: I11249e9b68c989033263e34e1cde3f19ffe7c54c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2537631
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
On STM32F4, when converting micro-seconds to the RTC sub-second counter
value, the current computation in the us_to_rtcss() routine has a large
rounding error which can even led to generate a negative value.
When such a negative value is output and then programmed in the
(unsigned) RTC_ALRMASSR register used to set the alarm precise
sub-second timestamp, it might put a wrong value in the past.
As a consequence when the RTC alarm is used a wake-up mechanism for the
low power idle, it might never fired and trigger a watchdog reboot.
An example of bad values on a STM32F412 with the RTC driven by the
32-kHz LSI:
- RTC_PREDIV_A = 1
- RTC_FREQ = (STM32F4_LSI_CLOCK / (RTC_PREDIV_A + 1) = 16000 /* Hz */
- RTC_PREDIV_S = (RTC_FREQ - 1) = 15999
- US_PER_RTC_TICK = 1000000 / RTC_FREQ = 62 /* rounded from 62.5 */
When converting 996000 us,
us_to_rtcss(996000) = RTC_PREDIV_S - (us / US_PER_RTC_TICK)
= 15999 - (996000 / 62)
= -65
returned as a uint32_t as 0xfffffffb.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, with the STOP mode enabled, we no longer see watchdog
reboot due to the RTC alarm being set in the past and never firing.
TEST=manual, verify that the output of the 'gettime' console command is not
drifting compared to the wall clock when the low power idle using the
RTC time is used.
BRANCH=fpmcu-bloonchipper
Change-Id: I53869539828bed9a5900d29407b5feba140b8217
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563684
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Allow to transition between the PLL to run at full speed
and the bare HSI (internal RC oscillator at 16Mhz) to save power.
On HSI, as our sysclk frequency is low, we run all peripheral clocks
undivided at the same frequency.
Keep the configuration for other platforms running from the HSE
(external crystal)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, verify the timers are working by checking the output of the
'gettime' console command against the wall clock.
TEST=manual, verify the UART console works as expected.
TEST=measure MCU power on bloonchipper in various modes through the INA:
PLL 19.20 mW HSI 4.73 mW STOP 2.10 mW
BRANCH=fpmcu-bloonchipper
Change-Id: I1185e04c9a7819fec05dd643b7026116b146f3b8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2527049
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Add support for changing for the timer source clock frequency on
STM32F4 by re-computing the timer pre-scaler value in the
HOOK_FREQ_CHANGE callback.
Preparatory work to implement power management switching between PLL and
HSI as sysclk.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, verify the output of the 'gettime' console command against
the wall clock.
BRANCH=fpmcu-bloonchipper
Change-Id: Ia7dc24d3b1dbff816b1cebbc87492e678b987dfd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2527048
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
fix usb type-a bc1.2 charging
BUG=b:173093980
BRANCH=firmware-volteer-13521.B
TEST=make buildall, test usb type-a charging and usb function work normally
Signed-off-by: jerry2.huang <jerry2.huang@lcfc.corp-partner.google.com>
Change-Id: I60aadcac58ccbfe86d7005db506788a13d6fe4c9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2557759
Reviewed-by: Keith Short <keithshort@chromium.org>
1.fix c1 charging and usb function
2.remove USB4 and cleaning up the TCPC,PPC,and USB mux configuration
BUG=b:173093980
BRANCH=firmware-volteer-13521.B
TEST=make buildall, test c1 charging and usb function work normally
Signed-off-by: amber.chen <amber.chen@lcfc.corp-partner.google.com>
Change-Id: Ic49d6dfee0e977885e5098dd9d71b89cf19410f8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2549000
Tested-by: jerry2.huang <jerry2.huang@lcfc.corp-partner.google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
This gives us the "apreset" and "apshutdown" console commands.
BUG=b:171312361
BRANCH=none
TEST=try "apreset" and "apshutdown" commands on volteer
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: Ib71afa66cfb5d0044c4cf98839b263ee2e2da338
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567343
Commit-Queue: Yuval Peress <peress@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>
Since the thermal concern has already been solved, we don't have to
limit C1 charging current to 2A in lantis.
BUG=b:161942987
BRANCH=dedede
TEST=In lantis, make sure that C1 charging current is not limited
to 2A.
Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com>
Change-Id: I9c3e13b2e1fa2acaeb9dfae17f8ed1639550689b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2557283
Reviewed-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Create the initial EC image for the copano variant by copying the
terrador reference board EC files into a new directory named for
the variant.
(Auto-Generated by create_initial_ec_image.sh version 1.3.0).
BUG=b:174413884
BRANCH=None
TEST=make BOARD=copano
Signed-off-by: Jacky Wang <jacky5_wang@pegatron.corp-partner.google.com>
Change-Id: I463b3087d1a66ccf0325bc8ac369349fbb9ac307
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2565218
Reviewed-by: Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
When run the FAFT firmware_ECUsbPorts, getting the fail result.
The program can detect pin EN_USB_A_5V using the config file
strongbad.json. But coachz board not support USB-A,
therefore we modify the gpio to unused signals.
BUG=b:168868418
BRANCH=none
TEST=make BOARD=coachz
Signed-off-by: Jennifer Wang <jenniferchwang@ami.corp-partner.google.com>
Change-Id: I017615c0afb8fba4e48d87201096ad1de38d3e9f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563355
Reviewed-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Commit-Queue: Bob Moragues <moragues@chromium.org>
Tested-by: Bob Moragues <moragues@chromium.org>
CL:2558905 broke our build as it renamed this file. Update the name
here too.
BUG=b:174572350
BRANCH=none
TEST=build for volteer
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I96c0922a988df05b8935b169781b809bd4425b7d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567586
Commit-Queue: Diana Z <dzigterman@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
We were casting the int to a pointer. Needed '&'.
BRANCH=none
BUG=none
TEST=zmake testall (but it still fails on missing cros_kb_raw.h
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I9d61fb27826c581214d5557364a97e6ea9d215e8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567583
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Apply changes in CL:2566813 to ServoV4P1 too. Original message below.
When ServoV4 acts as sink ('cc snk' issued), and we issue 'cc pdsnk'
there are following state transitions (starting from C1 SNK_READY):
C1 st8 SNK_READY <--- From this point DUT acts as source
DUT's PE is in PE_SRC_Ready state
C1 RECV 196f/1 [0]ff008001
C1 RECV 0b67/0 <--- DUT asks for source capabilities
C1 srcCAP>1 <--- ServoV4 sends its capabilities
C1 RECV 0d6a/0 <--- DUT requests power swap
C1 CTRL[3]>1 <--- ServoV4 accepts
C1 st10 SNK_SWAP_SNK_DISABLE
C1 st11 SNK_SWAP_SRC_DISABLE
C1 RECV 0e66/0 <--- DUT sends PS_RDY to inform that it
disabled power
C1 st12 SNK_SWAP_STANDBY <--- ServoV4 enables power supply and waits
PD_POWER_SUPPLY_TURN_ON_DELAY to ensure
that it is turned on, before switching
to SNK_SWAP_COMPLETE
C1 st13 SNK_SWAP_COMPLETE <--- Power swap completed successfully
C1 CTRL[6]>1 <--- ServoV4 sends PS_RDY to inform that
power was enabled.
C1 st18 SRC_DISCOVERY
C1 srcCAP>1 <--- ServoV4 sends its capabilities
C1 st19 SRC_NEGOCIATE
C1 RECV 1062/1 [0]4304b12c
Requested 15000 mV 3000 mA (for 3000/3000 mA)
C1 CTRL[3]>1 <--- ServoV4 accepts
C1 st20 SRC_ACCEPTED
C1 st21 SRC_POWERED <--- Switching to requested voltage. This
calls pd_transition_voltage() from
servo_v4/usb_pd_policy which requests
charger to change its voltage.
[570.815776 Waiting for CHG port transition]
<--- Here we are changing active task to
PD_C0. This task changes dual role
for C1 (DUT port), because CC_ALLOW_SRC
is not set. Appropriate event is set too
C0 Req [4] 15000mV 3000mA
C0 REQ>1
C0 st6 SNK_REQUESTED
[570.822679 CL: p0 s0 i500 v5000]
C0 RECV 0763/0
C0 st7 SNK_TRANSITION
C0 RECV 0966/0
C0 st8 SNK_READY <--- Charger voltage changed successfully
[570.991969 CL: p0 s0 i3000 v15000]
<--- Context switch to PD_C1 task
[571.001981 CHG transitioned]
<--- Check event and call
update_dual_role_config() which
changes state to SNK_DISCONNECTED
C1 st2 SNK_DISCONNECTED
Port 1 switches to SNK_DISCONNECTED state because PD_C0 task calls
pd_send_request_msg() (reaction for voltage change request), which
limits maximum current by calling charge_manager_force_ceil().
Charge manager calls board_set_charge_limit() to limit current, which
calls update_ports() which calls board_manage_dut_port()
unconditionally. This function checks if charge through is allowed. It
turns out that it is not allowed, because CC_ALLOW_SRC bit is not set
in cc_config (see is_charge_through_allowed()), then
board_manage_dut_port() changes dual role of port 1 to force sink.
Fix for this issue is simple. Function is_charge_through_allowed()
actually tells us that we are not able to source power when 'cc snk' or
'cc pdsnk' was issued. So fix is just to reject power swap when our
power role is sink, and CC_ALLOW_SRC is not set.
BUG=b:162254118
BRANCH=none
TEST=Issue 'cc snk' from ServoV4 console and wait until state gets
stable. Issue 'cc pdsnk' from ServoV4 console and check if port 1
reaches SNK_READY state.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: Iadf41bbb82d300bc05c1528a403267225a6907d4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2566991
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
Wake the PD task from pe_message_received(), pe_message_sent(), and
pe_report_error() to avoid having to wait USBC_EVENT_TIMEOUT.
BUG=none
BRANCH=none
TEST=make run-usb_pe_drp
Signed-off-by: Edward Hill <ecgh@chromium.org>
Change-Id: I2fd1465796224507e1eb64ea20572165918d5bf3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2564818
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Add a test for the other half of handling an error on sending
source capabilities. Before connection, PE_SRC_Send_Capabilities
goes to PE_SRC_Discovery on send error. Once connected, to goes
to PE_Send_Soft_Reset.
BUG=b:161835483
BRANCH=none
TEST=make run-usb_pe_drp
Signed-off-by: Edward Hill <ecgh@chromium.org>
Change-Id: I92df9159286536bdda76e5b8530494c6aa368af1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2553344
Reviewed-by: Diana Z <dzigterman@chromium.org>
When ServoV4 acts as sink ('cc snk' issued), and we issue 'cc pdsnk'
there are following state transitions (starting from C1 SNK_READY):
C1 st8 SNK_READY <--- From this point DUT acts as source
DUT's PE is in PE_SRC_Ready state
C1 RECV 196f/1 [0]ff008001
C1 RECV 0b67/0 <--- DUT asks for source capabilities
C1 srcCAP>1 <--- ServoV4 sends its capabilities
C1 RECV 0d6a/0 <--- DUT requests power swap
C1 CTRL[3]>1 <--- ServoV4 accepts
C1 st10 SNK_SWAP_SNK_DISABLE
C1 st11 SNK_SWAP_SRC_DISABLE
C1 RECV 0e66/0 <--- DUT sends PS_RDY to inform that it
disabled power
C1 st12 SNK_SWAP_STANDBY <--- ServoV4 enables power supply and waits
PD_POWER_SUPPLY_TURN_ON_DELAY to ensure
that it is turned on, before switching
to SNK_SWAP_COMPLETE
C1 st13 SNK_SWAP_COMPLETE <--- Power swap completed successfully
C1 CTRL[6]>1 <--- ServoV4 sends PS_RDY to inform that
power was enabled.
C1 st18 SRC_DISCOVERY
C1 srcCAP>1 <--- ServoV4 sends its capabilities
C1 st19 SRC_NEGOCIATE
C1 RECV 1062/1 [0]4304b12c
Requested 15000 mV 3000 mA (for 3000/3000 mA)
C1 CTRL[3]>1 <--- ServoV4 accepts
C1 st20 SRC_ACCEPTED
C1 st21 SRC_POWERED <--- Switching to requested voltage. This
calls pd_transition_voltage() from
servo_v4/usb_pd_policy which requests
charger to change its voltage.
[570.815776 Waiting for CHG port transition]
<--- Here we are changing active task to
PD_C0. This task changes dual role
for C1 (DUT port), because CC_ALLOW_SRC
is not set. Appropriate event is set too
C0 Req [4] 15000mV 3000mA
C0 REQ>1
C0 st6 SNK_REQUESTED
[570.822679 CL: p0 s0 i500 v5000]
C0 RECV 0763/0
C0 st7 SNK_TRANSITION
C0 RECV 0966/0
C0 st8 SNK_READY <--- Charger voltage changed successfully
[570.991969 CL: p0 s0 i3000 v15000]
<--- Context switch to PD_C1 task
[571.001981 CHG transitioned]
<--- Check event and call
update_dual_role_config() which
changes state to SNK_DISCONNECTED
C1 st2 SNK_DISCONNECTED
Port 1 switches to SNK_DISCONNECTED state because PD_C0 task calls
pd_send_request_msg() (reaction for voltage change request), which
limits maximum current by calling charge_manager_force_ceil().
Charge manager calls board_set_charge_limit() to limit current, which
calls update_ports() which calls board_manage_dut_port()
unconditionally. This function checks if charge through is allowed. It
turns out that it is not allowed, because CC_ALLOW_SRC bit is not set
in cc_config (see is_charge_through_allowed()), then
board_manage_dut_port() changes dual role of port 1 to force sink.
Fix for this issue is simple. Function is_charge_through_allowed()
actually tells us that we are not able to source power when 'cc snk' or
'cc pdsnk' was issued. So fix is just to reject power swap when our
power role is sink, and CC_ALLOW_SRC is not set.
BUG=b:162254118
BRANCH=none
TEST=Issue 'cc snk' from ServoV4 console and wait until state gets
stable. Issue 'cc pdsnk' from ServoV4 console and check if port 1
reaches SNK_READY state.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: Idf89c0f79a60275345d23aca4705811b1acba98a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563682
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Sam Hurst <shurst@google.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
When ServoV4 acts as sink ('cc snk' issued), and we issue 'cc pdsnk'
there are following state transitions:
> cc pdsnk
C1 st2 SNK_DISCONNECTED
C1 st3 SNK_DISCONNECTED_DEBOUNCE
C1 st5 SNK_DISCOVERY
C1 RECV 1361/1 [0]2601912c
C1 Req [1] 5000mV 3000mA
C1 REQ>1
C1 st6 SNK_REQUESTED
C1 RECV 0563/0
C1 st7 SNK_TRANSITION
C1 RECV 0766/0
C1 st8 SNK_READY <--- From this point DUT acts as source
DUT's PE is in PE_SRC_Ready state
C1 RECV 196f/1 [0]ff008001
C1 RECV 0b67/0 <--- DUT asks for source capabilities
C1 srcCAP>1 <--- ServoV4 sends its capabilities
C1 RECV 0d6a/0 <--- DUT requests power swap
C1 CTRL[3]>1 <--- ServoV4 accepts
C1 st10 SNK_SWAP_SNK_DISABLE
C1 st11 SNK_SWAP_SRC_DISABLE
C1 RECV 0e66/0 <--- DUT sends PS_RDY to inform that it
disabled power
C1 st12 SNK_SWAP_STANDBY <--- ServoV4 enables power supply and waits
PD_POWER_SUPPLY_TURN_ON_DELAY to ensure
that it is turned on, before switching
to SNK_SWAP_COMPLETE
C1 st14 SRC_DISCONNECTED <--- This is not expected state, DUT is still
waiting for PS_RDY from ServoV4
C1 st15 SRC_DISCONNECTED_DEBOUNCE
C1 st17 SRC_STARTUP
C1 st18 SRC_DISCOVERY
C1 srcCAP>1 <--- ServoV4 tries to negotiate, but DUT is
still waiting for PS_RDY
C1 st19 SRC_NEGOCIATE
C1 st34 HARD_RESET_SEND <--- Negotiation timeout
C1 st35 HARD_RESET_EXECUTE
DUT requests power swap which is interrupted by wrong state transition.
SNK_SWAP_STANDBY state should be switched to SNK_SWAP_COMPLETE, but
instead of it switched to SRC_DISCONNECTED, this is caused by changing
DRP state to force source in pd_set_power_supply_ready() called in
SNK_SWAP_STANDBY state. Changing DRP state also sets
PD_EVENT_UPDATE_DUAL_ROLE, which causes state transition (performed in
pd_update_dual_role_config() function), because power role is still
PD_ROLE_SINK, but DRP is now force source.
This was fixed by adding requirement that we should not perform power
swap, because we are going to change our power role in SNK_SWAP_COMPLETE
actually.
BUG=b:162254118
BRANCH=none
TEST=Issue 'cc snk' on ServoV4 console, wait until it reaches stable
state. Issue 'cc pdsnk' and check if SNK_SWAP_COMPLETE state comes
after SNK_SWAP_STANDBY
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I0ffd6ef79d59ca7fcb0dd1357dd491fe852b7461
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563681
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
It is replaced by the hdctools in all current configurations (servod
based development).
BUG=none
TEST=none
Change-Id: I56d97d776a8c2aaf47aa39802cc9831c4f3416a7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2560631
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Create the initial EC image for the delbin_npcx796fc variant by
copying the delbin reference board EC files into a new directory
named for the variant.
(Auto-Generated by create_initial_ec_image.sh version 1.3.0).
BUG=b:174106425
BRANCH=firmware-volteer-13521.B
TEST=make BOARD=delbin_npcx796fc
Signed-off-by: Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com>
Change-Id: I97529b787246f74765e29d9ceab275431be28767
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567074
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Create the initial EC image for the sasuke variant by copying the
waddledoo reference board EC files into a new directory named for
the variant.
(Auto-Generated by create_initial_ec_image.sh version 1.3.0).
BUG=b:172104731
BRANCH=None
TEST=make BOARD=sasuke
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I0bf2096e91a17d2b9b842128665b454ab1d77f35
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2562913
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Henry Sun <henrysun@google.com>
Dock is requesting a PR_Swap to become our SRC
and, after accepting this, the dock sends a VDM
Attention instead of the expected PS_RDY. Since
we are past the initial PR_Swap/Accept, this is
no longer handled as a Power Transition state
and a SoftReset will be used.
BUG=b:170265589
BRANCH=zork
TEST=use test in bug
Signed-off-by: Denis Brockus <dbrockus@google.com>
Change-Id: I7afabbf3dc9cffb60de332b8eba38ee40b93d8ba
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2565695
Tested-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Auto-Submit: Denis Brockus <dbrockus@chromium.org>
ADL SOC has a TDP of 45W and the RVP can support up to
200W power.Hence, increased the power support to 100W.
BRANCH=None
BUG=b:173081793
TEST=use chgsup command and list charger type negotiated values.
Tested below on ADL:
When Typec Charger connected to Port3:
> chgsup
port=3, type=0, cur=3000mA, vtg=20000mV, lsm=1
when TBT dock connected to Port1:
> chgsup
port=1, type=0, cur=4500mA, vtg=20000mV, lsm=1
when AC charger connected:
> chgsup
port=4, type=3, cur=5263mA, vtg=19000mV, lsm=0
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: I0677519a68013dbc593539b692bad5016b52654f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531771
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Shim in the port80 module.
BUG=b:172471337
BRANCH=none
TEST=boot volteer, watch the port80 writes
test port80 command
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I35e3254bb95fec92e4b69ca65f1d8eebbc6d14f1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567033
Commit-Queue: Yuval Peress <peress@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>
It shims the keyboard_scan task by introducing another keyboard_raw.c
which calls down to the zephyr-chrome cros_kb_raw driver.
BRANCH=none
BUG=b:167405015
TEST=Build pass by zmake configure -B ./build projects/experimental/volteer.
TEST=Check all the keys on volteer platform by "ksstate".
Change-Id: Ic87f67c28779f7feafa350020a07ba87e3600ecd
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2523839
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Jack Rosenthal