Flash Descriptor and Management Engine blobs extracted from stock.
Microcodes from public GitHub repository, as Intel doesn't carry
microcode for D0 stepping in their tree.
Change-Id: I9ee9e031969b477d2d9f63f7e49a113bd4380f91
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
To sync DRAMC_PARAM_HEADER_VERSION with CB:61132 and CB:62549, update
dram.elf from ChromeOS build 15692.0.0.
BUG=b:315082772
Change-Id: I2ec5b724cf69892f04eea3c512cb28efafc02031
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Quark was removed from the coreboot repo several months ago. The
submodule pointer for the 4.20 branch will still contain these blobs,
so they can be removed from ToT.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id13ce993f6d0e397ad0b8f84de7773129f2de2f0
This patch includes following changes:
- Simplify the timer driver by using ARM ARCH timer.
- Bump FIRMWARE_BUILD_VER to 2
BUG=b:229800119
TEST=check cbmem timestamp; pass FAFT test.
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: I1dde73b753d6db36f569522352cc728be840a836
From mid-2022, EC updates were bundled into coreboot using the
ITE mirror protocol, leading to individual binaries being added
solely to the blobs repo.
This made separate version histories redundant. To simplify
tracking, the old history has been removed, centralizing
all changes in the blobs repository.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icdac82a0dfd90559a9a7d9808b3fb57a164d121f
Add signed verstage files previously held within the chromium repo to align with our upstream first philosophy.
BUG=None
TEST=builds
Change-Id: I3ce54d2bbd84a9b0b0ed070fde86d91cd0c8c6a9
Signed-off-by: Jon Murphy <jpmurphy@google.com>
The bug was discussed in CB:31074, referred to as "off-by-one" error.
AGESA looks for ROM signature of the firmware table at 5 offsets
instead of all 6 possible offsets. As a result placing the AMD firmware
with amdfwtool at offset FFFA0000 will lead to the incorrect xHCI
controller initialization by not loading the xHCI firmware from the
firmware table.
Increase the loop iterations to 6 in order to allow offset FFFA0000 to
be checked for ROM signature presence. The goal is to save even more
space in the SPI flash by putting the AMD firmware at the highest possible
address. The bug was present in both AGESA 1.0.0.A and 1.0.0.4 used by
PC Engines apu2 platforms.
TEST=Set the AMD FW offset to FFFA0000, build apu2 firmware and check
whether xHCI controller appears in lspci on Linux and USB 3.0 devices get
enumerated properly.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7d81998b34c24d8294c81631224d92133bb67f24
This script helps to prepare the PSP verstage for signing as per
guidelines from AMD BIOS Signing Key Pair and Certification Process
document.
BUG=None
TEST=Build Skyrim BIOS image and ensure that the prepared verstage
binary built as part of coreboot is ready for signing.
Change-Id: I1d0997364ff4f89feed26ed1611108258845f0e9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Co-authored-by: Kangheui Won <khwon@google.com>
Co-authored-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
1.13
Increase the charging speed to 1C when temperatures allow
Reduce the amount of variables polled via the SMBus
Fixed an issue when batteries would not exit shipping mode
1.12
Revert the charging rate to 0.5C
Store the state of charging at 0xa0
1.11
Adjust the threshold for Hybrid Power to 1536MA
Adjust the threshold for Hybrid Power to be disable to 5 percent RSOC
1.10
Disable Hybrid Power when the RSOC is less than 20 percent
Only enable LEARN once when RSOC is greater than 50 percent
Dont query unused registers on the BQ24780S
1.07
Disable PD requests when a normal USB-C device is connected
Account for having two chargers connected
Optimise the charging calculations
1.06
Strip PD responses to only include valid bits
1.05
Fix the charging voltage to 13.2V
Only call Anx when USB-C PD chargers are connected
Disable Hybrid-Power when charging current is less that 1536
1.04
Store power related variables in the EC RAM and mirror them to EC memory
to avoid memory overflow to mitigate some strange behaviours when the EC
memory overflows
1.03
Improved the reliability of DC Jack charging by modifying it to 800MHz, 3A
Avoided charging stalling by continuously polling the SMBus after overcharge
protection is active
Exposed the behavior of overcharge protection to APCI
Set the charge LED to purple when overcharge protection is active
Modified fan curve
Ensured the trackpad is in the desired state by polling its state every 10ms
Set the brightness of the keyboard backlight to the maximum
Streamlined the system by removing unused SMM events
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3b08cb8b2b4e9e9836cd7e8c545fc83b2e0e3f99
This version adds scramble switch to support both production build and
serial build, and also fixes fast-k single rank wrong register bit.
BUG=b:269049451,b:267590318
TEST=Single rank DRAM suspend/resume pass, enable/disable scramble pass
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I7bf751e19d6df32bbd40b9dacad16fb99253d2ae
In addition to DRAM, DPM also needs to handle scramble enable or
disable.
BUG=b:269049451
TEST=build pass and confirm enable/disable scramble successfully
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I291376edacfd4ae959764dbeb9b5b03739e3f4d5
Update CPU DVFS OPP table to enhance power saving. The current CPU OPP
voltage is conservative, so CPU OPP voltage can be further optimized for
power saving.
TEST=get "MediaTek MCUPM firmware: version 1.01.04" string by
`strings mcupm.bin | grep -i media`
TEST=boot to shell.
BUG=NONE
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.corp-partner.google.com>
Change-Id: I2dbb67f3b72f4fe7de2418189ae79f2e3694d9fa
Fix the PMIC MT6315 id bug when registering the MT6315 regulator.
BUG=b:249436110
TEST=Video playback works well on MT8186 and MT8186T Steelix after
executing suspend_stress_test.
TEST=get "MediaTek SSPM firmware: version 2.0.1" by
strings sspm.bin | grep version
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Change-Id: Ib5d3612ac488aa41a9bcd61ad1e59048d395a3ef
ChromeOS requires a RO SPL table. Add it here so that it can be linked
in coreboot.
The SPL table contains a set of version numbers to prevent rollback
attacks. Updates with a value lower than the value in the table are
not allowed.
See the Versioned Chip Endorsement Key (VCEK) Certificate and KDS
Interface Specification. Document # 57230 Rev. 0.50 October 2021
https://web.archive.org/web/20221213033802/https://www.amd.com/system/files/TechDocs/57230.pdf
BUG=b:243470283
TEST=Build Skyrim BIOS image and boot to OS.
Change-Id: Iee897dd2c0943c17e81e02a4d6c6296b585e12af
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Add PMIC MT6315 support for SSPM.
BUG=b:249436110
TEST=test of suspend and resume pass.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Change-Id: I5cf5c0a46ce0af056dca6af7442a9ddb5be4b490
The last_emi is unsupported in ChromeOS project, so EMI driver would
get a NULL address because no memory is reserved for last_emi. Add
error checking for last_emi to avoid null pointer issue.
BUG=b:233720142
TEST=Test of suspend resume passes.
Change-Id: I7ceb048fc8e393607cab5096e6be626b9e0de135
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
1.02
Modified the F10 scan code for better compatibility
Modified the F12 scan code for better compatibility
Initialised the Keyboard Backlight from the EC to avoid problems when switching branch
1.01
Fix the backlight helper to remember the last state
Modified the scan code of the sysreq key
1.00
Initial release EC firmware for the StarBook Mk VI
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I557fd5cd3b987fb4d9a1fb0eaa0e442d94c848fe
[ADL] 1.01:
Enable hybrid power - when the battery has more than 15% power, support
chargers that don't output the required 40W.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If2c6311af7744b6bd708c2084ce18fcfe13b8f5d
The efuse memory address is wrong for MCUPM to access. Add the
offset to revise the efuse memory address.
TEST=boot to shell.
BUG=b:244250440
Change-Id: I6e1b873cffa2949997ff36346266446c9380ae04
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
coreboot was spelled with a capital C in these files. We don't run the
linters on these files, but since they're part of a coreboot-owned repo,
let's fix them.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Icb1d6ee12057d552938496d198a17b6c8bfd93e8
Add changelogs for the EC updates and update the versions to:
[ADL] 1.00:
Initial release firmware
[TGL] 1.03:
Initial release firmware for the StarBook Mk VI
[CML] 1.07:
Add support to set the maximum charge level of the battery
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2130852554388baf61b44091bfa827cb2b2f09e3
ChromeOS requires a custom SPL table. Make that table available in
coreboot to link against.
Bug=b:245727030
Test=Boots
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I70dcb19983c970283ee887b78a18c0668e83d4b0
For ChromeOS project, we need to use MCUPM firmware without mtk header.
TEST=boot to shell.
BUG=b:244250440
Change-Id: I9730a9e16642644dd5282bb6714e29cf6f6ce335
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Revise the latency offset in SYSRAM for CPUFreq to be consistent with
MT8195.
TEST=boot to shell.
BUG=b:244250440
Change-Id: Id2fee742b545d2b50595cf35baaf647008fd0e2e
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.corp-partner.google.com>
This is a data file that gives configuration data to AMD's ABL,
the PSP AGESA Bootloader. As there is no code, there is no ABI,
license, or version number.
Specified contents describing memory initialization:
Memory is 2 channel, LPDDR5/LPDDR5x
The GPIOs to use for the SPD identifiers:
Bit 0: GPIO 144
Bit 1: GPIO 85
Bit 2: GPIO 79
Bit 3: GPIO 91
Contains 16 slots for possible SPD entries.
UMA size is set to 64MB.
eSPI I/O range address and size configuration.
MEMRESTORECTL is enabled to leverage MRC Cache.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia72eb4bd3ea74d813cad34e06fb0452814460144
This blob includes both full calibration and fast calibration flow.
BUG=b:233720142
TEST=DRAM calibration pass
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0a6c0085700cad4582de2d5b9c1a6a18e9313c35
Add SPM firmware version: pcm_suspend_20220705_v2_MP.
SPM suspend can turn 26M clock off when system goes into suspend
to save power.
TEST=spm pc is 0x400 which is in idle state.
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I2221f757ebe29ba982b80291a3f2fbd314083615
Add dpm.pm and dpm.dm to support DRAM power management.
TEST=build pass
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I5d6d27c7d06b91a6530f9e259ae7bb69f1f12c60
Since switching to upstream edk2, the extra padding that was added
to overcome MrChromebox’s hardcoded options is no longer needed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia2740b8082131d1dc9cca71cd5049f29914d3e62
1.07 has the following changes:
* Add support to set the maximum charge level of the battery
* Add Q Event for Touchpad State which allows it to be saved on
reboot
* Updated power configuration
* Use battery as a power source when the charger doesn't supply
enough output
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9b7cba104f347b31e075e18f0d5b1bdc8cb406ad
1.03 contains the following changes:
* Fixed issue where keyboard backlight wouldn't turn off when
entering S3 or turning off
* Update Normal and Quiet fan curves to delay start until 65
degrees. Performance mode is unchanged.
* Added support to select maximum charge percentage
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia478540ef0a850de27d1dd34e40fd7fe8ccfbbba
The LabTop was renamed to the StarBook in its 5th generation, so this
change makes the folder more correct.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I97dbd66ec5b0acd68ca029dd156f8c8c5409ee88
This reverts commit d13ba18eb0.
Revert reason:
CB:62327 was created to fix a suspend failure issue, where we disable
26M clock to bypass pmic wrap when suspending. However, it turns out
that the root cause of the suspend issue is an incorrect pmif setting,
which is fixed in CB:63089. Therefore, revert CB:62327 to enable 26M
clock.
BUG=b:215639203
TEST=test of suspend and resume pass.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I63923188b814f0b44690784b55bcec9aff9b3d23
The existing APCB file only has 4 SPD slots. This will not be enough
for DeWatt devices due to upcoming changes in how RAM IDs are allocated
for that variant. This commit updates the APCB file to have 16 slots
which is sufficient for DeWatt.
BUG=b:224884904
TEST=Used apcb_v3_edit to verify that the APCB file has 16 slots,
checked that AP firmware images built with this file boot correctly
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ifbfe2c61c42cd503a70fd84c51ce184c40fed318
The SRCLKENA0 is not pulled down when suspending. The root cause is that
26MHz clock is not disabled when suspending, so we update SPM firmware
to fix this issue.
TEST=verify 26MHz clock off using the oscilloscope.
BUG=b:215639203
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: Iccaea858ff37cc3934c9a9a64bce7edf7cb0fbf1
This SPL table is for all the Guybrush Chromebook.
BUG=b:216096562
Change-Id: I651bc76ca8f71ea842ca9ddb4ba99cfe03fc31bb
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
This blob includes both full calibration and fast calibration flow.
TEST=DRAM calibration pass
BUG=b:204226005
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I010ded1cb68f4bd50f08927b0b4faaa9b9db67f6
Alicja Michalska