xtensa: add xtensa_dc233c
This adds config and overlay to support the dc233c core that is available on QEMU. This core has more features than sample_controller, such as MMU support. The overlay comes from: https://github.com/jcmvbkbc/xtensa-toolchain-build/blob/master/overlays/original/dc233c.tar.gz Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
7d1b95ecfa
commit
b9b150ad31
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@ -50,6 +50,7 @@ on:
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- riscv64-zephyr-elf
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- sparc-zephyr-elf
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- x86_64-zephyr-elf
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- xtensa-dc233c_zephyr-elf
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- xtensa-espressif_esp32_zephyr-elf
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- xtensa-espressif_esp32s2_zephyr-elf
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- xtensa-espressif_esp32s3_zephyr-elf
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@ -159,6 +160,7 @@ jobs:
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riscv64-zephyr-elf) build_target_riscv64_zephyr_elf="y";;
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sparc-zephyr-elf) build_target_sparc_zephyr_elf="y";;
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x86_64-zephyr-elf) build_target_x86_64_zephyr_elf="y";;
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xtensa-dc233c_zephyr-elf) build_target_xtensa_dc233c_zephyr_elf="y";;
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xtensa-espressif_esp32_zephyr-elf) build_target_xtensa_espressif_esp32_zephyr_elf="y";;
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xtensa-espressif_esp32s2_zephyr-elf) build_target_xtensa_espressif_esp32s2_zephyr_elf="y";;
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xtensa-espressif_esp32s3_zephyr-elf) build_target_xtensa_espressif_esp32s3_zephyr_elf="y";;
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@ -196,6 +198,7 @@ jobs:
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build_target_riscv64_zephyr_elf="y"
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build_target_sparc_zephyr_elf="y"
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build_target_x86_64_zephyr_elf="y"
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build_target_xtensa_dc233c_zephyr_elf="y"
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build_target_xtensa_espressif_esp32_zephyr_elf="y"
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build_target_xtensa_espressif_esp32s2_zephyr_elf="y"
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build_target_xtensa_espressif_esp32s3_zephyr_elf="y"
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@ -273,6 +276,7 @@ jobs:
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[ "${build_target_riscv64_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"riscv64-zephyr-elf",'
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[ "${build_target_sparc_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"sparc-zephyr-elf",'
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[ "${build_target_x86_64_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"x86_64-zephyr-elf",'
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[ "${build_target_xtensa_dc233c_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-dc233c_zephyr-elf",'
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[ "${build_target_xtensa_espressif_esp32_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-espressif_esp32_zephyr-elf",'
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[ "${build_target_xtensa_espressif_esp32s2_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-espressif_esp32s2_zephyr-elf",'
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[ "${build_target_xtensa_espressif_esp32s3_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-espressif_esp32s3_zephyr-elf",'
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@ -1520,6 +1524,9 @@ jobs:
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PLATFORM_ARGS+="-p qemu_x86 "
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PLATFORM_ARGS+="-p qemu_x86_64 "
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;;
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xtensa-dc233c_zephyr-elf)
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PLATFORM_ARGS+="-p qemu_xtensa_dc233c "
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;;
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xtensa-espressif_esp32_zephyr-elf)
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PLATFORM_ARGS+="-p esp32 "
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;;
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@ -0,0 +1,8 @@
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CT_CONFIG_VERSION="3"
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CT_EXPERIMENTAL=y
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CT_OVERLAY_LOCATION="overlays"
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CT_OVERLAY_NAME="dc233c"
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CT_ARCH_XTENSA=y
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CT_XTENSA_CUSTOM=y
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CT_TARGET_VENDOR="dc233c_zephyr"
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CT_TARGET_CFLAGS="-ftls-model=local-exec"
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,174 @@
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/* Xtensa configuration settings.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef XTENSA_CONFIG_H
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#define XTENSA_CONFIG_H
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/* The macros defined here match those with the same names in the Xtensa
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compile-time HAL (Hardware Abstraction Layer). Please refer to the
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Xtensa System Software Reference Manual for documentation of these
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macros. */
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#undef XCHAL_HAVE_BE
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#define XCHAL_HAVE_BE 0
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#undef XCHAL_HAVE_DENSITY
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#define XCHAL_HAVE_DENSITY 1
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#undef XCHAL_HAVE_CONST16
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#define XCHAL_HAVE_CONST16 0
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#undef XCHAL_HAVE_ABS
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#define XCHAL_HAVE_ABS 1
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#undef XCHAL_HAVE_ADDX
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#define XCHAL_HAVE_ADDX 1
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#undef XCHAL_HAVE_L32R
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#define XCHAL_HAVE_L32R 1
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#undef XSHAL_USE_ABSOLUTE_LITERALS
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#define XSHAL_USE_ABSOLUTE_LITERALS 0
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#undef XCHAL_HAVE_MAC16
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#define XCHAL_HAVE_MAC16 1
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#undef XCHAL_HAVE_MUL16
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#define XCHAL_HAVE_MUL16 1
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#undef XCHAL_HAVE_MUL32
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#define XCHAL_HAVE_MUL32 1
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#undef XCHAL_HAVE_MUL32_HIGH
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#define XCHAL_HAVE_MUL32_HIGH 0
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#undef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 1
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#undef XCHAL_HAVE_NSA
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#define XCHAL_HAVE_NSA 1
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#undef XCHAL_HAVE_MINMAX
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#define XCHAL_HAVE_MINMAX 1
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#undef XCHAL_HAVE_SEXT
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#define XCHAL_HAVE_SEXT 1
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#undef XCHAL_HAVE_LOOPS
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#define XCHAL_HAVE_LOOPS 1
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#undef XCHAL_HAVE_THREADPTR
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#define XCHAL_HAVE_THREADPTR 1
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#undef XCHAL_HAVE_RELEASE_SYNC
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#define XCHAL_HAVE_RELEASE_SYNC 1
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#undef XCHAL_HAVE_S32C1I
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#define XCHAL_HAVE_S32C1I 1
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#undef XCHAL_HAVE_BOOLEANS
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#define XCHAL_HAVE_BOOLEANS 0
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#undef XCHAL_HAVE_FP
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#define XCHAL_HAVE_FP 0
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#undef XCHAL_HAVE_FP_DIV
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#define XCHAL_HAVE_FP_DIV 0
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#undef XCHAL_HAVE_FP_RECIP
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#define XCHAL_HAVE_FP_RECIP 0
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#undef XCHAL_HAVE_FP_SQRT
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#define XCHAL_HAVE_FP_SQRT 0
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#undef XCHAL_HAVE_FP_RSQRT
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#define XCHAL_HAVE_FP_RSQRT 0
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#undef XCHAL_HAVE_DFP_accel
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#define XCHAL_HAVE_DFP_accel 0
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#undef XCHAL_HAVE_WINDOWED
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#define XCHAL_HAVE_WINDOWED 1
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#undef XCHAL_NUM_AREGS
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#define XCHAL_NUM_AREGS 32
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#undef XCHAL_HAVE_WIDE_BRANCHES
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#define XCHAL_HAVE_WIDE_BRANCHES 0
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#undef XCHAL_HAVE_PREDICTED_BRANCHES
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0
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#undef XCHAL_ICACHE_SIZE
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#define XCHAL_ICACHE_SIZE 16384
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#undef XCHAL_DCACHE_SIZE
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#define XCHAL_DCACHE_SIZE 16384
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#undef XCHAL_ICACHE_LINESIZE
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#define XCHAL_ICACHE_LINESIZE 32
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#undef XCHAL_DCACHE_LINESIZE
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#define XCHAL_DCACHE_LINESIZE 32
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#undef XCHAL_ICACHE_LINEWIDTH
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#define XCHAL_ICACHE_LINEWIDTH 5
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#undef XCHAL_DCACHE_LINEWIDTH
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#define XCHAL_DCACHE_LINEWIDTH 5
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#undef XCHAL_DCACHE_IS_WRITEBACK
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#define XCHAL_DCACHE_IS_WRITEBACK 1
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#undef XCHAL_HAVE_MMU
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#define XCHAL_HAVE_MMU 1
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#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
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#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
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#undef XCHAL_HAVE_DEBUG
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#define XCHAL_HAVE_DEBUG 1
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#undef XCHAL_NUM_IBREAK
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#define XCHAL_NUM_IBREAK 2
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#undef XCHAL_NUM_DBREAK
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#define XCHAL_NUM_DBREAK 2
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#undef XCHAL_DEBUGLEVEL
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#define XCHAL_DEBUGLEVEL 6
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#undef XCHAL_MAX_INSTRUCTION_SIZE
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#define XCHAL_MAX_INSTRUCTION_SIZE 3
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#undef XCHAL_INST_FETCH_WIDTH
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#define XCHAL_INST_FETCH_WIDTH 4
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#undef XSHAL_ABI
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#undef XTHAL_ABI_WINDOWED
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#undef XTHAL_ABI_CALL0
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#define XSHAL_ABI XTHAL_ABI_WINDOWED
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#define XTHAL_ABI_WINDOWED 0
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#define XTHAL_ABI_CALL0 1
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#endif /* !XTENSA_CONFIG_H */
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@ -0,0 +1,174 @@
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/* Xtensa configuration settings.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef XTENSA_CONFIG_H
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#define XTENSA_CONFIG_H
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/* The macros defined here match those with the same names in the Xtensa
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compile-time HAL (Hardware Abstraction Layer). Please refer to the
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Xtensa System Software Reference Manual for documentation of these
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macros. */
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#undef XCHAL_HAVE_BE
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#define XCHAL_HAVE_BE 0
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#undef XCHAL_HAVE_DENSITY
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#define XCHAL_HAVE_DENSITY 1
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#undef XCHAL_HAVE_CONST16
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#define XCHAL_HAVE_CONST16 0
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#undef XCHAL_HAVE_ABS
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#define XCHAL_HAVE_ABS 1
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#undef XCHAL_HAVE_ADDX
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#define XCHAL_HAVE_ADDX 1
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#undef XCHAL_HAVE_L32R
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#define XCHAL_HAVE_L32R 1
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#undef XSHAL_USE_ABSOLUTE_LITERALS
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#define XSHAL_USE_ABSOLUTE_LITERALS 0
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#undef XCHAL_HAVE_MAC16
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#define XCHAL_HAVE_MAC16 1
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#undef XCHAL_HAVE_MUL16
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#define XCHAL_HAVE_MUL16 1
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#undef XCHAL_HAVE_MUL32
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#define XCHAL_HAVE_MUL32 1
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#undef XCHAL_HAVE_MUL32_HIGH
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#define XCHAL_HAVE_MUL32_HIGH 0
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#undef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 1
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#undef XCHAL_HAVE_NSA
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#define XCHAL_HAVE_NSA 1
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#undef XCHAL_HAVE_MINMAX
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#define XCHAL_HAVE_MINMAX 1
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#undef XCHAL_HAVE_SEXT
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#define XCHAL_HAVE_SEXT 1
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#undef XCHAL_HAVE_LOOPS
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#define XCHAL_HAVE_LOOPS 1
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#undef XCHAL_HAVE_THREADPTR
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#define XCHAL_HAVE_THREADPTR 1
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#undef XCHAL_HAVE_RELEASE_SYNC
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#define XCHAL_HAVE_RELEASE_SYNC 1
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#undef XCHAL_HAVE_S32C1I
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#define XCHAL_HAVE_S32C1I 1
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#undef XCHAL_HAVE_BOOLEANS
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#define XCHAL_HAVE_BOOLEANS 0
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#undef XCHAL_HAVE_FP
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#define XCHAL_HAVE_FP 0
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#undef XCHAL_HAVE_FP_DIV
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#define XCHAL_HAVE_FP_DIV 0
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#undef XCHAL_HAVE_FP_RECIP
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#define XCHAL_HAVE_FP_RECIP 0
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#undef XCHAL_HAVE_FP_SQRT
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#define XCHAL_HAVE_FP_SQRT 0
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#undef XCHAL_HAVE_FP_RSQRT
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#define XCHAL_HAVE_FP_RSQRT 0
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#undef XCHAL_HAVE_DFP_accel
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#define XCHAL_HAVE_DFP_accel 0
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#undef XCHAL_HAVE_WINDOWED
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#define XCHAL_HAVE_WINDOWED 1
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#undef XCHAL_NUM_AREGS
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#define XCHAL_NUM_AREGS 32
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#undef XCHAL_HAVE_WIDE_BRANCHES
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#define XCHAL_HAVE_WIDE_BRANCHES 0
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#undef XCHAL_HAVE_PREDICTED_BRANCHES
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0
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#undef XCHAL_ICACHE_SIZE
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#define XCHAL_ICACHE_SIZE 16384
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#undef XCHAL_DCACHE_SIZE
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#define XCHAL_DCACHE_SIZE 16384
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#undef XCHAL_ICACHE_LINESIZE
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#define XCHAL_ICACHE_LINESIZE 32
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#undef XCHAL_DCACHE_LINESIZE
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#define XCHAL_DCACHE_LINESIZE 32
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#undef XCHAL_ICACHE_LINEWIDTH
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#define XCHAL_ICACHE_LINEWIDTH 5
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#undef XCHAL_DCACHE_LINEWIDTH
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#define XCHAL_DCACHE_LINEWIDTH 5
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#undef XCHAL_DCACHE_IS_WRITEBACK
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#define XCHAL_DCACHE_IS_WRITEBACK 1
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#undef XCHAL_HAVE_MMU
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#define XCHAL_HAVE_MMU 1
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#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
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#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
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#undef XCHAL_HAVE_DEBUG
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#define XCHAL_HAVE_DEBUG 1
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#undef XCHAL_NUM_IBREAK
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#define XCHAL_NUM_IBREAK 2
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#undef XCHAL_NUM_DBREAK
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#define XCHAL_NUM_DBREAK 2
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#undef XCHAL_DEBUGLEVEL
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#define XCHAL_DEBUGLEVEL 6
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#undef XCHAL_MAX_INSTRUCTION_SIZE
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#define XCHAL_MAX_INSTRUCTION_SIZE 3
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#undef XCHAL_INST_FETCH_WIDTH
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#define XCHAL_INST_FETCH_WIDTH 4
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#undef XSHAL_ABI
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#undef XTHAL_ABI_WINDOWED
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#undef XTHAL_ABI_CALL0
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#define XSHAL_ABI XTHAL_ABI_WINDOWED
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#define XTHAL_ABI_WINDOWED 0
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#define XTHAL_ABI_CALL0 1
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#endif /* !XTENSA_CONFIG_H */
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,54 @@
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name:xtensa
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expedite:pc,windowbase,windowstart
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32:pc
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32:ar0
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32:ar1
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32:ar2
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32:ar3
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32:ar4
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32:ar5
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32:ar6
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32:ar7
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32:ar8
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32:ar9
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32:ar10
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32:ar11
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32:ar12
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32:ar13
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32:ar14
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32:ar15
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32:ar16
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32:ar17
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32:ar18
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32:ar19
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32:ar20
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32:ar21
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32:ar22
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32:ar23
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32:ar24
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32:ar25
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32:ar26
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32:ar27
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32:ar28
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32:ar29
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32:ar30
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32:ar31
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32:lbeg
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32:lend
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32:lcount
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32:sar
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32:litbase
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32:windowbase
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32:windowstart
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32:sr176
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32:sr208
|
||||
32:ps
|
||||
32:threadptr
|
||||
32:scompare1
|
||||
32:acclo
|
||||
32:acchi
|
||||
32:m0
|
||||
32:m1
|
||||
32:m2
|
||||
32:m3
|
||||
32:expstate
|
||||
|
|
@ -0,0 +1,251 @@
|
|||
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
|
||||
|
||||
Copyright (c) 2003-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#define XTENSA_CONFIG_VERSION 0x60
|
||||
|
||||
#include "defs.h"
|
||||
#include "xtensa-config.h"
|
||||
#include "xtensa-tdep.h"
|
||||
|
||||
|
||||
|
||||
/* Masked registers. */
|
||||
xtensa_reg_mask_t xtensa_submask0[] = { { 42, 0, 4 } };
|
||||
const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
|
||||
xtensa_reg_mask_t xtensa_submask1[] = { { 42, 5, 1 } };
|
||||
const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
|
||||
xtensa_reg_mask_t xtensa_submask2[] = { { 42, 18, 1 } };
|
||||
const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
|
||||
xtensa_reg_mask_t xtensa_submask3[] = { { 42, 6, 2 } };
|
||||
const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
|
||||
xtensa_reg_mask_t xtensa_submask4[] = { { 42, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
|
||||
xtensa_reg_mask_t xtensa_submask5[] = { { 42, 16, 2 } };
|
||||
const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
|
||||
xtensa_reg_mask_t xtensa_submask6[] = { { 42, 8, 4 } };
|
||||
const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
|
||||
xtensa_reg_mask_t xtensa_submask7[] = { { 37, 12, 20 } };
|
||||
const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
|
||||
xtensa_reg_mask_t xtensa_submask8[] = { { 37, 0, 1 } };
|
||||
const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
|
||||
xtensa_reg_mask_t xtensa_submask9[] = { { 45, 0, 32 }, { 46, 0, 8 } };
|
||||
const xtensa_mask_t xtensa_mask9 = { 2, xtensa_submask9 };
|
||||
xtensa_reg_mask_t xtensa_submask10[] = { { 94, 8, 4 } };
|
||||
const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
|
||||
xtensa_reg_mask_t xtensa_submask11[] = { { 54, 24, 8 } };
|
||||
const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
|
||||
xtensa_reg_mask_t xtensa_submask12[] = { { 54, 16, 8 } };
|
||||
const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
|
||||
xtensa_reg_mask_t xtensa_submask13[] = { { 54, 8, 8 } };
|
||||
const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
|
||||
xtensa_reg_mask_t xtensa_submask14[] = { { 55, 24, 1 } };
|
||||
const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
|
||||
xtensa_reg_mask_t xtensa_submask15[] = { { 55, 20, 1 } };
|
||||
const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
|
||||
xtensa_reg_mask_t xtensa_submask16[] = { { 55, 16, 2 } };
|
||||
const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
|
||||
xtensa_reg_mask_t xtensa_submask17[] = { { 56, 24, 1 } };
|
||||
const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
|
||||
xtensa_reg_mask_t xtensa_submask18[] = { { 56, 20, 1 } };
|
||||
const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
|
||||
xtensa_reg_mask_t xtensa_submask19[] = { { 56, 16, 2 } };
|
||||
const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
|
||||
xtensa_reg_mask_t xtensa_submask20[] = { { 52, 22, 10 } };
|
||||
const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
|
||||
|
||||
|
||||
/* Register map. */
|
||||
xtensa_register_t rmap[] =
|
||||
{
|
||||
/* idx ofs bi sz al targno flags cp typ group name */
|
||||
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
|
||||
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
|
||||
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
|
||||
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
|
||||
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
|
||||
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
|
||||
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
|
||||
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
|
||||
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
|
||||
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
|
||||
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
|
||||
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
|
||||
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
|
||||
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
|
||||
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
|
||||
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
|
||||
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
|
||||
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
|
||||
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
|
||||
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
|
||||
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
|
||||
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
|
||||
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
|
||||
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
|
||||
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
|
||||
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
|
||||
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
|
||||
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
|
||||
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
|
||||
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
|
||||
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
|
||||
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
|
||||
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
|
||||
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
|
||||
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
|
||||
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
|
||||
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
|
||||
XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
|
||||
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
|
||||
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
|
||||
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176, 0,0,0,0,0,0)
|
||||
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208, 0,0,0,0,0,0)
|
||||
XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
|
||||
XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
|
||||
XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
|
||||
XTREG( 45,180,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
|
||||
XTREG( 46,184, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
|
||||
XTREG( 47,188,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
|
||||
XTREG( 48,192,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
|
||||
XTREG( 49,196,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
|
||||
XTREG( 50,200,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
|
||||
XTREG( 51,204,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
|
||||
XTREG( 52,208,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
|
||||
XTREG( 53,212,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
|
||||
XTREG( 54,216,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
|
||||
XTREG( 55,220,25, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
|
||||
XTREG( 56,224,25, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
|
||||
XTREG( 57,228, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
|
||||
XTREG( 58,232, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
|
||||
XTREG( 59,236,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
|
||||
XTREG( 60,240,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 61,244,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 62,248,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 63,252,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 64,256,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
|
||||
XTREG( 65,260,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
|
||||
XTREG( 66,264,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
|
||||
XTREG( 67,268,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
|
||||
XTREG( 68,272,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
|
||||
XTREG( 69,276,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
|
||||
XTREG( 70,280,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
|
||||
XTREG( 71,284,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
|
||||
XTREG( 72,288,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
|
||||
XTREG( 73,292,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
|
||||
XTREG( 74,296,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
|
||||
XTREG( 75,300,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
|
||||
XTREG( 76,304,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
|
||||
XTREG( 77,308,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
|
||||
XTREG( 78,312,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
|
||||
XTREG( 79,316,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
|
||||
XTREG( 80,320,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
|
||||
XTREG( 81,324,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
|
||||
XTREG( 82,328,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
|
||||
XTREG( 83,332,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
|
||||
XTREG( 84,336,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
|
||||
XTREG( 85,340,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
|
||||
XTREG( 86,344,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
|
||||
XTREG( 87,348, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
|
||||
XTREG( 88,352,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
|
||||
XTREG( 89,356,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
|
||||
XTREG( 90,360,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
|
||||
XTREG( 91,364,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
|
||||
XTREG( 92,368,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
|
||||
XTREG( 93,372, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
|
||||
XTREG( 94,376,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
|
||||
XTREG( 95,380,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
|
||||
XTREG( 96,384,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
|
||||
XTREG( 97,388,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
|
||||
XTREG( 98,392, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
||||
XTREG( 99,396,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG(100,400,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG(101,404,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG(102,408,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
|
||||
XTREG(103,412,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
|
||||
XTREG(104,416,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
|
||||
XTREG(105,420,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
|
||||
XTREG(106,424,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
|
||||
XTREG(107,428,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
|
||||
XTREG(108,432,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
|
||||
XTREG(109,436,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
|
||||
XTREG(110,440,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
|
||||
XTREG(111,444,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
|
||||
XTREG(112,448,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
|
||||
XTREG(113,452,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
|
||||
XTREG(114,456,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
|
||||
XTREG(115,460,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
|
||||
XTREG(116,464,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
|
||||
XTREG(117,468,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
|
||||
XTREG(118,472,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
|
||||
XTREG(119,476,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
|
||||
XTREG(120,480,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
|
||||
XTREG(121,484, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
|
||||
0,0,&xtensa_mask0,0,0,0)
|
||||
XTREG(122,488, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
|
||||
0,0,&xtensa_mask1,0,0,0)
|
||||
XTREG(123,492, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
|
||||
0,0,&xtensa_mask2,0,0,0)
|
||||
XTREG(124,496, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,
|
||||
0,0,&xtensa_mask3,0,0,0)
|
||||
XTREG(125,500, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,
|
||||
0,0,&xtensa_mask4,0,0,0)
|
||||
XTREG(126,504, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,
|
||||
0,0,&xtensa_mask5,0,0,0)
|
||||
XTREG(127,508, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,
|
||||
0,0,&xtensa_mask6,0,0,0)
|
||||
XTREG(128,512,20, 4, 4,0x200f,0x0006,-2, 6,0x1010,litbaddr,
|
||||
0,0,&xtensa_mask7,0,0,0)
|
||||
XTREG(129,516, 1, 4, 4,0x2010,0x0006,-2, 6,0x1010,litben,
|
||||
0,0,&xtensa_mask8,0,0,0)
|
||||
XTREG(130,520,40, 8, 4,0x2011,0x0006,-2, 6,0x1010,acc,
|
||||
0,0,&xtensa_mask9,0,0,0)
|
||||
XTREG(131,528, 4, 4, 4,0x2016,0x0006,-2, 6,0x1010,dbnum,
|
||||
0,0,&xtensa_mask10,0,0,0)
|
||||
XTREG(132,532, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid3,
|
||||
0,0,&xtensa_mask11,0,0,0)
|
||||
XTREG(133,536, 8, 4, 4,0x2018,0x0006,-2, 6,0x1010,asid2,
|
||||
0,0,&xtensa_mask12,0,0,0)
|
||||
XTREG(134,540, 8, 4, 4,0x2019,0x0006,-2, 6,0x1010,asid1,
|
||||
0,0,&xtensa_mask13,0,0,0)
|
||||
XTREG(135,544, 1, 4, 4,0x201a,0x0006,-2, 6,0x1010,instpgszid6,
|
||||
0,0,&xtensa_mask14,0,0,0)
|
||||
XTREG(136,548, 1, 4, 4,0x201b,0x0006,-2, 6,0x1010,instpgszid5,
|
||||
0,0,&xtensa_mask15,0,0,0)
|
||||
XTREG(137,552, 2, 4, 4,0x201c,0x0006,-2, 6,0x1010,instpgszid4,
|
||||
0,0,&xtensa_mask16,0,0,0)
|
||||
XTREG(138,556, 1, 4, 4,0x201d,0x0006,-2, 6,0x1010,datapgszid6,
|
||||
0,0,&xtensa_mask17,0,0,0)
|
||||
XTREG(139,560, 1, 4, 4,0x201e,0x0006,-2, 6,0x1010,datapgszid5,
|
||||
0,0,&xtensa_mask18,0,0,0)
|
||||
XTREG(140,564, 2, 4, 4,0x201f,0x0006,-2, 6,0x1010,datapgszid4,
|
||||
0,0,&xtensa_mask19,0,0,0)
|
||||
XTREG_END
|
||||
};
|
||||
|
||||
|
||||
|
||||
#ifdef XTENSA_CONFIG_INSTANTIATE
|
||||
XTENSA_CONFIG_INSTANTIATE(rmap,0)
|
||||
#endif
|
||||
|
||||
xtensa_gdbarch_tdep xtensa_tdep (rmap);
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/* Customized table mapping between kernel xtregset and GDB register cache.
|
||||
|
||||
Copyright (c) 2007-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
typedef struct {
|
||||
int gdb_regnum;
|
||||
int gdb_offset;
|
||||
int ptrace_cp_offset;
|
||||
int ptrace_offset;
|
||||
int size;
|
||||
int coproc;
|
||||
int dbnum;
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 28
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 44, 176, 24, 24, 4, -1, 0x020c, "scompare1" },
|
||||
{ 45, 180, 0, 0, 4, -1, 0x0210, "acclo" },
|
||||
{ 46, 184, 4, 4, 4, -1, 0x0211, "acchi" },
|
||||
{ 47, 188, 8, 8, 4, -1, 0x0220, "m0" },
|
||||
{ 48, 192, 12, 12, 4, -1, 0x0221, "m1" },
|
||||
{ 49, 196, 16, 16, 4, -1, 0x0222, "m2" },
|
||||
{ 50, 200, 20, 20, 4, -1, 0x0223, "m3" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/* Customized table mapping between kernel xtregset and GDB register cache.
|
||||
|
||||
Copyright (c) 2007-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
typedef struct {
|
||||
int gdb_regnum;
|
||||
int gdb_offset;
|
||||
int ptrace_cp_offset;
|
||||
int ptrace_offset;
|
||||
int size;
|
||||
int coproc;
|
||||
int dbnum;
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 28
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 44, 176, 24, 24, 4, -1, 0x020c, "scompare1" },
|
||||
{ 45, 180, 0, 0, 4, -1, 0x0210, "acclo" },
|
||||
{ 46, 184, 4, 4, 4, -1, 0x0211, "acchi" },
|
||||
{ 47, 188, 8, 8, 4, -1, 0x0220, "m0" },
|
||||
{ 48, 192, 12, 12, 4, -1, 0x0221, "m1" },
|
||||
{ 49, 196, 16, 16, 4, -1, 0x0222, "m2" },
|
||||
{ 50, 200, 20, 20, 4, -1, 0x0223, "m3" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
/* Xtensa configuration settings.
|
||||
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
||||
|
||||
#ifndef XTENSA_CONFIG_H
|
||||
#define XTENSA_CONFIG_H
|
||||
|
||||
/* The macros defined here match those with the same names in the Xtensa
|
||||
compile-time HAL (Hardware Abstraction Layer). Please refer to the
|
||||
Xtensa System Software Reference Manual for documentation of these
|
||||
macros. */
|
||||
|
||||
#undef XCHAL_HAVE_BE
|
||||
#define XCHAL_HAVE_BE 0
|
||||
|
||||
#undef XCHAL_HAVE_DENSITY
|
||||
#define XCHAL_HAVE_DENSITY 1
|
||||
|
||||
#undef XCHAL_HAVE_CONST16
|
||||
#define XCHAL_HAVE_CONST16 0
|
||||
|
||||
#undef XCHAL_HAVE_ABS
|
||||
#define XCHAL_HAVE_ABS 1
|
||||
|
||||
#undef XCHAL_HAVE_ADDX
|
||||
#define XCHAL_HAVE_ADDX 1
|
||||
|
||||
#undef XCHAL_HAVE_L32R
|
||||
#define XCHAL_HAVE_L32R 1
|
||||
|
||||
#undef XSHAL_USE_ABSOLUTE_LITERALS
|
||||
#define XSHAL_USE_ABSOLUTE_LITERALS 0
|
||||
|
||||
#undef XCHAL_HAVE_MAC16
|
||||
#define XCHAL_HAVE_MAC16 1
|
||||
|
||||
#undef XCHAL_HAVE_MUL16
|
||||
#define XCHAL_HAVE_MUL16 1
|
||||
|
||||
#undef XCHAL_HAVE_MUL32
|
||||
#define XCHAL_HAVE_MUL32 1
|
||||
|
||||
#undef XCHAL_HAVE_MUL32_HIGH
|
||||
#define XCHAL_HAVE_MUL32_HIGH 0
|
||||
|
||||
#undef XCHAL_HAVE_DIV32
|
||||
#define XCHAL_HAVE_DIV32 1
|
||||
|
||||
#undef XCHAL_HAVE_NSA
|
||||
#define XCHAL_HAVE_NSA 1
|
||||
|
||||
#undef XCHAL_HAVE_MINMAX
|
||||
#define XCHAL_HAVE_MINMAX 1
|
||||
|
||||
#undef XCHAL_HAVE_SEXT
|
||||
#define XCHAL_HAVE_SEXT 1
|
||||
|
||||
#undef XCHAL_HAVE_LOOPS
|
||||
#define XCHAL_HAVE_LOOPS 1
|
||||
|
||||
#undef XCHAL_HAVE_THREADPTR
|
||||
#define XCHAL_HAVE_THREADPTR 1
|
||||
|
||||
#undef XCHAL_HAVE_RELEASE_SYNC
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1
|
||||
|
||||
#undef XCHAL_HAVE_S32C1I
|
||||
#define XCHAL_HAVE_S32C1I 1
|
||||
|
||||
#undef XCHAL_HAVE_BOOLEANS
|
||||
#define XCHAL_HAVE_BOOLEANS 0
|
||||
|
||||
#undef XCHAL_HAVE_FP
|
||||
#define XCHAL_HAVE_FP 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_DIV
|
||||
#define XCHAL_HAVE_FP_DIV 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_RECIP
|
||||
#define XCHAL_HAVE_FP_RECIP 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_SQRT
|
||||
#define XCHAL_HAVE_FP_SQRT 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_RSQRT
|
||||
#define XCHAL_HAVE_FP_RSQRT 0
|
||||
|
||||
#undef XCHAL_HAVE_DFP_accel
|
||||
#define XCHAL_HAVE_DFP_accel 0
|
||||
#undef XCHAL_HAVE_WINDOWED
|
||||
#define XCHAL_HAVE_WINDOWED 1
|
||||
|
||||
#undef XCHAL_NUM_AREGS
|
||||
#define XCHAL_NUM_AREGS 32
|
||||
|
||||
#undef XCHAL_HAVE_WIDE_BRANCHES
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0
|
||||
|
||||
#undef XCHAL_HAVE_PREDICTED_BRANCHES
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
|
||||
|
||||
|
||||
#undef XCHAL_ICACHE_SIZE
|
||||
#define XCHAL_ICACHE_SIZE 16384
|
||||
|
||||
#undef XCHAL_DCACHE_SIZE
|
||||
#define XCHAL_DCACHE_SIZE 16384
|
||||
|
||||
#undef XCHAL_ICACHE_LINESIZE
|
||||
#define XCHAL_ICACHE_LINESIZE 32
|
||||
|
||||
#undef XCHAL_DCACHE_LINESIZE
|
||||
#define XCHAL_DCACHE_LINESIZE 32
|
||||
|
||||
#undef XCHAL_ICACHE_LINEWIDTH
|
||||
#define XCHAL_ICACHE_LINEWIDTH 5
|
||||
|
||||
#undef XCHAL_DCACHE_LINEWIDTH
|
||||
#define XCHAL_DCACHE_LINEWIDTH 5
|
||||
|
||||
#undef XCHAL_DCACHE_IS_WRITEBACK
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1
|
||||
|
||||
|
||||
#undef XCHAL_HAVE_MMU
|
||||
#define XCHAL_HAVE_MMU 1
|
||||
|
||||
#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
|
||||
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
|
||||
|
||||
|
||||
#undef XCHAL_HAVE_DEBUG
|
||||
#define XCHAL_HAVE_DEBUG 1
|
||||
|
||||
#undef XCHAL_NUM_IBREAK
|
||||
#define XCHAL_NUM_IBREAK 2
|
||||
|
||||
#undef XCHAL_NUM_DBREAK
|
||||
#define XCHAL_NUM_DBREAK 2
|
||||
|
||||
#undef XCHAL_DEBUGLEVEL
|
||||
#define XCHAL_DEBUGLEVEL 6
|
||||
|
||||
|
||||
#undef XCHAL_MAX_INSTRUCTION_SIZE
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 3
|
||||
|
||||
#undef XCHAL_INST_FETCH_WIDTH
|
||||
#define XCHAL_INST_FETCH_WIDTH 4
|
||||
|
||||
|
||||
#undef XSHAL_ABI
|
||||
#undef XTHAL_ABI_WINDOWED
|
||||
#undef XTHAL_ABI_CALL0
|
||||
#define XSHAL_ABI XTHAL_ABI_WINDOWED
|
||||
#define XTHAL_ABI_WINDOWED 0
|
||||
#define XTHAL_ABI_CALL0 1
|
||||
|
||||
#endif /* !XTENSA_CONFIG_H */
|
||||
|
|
@ -0,0 +1,472 @@
|
|||
/*
|
||||
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
|
||||
* processor CORE configuration
|
||||
*
|
||||
* See <xtensa/config/core.h>, which includes this file, for more details.
|
||||
*/
|
||||
|
||||
/* Xtensa processor core configuration information.
|
||||
|
||||
Copyright (c) 1999-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef _XTENSA_CORE_CONFIGURATION_H
|
||||
#define _XTENSA_CORE_CONFIGURATION_H
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
|
||||
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 0 /* floating point pkg */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
|
||||
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
|
||||
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
|
||||
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
|
||||
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
|
||||
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
|
||||
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
|
||||
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_SW_VERSION 800002 /* sw version of this header */
|
||||
|
||||
#define XCHAL_CORE_ID "DC_C_233L" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x0002CFEC /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC56707FE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x1040BEEF /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX3.0.2" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 230002 /* major*100+minor */
|
||||
#define XCHAL_HW_REL_LX3 1
|
||||
#define XCHAL_HW_REL_LX3_0 1
|
||||
#define XCHAL_HW_REL_LX3_0_2 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 230000 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 230002 /* latest targeted hw */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 7
|
||||
#define XCHAL_DCACHE_SETWIDTH 7
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 4
|
||||
#define XCHAL_DCACHE_WAYS 4
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 4
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 4
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x001F80FF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00000100
|
||||
#define XCHAL_INTLEVEL3_MASK 0x00200E00
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00001000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00002000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00004000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 2
|
||||
#define XCHAL_INT9_LEVEL 3
|
||||
#define XCHAL_INT10_LEVEL 3
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 4
|
||||
#define XCHAL_INT13_LEVEL 5
|
||||
#define XCHAL_INT14_LEVEL 7
|
||||
#define XCHAL_INT15_LEVEL 1
|
||||
#define XCHAL_INT16_LEVEL 1
|
||||
#define XCHAL_INT17_LEVEL 1
|
||||
#define XCHAL_INT18_LEVEL 1
|
||||
#define XCHAL_INT19_LEVEL 1
|
||||
#define XCHAL_INT20_LEVEL 1
|
||||
#define XCHAL_INT21_LEVEL 3
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL2_NUM 8
|
||||
#define XCHAL_INTLEVEL4_NUM 12
|
||||
#define XCHAL_INTLEVEL5_NUM 13
|
||||
#define XCHAL_INTLEVEL7_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1, 3.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt vectors/levels.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
|
||||
#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x00002000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x00001000
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x00001000
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x00002340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x00002340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180
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||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x000022C0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x000022C0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
/* If none of the above last 4 are set, it's a custom TLB configuration. */
|
||||
#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
||||
Loading…
Reference in New Issue