xtensa: add rt500_adsp toolchain
This adds the Xtensa toolchain for Tensilica Fusion F1 DSP found on NXP RT500 MCU family. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
This commit is contained in:
parent
8d9b4feeab
commit
7d1b95ecfa
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@ -57,6 +57,7 @@ on:
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- xtensa-intel_tgl_adsp_zephyr-elf
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- xtensa-nxp_imx_adsp_zephyr-elf
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- xtensa-nxp_imx8m_adsp_zephyr-elf
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- xtensa-nxp_rt500_adsp_zephyr-elf
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- xtensa-sample_controller_zephyr-elf
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debug:
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description: 'Debug'
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@ -165,6 +166,7 @@ jobs:
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xtensa-intel_tgl_adsp_zephyr-elf) build_target_xtensa_intel_tgl_adsp_zephyr_elf="y";;
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xtensa-nxp_imx_adsp_zephyr-elf) build_target_xtensa_nxp_imx_adsp_zephyr_elf="y";;
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xtensa-nxp_imx8m_adsp_zephyr-elf) build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y";;
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xtensa-nxp_rt500_adsp_zephyr-elf) build_target_xtensa_nxp_rt500_adsp_zephyr_elf="y";;
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xtensa-sample_controller_zephyr-elf) build_target_xtensa_sample_controller_zephyr_elf="y";;
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esac
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@ -201,6 +203,7 @@ jobs:
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build_target_xtensa_intel_tgl_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_imx_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_imx8m_adsp_zephyr_elf="y"
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build_target_xtensa_nxp_rt500_adsp_zephyr_elf="y"
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build_target_xtensa_sample_controller_zephyr_elf="y"
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fi
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@ -277,6 +280,7 @@ jobs:
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[ "${build_target_xtensa_intel_tgl_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-intel_tgl_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_imx_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_imx8m_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_imx8m_adsp_zephyr-elf",'
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[ "${build_target_xtensa_nxp_rt500_adsp_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-nxp_rt500_adsp_zephyr-elf",'
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[ "${build_target_xtensa_sample_controller_zephyr_elf}" == "y" ] && MATRIX_TARGETS+='"xtensa-sample_controller_zephyr-elf",'
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MATRIX_TARGETS+=']'
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@ -1537,6 +1541,9 @@ jobs:
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xtensa-nxp_imx8m_adsp_zephyr-elf)
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PLATFORM_ARGS+="-p nxp_adsp_imx8m "
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;;
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xtensa-nxp_rt500_adsp_zephyr-elf)
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PLATFORM_ARGS+="-p nxp_adsp_rt500 "
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;;
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xtensa-sample_controller_zephyr-elf)
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PLATFORM_ARGS+="-p qemu_xtensa "
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;;
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@ -15,7 +15,7 @@ The toolchains for the following target architectures are supported:
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- SPARC (32-bit and 64-bit; SPARC V8, SPARC V9)
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- x86 (32-bit and 64-bit)
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- Xtensa (sample_controller, intel_ace15_mtpm, intel_tgl_adsp,
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nxp_imx_adsp, nxp_imx8m_adsp, espressif_esp32, espressif_esp32s2,
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nxp_imx_adsp, nxp_imx8m_adsp, nxp_rt500_adsp, espressif_esp32, espressif_esp32s2,
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espressif_esp32s3)
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The following host tools are available as part of the Zephyr SDK:
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@ -0,0 +1,9 @@
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CT_CONFIG_VERSION="3"
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CT_EXPERIMENTAL=y
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CT_OVERLAY_LOCATION="overlays"
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CT_OVERLAY_NAME="nxp_rt500_adsp"
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CT_ARCH_XTENSA=y
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CT_XTENSA_CUSTOM=y
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CT_TARGET_VENDOR="nxp_rt500_adsp_zephyr"
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CT_TARGET_CFLAGS="-ftls-model=local-exec"
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CT_CC_GCC_CONFIG_TLS=n
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,189 @@
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/* Xtensa configuration settings.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef XTENSA_CONFIG_H
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#define XTENSA_CONFIG_H
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/* The macros defined here match those with the same names in the Xtensa
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compile-time HAL (Hardware Abstraction Layer). Please refer to the
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Xtensa System Software Reference Manual for documentation of these
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macros. */
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#undef XCHAL_HAVE_BE
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#define XCHAL_HAVE_BE 0
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#undef XCHAL_HAVE_DENSITY
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#define XCHAL_HAVE_DENSITY 1
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#undef XCHAL_HAVE_CONST16
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#define XCHAL_HAVE_CONST16 0
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#undef XCHAL_HAVE_ABS
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#define XCHAL_HAVE_ABS 1
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#undef XCHAL_HAVE_ADDX
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#define XCHAL_HAVE_ADDX 1
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#undef XCHAL_HAVE_L32R
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#define XCHAL_HAVE_L32R 1
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#undef XSHAL_USE_ABSOLUTE_LITERALS
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#define XSHAL_USE_ABSOLUTE_LITERALS 0
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#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
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#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
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#undef XCHAL_HAVE_MAC16
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#define XCHAL_HAVE_MAC16 1
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#undef XCHAL_HAVE_MUL16
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#define XCHAL_HAVE_MUL16 0
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#undef XCHAL_HAVE_MUL32
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#define XCHAL_HAVE_MUL32 0
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#undef XCHAL_HAVE_MUL32_HIGH
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#define XCHAL_HAVE_MUL32_HIGH 0
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#undef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 1
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#undef XCHAL_HAVE_NSA
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#define XCHAL_HAVE_NSA 1
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#undef XCHAL_HAVE_MINMAX
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#define XCHAL_HAVE_MINMAX 1
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#undef XCHAL_HAVE_SEXT
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#define XCHAL_HAVE_SEXT 1
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#undef XCHAL_HAVE_LOOPS
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#define XCHAL_HAVE_LOOPS 1
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#undef XCHAL_HAVE_THREADPTR
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#define XCHAL_HAVE_THREADPTR 1
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#undef XCHAL_HAVE_RELEASE_SYNC
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#define XCHAL_HAVE_RELEASE_SYNC 1
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#undef XCHAL_HAVE_S32C1I
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#define XCHAL_HAVE_S32C1I 1
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#undef XCHAL_HAVE_BOOLEANS
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#define XCHAL_HAVE_BOOLEANS 1
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#undef XCHAL_HAVE_FP
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#define XCHAL_HAVE_FP 0
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#undef XCHAL_HAVE_FP_DIV
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#define XCHAL_HAVE_FP_DIV 0
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#undef XCHAL_HAVE_FP_RECIP
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#define XCHAL_HAVE_FP_RECIP 0
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#undef XCHAL_HAVE_FP_SQRT
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#define XCHAL_HAVE_FP_SQRT 0
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#undef XCHAL_HAVE_FP_RSQRT
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#define XCHAL_HAVE_FP_RSQRT 0
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#undef XCHAL_HAVE_DFP_ACCEL
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#define XCHAL_HAVE_DFP_ACCEL 0
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/* For backward compatibility */
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#undef XCHAL_HAVE_DFP_accel
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#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
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#undef XCHAL_HAVE_WINDOWED
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#define XCHAL_HAVE_WINDOWED 1
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#undef XCHAL_NUM_AREGS
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#define XCHAL_NUM_AREGS 32
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#undef XCHAL_HAVE_WIDE_BRANCHES
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#define XCHAL_HAVE_WIDE_BRANCHES 0
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#undef XCHAL_HAVE_PREDICTED_BRANCHES
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0
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#undef XCHAL_ICACHE_SIZE
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#define XCHAL_ICACHE_SIZE 0
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#undef XCHAL_DCACHE_SIZE
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#define XCHAL_DCACHE_SIZE 0
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#undef XCHAL_ICACHE_LINESIZE
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#define XCHAL_ICACHE_LINESIZE 16
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#undef XCHAL_DCACHE_LINESIZE
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#define XCHAL_DCACHE_LINESIZE 16
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#undef XCHAL_ICACHE_LINEWIDTH
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#define XCHAL_ICACHE_LINEWIDTH 4
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#undef XCHAL_DCACHE_LINEWIDTH
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#define XCHAL_DCACHE_LINEWIDTH 4
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#undef XCHAL_DCACHE_IS_WRITEBACK
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#define XCHAL_DCACHE_IS_WRITEBACK 0
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#undef XCHAL_HAVE_MMU
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#define XCHAL_HAVE_MMU 0
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#undef XCHAL_HAVE_DEBUG
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#define XCHAL_HAVE_DEBUG 1
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#undef XCHAL_NUM_IBREAK
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#define XCHAL_NUM_IBREAK 2
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#undef XCHAL_NUM_DBREAK
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#define XCHAL_NUM_DBREAK 2
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#undef XCHAL_DEBUGLEVEL
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#define XCHAL_DEBUGLEVEL 4
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#undef XCHAL_MAX_INSTRUCTION_SIZE
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#define XCHAL_MAX_INSTRUCTION_SIZE 6
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#undef XCHAL_INST_FETCH_WIDTH
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#define XCHAL_INST_FETCH_WIDTH 8
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#undef XSHAL_ABI
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#undef XTHAL_ABI_WINDOWED
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#undef XTHAL_ABI_CALL0
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#define XSHAL_ABI XTHAL_ABI_WINDOWED
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#define XTHAL_ABI_WINDOWED 0
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#define XTHAL_ABI_CALL0 1
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#undef XCHAL_M_STAGE
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#define XCHAL_M_STAGE 3
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#undef XTENSA_MARCH_LATEST
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#define XTENSA_MARCH_LATEST 260004
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#undef XTENSA_MARCH_EARLIEST
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#define XTENSA_MARCH_EARLIEST 260004
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#endif /* !XTENSA_CONFIG_H */
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@ -0,0 +1,189 @@
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/* Xtensa configuration settings.
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Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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Free Software Foundation, Inc.
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Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef XTENSA_CONFIG_H
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#define XTENSA_CONFIG_H
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/* The macros defined here match those with the same names in the Xtensa
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compile-time HAL (Hardware Abstraction Layer). Please refer to the
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Xtensa System Software Reference Manual for documentation of these
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macros. */
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#undef XCHAL_HAVE_BE
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#define XCHAL_HAVE_BE 0
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#undef XCHAL_HAVE_DENSITY
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#define XCHAL_HAVE_DENSITY 1
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#undef XCHAL_HAVE_CONST16
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#define XCHAL_HAVE_CONST16 0
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#undef XCHAL_HAVE_ABS
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#define XCHAL_HAVE_ABS 1
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#undef XCHAL_HAVE_ADDX
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#define XCHAL_HAVE_ADDX 1
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#undef XCHAL_HAVE_L32R
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#define XCHAL_HAVE_L32R 1
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#undef XSHAL_USE_ABSOLUTE_LITERALS
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#define XSHAL_USE_ABSOLUTE_LITERALS 0
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#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
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#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
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#undef XCHAL_HAVE_MAC16
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#define XCHAL_HAVE_MAC16 1
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#undef XCHAL_HAVE_MUL16
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#define XCHAL_HAVE_MUL16 0
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#undef XCHAL_HAVE_MUL32
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#define XCHAL_HAVE_MUL32 0
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#undef XCHAL_HAVE_MUL32_HIGH
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#define XCHAL_HAVE_MUL32_HIGH 0
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#undef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 1
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#undef XCHAL_HAVE_NSA
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#define XCHAL_HAVE_NSA 1
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#undef XCHAL_HAVE_MINMAX
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#define XCHAL_HAVE_MINMAX 1
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#undef XCHAL_HAVE_SEXT
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#define XCHAL_HAVE_SEXT 1
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#undef XCHAL_HAVE_LOOPS
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#define XCHAL_HAVE_LOOPS 1
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#undef XCHAL_HAVE_THREADPTR
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#define XCHAL_HAVE_THREADPTR 1
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#undef XCHAL_HAVE_RELEASE_SYNC
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#define XCHAL_HAVE_RELEASE_SYNC 1
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#undef XCHAL_HAVE_S32C1I
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#define XCHAL_HAVE_S32C1I 1
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#undef XCHAL_HAVE_BOOLEANS
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#define XCHAL_HAVE_BOOLEANS 1
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#undef XCHAL_HAVE_FP
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#define XCHAL_HAVE_FP 0
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#undef XCHAL_HAVE_FP_DIV
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#define XCHAL_HAVE_FP_DIV 0
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#undef XCHAL_HAVE_FP_RECIP
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#define XCHAL_HAVE_FP_RECIP 0
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#undef XCHAL_HAVE_FP_SQRT
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#define XCHAL_HAVE_FP_SQRT 0
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#undef XCHAL_HAVE_FP_RSQRT
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#define XCHAL_HAVE_FP_RSQRT 0
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#undef XCHAL_HAVE_DFP_ACCEL
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#define XCHAL_HAVE_DFP_ACCEL 0
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/* For backward compatibility */
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#undef XCHAL_HAVE_DFP_accel
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#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
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#undef XCHAL_HAVE_WINDOWED
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#define XCHAL_HAVE_WINDOWED 1
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#undef XCHAL_NUM_AREGS
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#define XCHAL_NUM_AREGS 32
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#undef XCHAL_HAVE_WIDE_BRANCHES
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#define XCHAL_HAVE_WIDE_BRANCHES 0
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#undef XCHAL_HAVE_PREDICTED_BRANCHES
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0
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#undef XCHAL_ICACHE_SIZE
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#define XCHAL_ICACHE_SIZE 0
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#undef XCHAL_DCACHE_SIZE
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#define XCHAL_DCACHE_SIZE 0
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#undef XCHAL_ICACHE_LINESIZE
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#define XCHAL_ICACHE_LINESIZE 16
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#undef XCHAL_DCACHE_LINESIZE
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#define XCHAL_DCACHE_LINESIZE 16
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#undef XCHAL_ICACHE_LINEWIDTH
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#define XCHAL_ICACHE_LINEWIDTH 4
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#undef XCHAL_DCACHE_LINEWIDTH
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#define XCHAL_DCACHE_LINEWIDTH 4
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#undef XCHAL_DCACHE_IS_WRITEBACK
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#define XCHAL_DCACHE_IS_WRITEBACK 0
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#undef XCHAL_HAVE_MMU
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#define XCHAL_HAVE_MMU 0
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#undef XCHAL_HAVE_DEBUG
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#define XCHAL_HAVE_DEBUG 1
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#undef XCHAL_NUM_IBREAK
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#define XCHAL_NUM_IBREAK 2
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#undef XCHAL_NUM_DBREAK
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#define XCHAL_NUM_DBREAK 2
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#undef XCHAL_DEBUGLEVEL
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#define XCHAL_DEBUGLEVEL 4
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#undef XCHAL_MAX_INSTRUCTION_SIZE
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#define XCHAL_MAX_INSTRUCTION_SIZE 6
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#undef XCHAL_INST_FETCH_WIDTH
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#define XCHAL_INST_FETCH_WIDTH 8
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#undef XSHAL_ABI
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#undef XTHAL_ABI_WINDOWED
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#undef XTHAL_ABI_CALL0
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#define XSHAL_ABI XTHAL_ABI_WINDOWED
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#define XTHAL_ABI_WINDOWED 0
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#define XTHAL_ABI_CALL0 1
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||||
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#undef XCHAL_M_STAGE
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#define XCHAL_M_STAGE 3
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#undef XTENSA_MARCH_LATEST
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#define XTENSA_MARCH_LATEST 260004
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#undef XTENSA_MARCH_EARLIEST
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#define XTENSA_MARCH_EARLIEST 260004
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#endif /* !XTENSA_CONFIG_H */
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,42 @@
|
|||
/* Customized table mapping between kernel xtregset and GDB register cache.
|
||||
|
||||
Copyright (c) 2007-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
typedef struct {
|
||||
int gdb_regnum;
|
||||
int gdb_offset;
|
||||
int ptrace_cp_offset;
|
||||
int ptrace_offset;
|
||||
int size;
|
||||
int coproc;
|
||||
int dbnum;
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 192
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 0 }
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/* Customized table mapping between kernel xtregset and GDB register cache.
|
||||
|
||||
Copyright (c) 2007-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
typedef struct {
|
||||
int gdb_regnum;
|
||||
int gdb_offset;
|
||||
int ptrace_cp_offset;
|
||||
int ptrace_offset;
|
||||
int size;
|
||||
int coproc;
|
||||
int dbnum;
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 192
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 0 }
|
||||
};
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
name:xtensa
|
||||
expedite:pc,windowbase,windowstart
|
||||
32:pc
|
||||
32:ar0
|
||||
32:ar1
|
||||
32:ar2
|
||||
32:ar3
|
||||
32:ar4
|
||||
32:ar5
|
||||
32:ar6
|
||||
32:ar7
|
||||
32:ar8
|
||||
32:ar9
|
||||
32:ar10
|
||||
32:ar11
|
||||
32:ar12
|
||||
32:ar13
|
||||
32:ar14
|
||||
32:ar15
|
||||
32:ar16
|
||||
32:ar17
|
||||
32:ar18
|
||||
32:ar19
|
||||
32:ar20
|
||||
32:ar21
|
||||
32:ar22
|
||||
32:ar23
|
||||
32:ar24
|
||||
32:ar25
|
||||
32:ar26
|
||||
32:ar27
|
||||
32:ar28
|
||||
32:ar29
|
||||
32:ar30
|
||||
32:ar31
|
||||
32:lbeg
|
||||
32:lend
|
||||
32:lcount
|
||||
32:sar
|
||||
32:windowbase
|
||||
32:windowstart
|
||||
32:configid0
|
||||
32:configid1
|
||||
32:ps
|
||||
32:threadptr
|
||||
32:br
|
||||
32:scompare1
|
||||
32:acclo
|
||||
32:acchi
|
||||
32:m0
|
||||
32:m1
|
||||
32:m2
|
||||
32:m3
|
||||
32:expstate
|
||||
64:aed0
|
||||
64:aed1
|
||||
64:aed2
|
||||
64:aed3
|
||||
64:aed4
|
||||
64:aed5
|
||||
64:aed6
|
||||
64:aed7
|
||||
64:aed8
|
||||
64:aed9
|
||||
64:aed10
|
||||
64:aed11
|
||||
64:u0
|
||||
64:u1
|
||||
64:u2
|
||||
64:u3
|
||||
64:circ
|
||||
64:tablefirstsearchnext
|
||||
64:fusionmisc
|
||||
32:fcr_fsr
|
|
@ -0,0 +1,132 @@
|
|||
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
|
||||
|
||||
Copyright (c) 2003-2022 Cadence Design Systems, Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#define XTENSA_CONFIG_VERSION 0x60
|
||||
|
||||
#include "defs.h"
|
||||
#include "xtensa-config.h"
|
||||
#include "xtensa-tdep.h"
|
||||
|
||||
|
||||
|
||||
/* Masked registers. */
|
||||
xtensa_reg_mask_t xtensa_submask0[] = { { 43, 0, 1 } };
|
||||
const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
|
||||
xtensa_reg_mask_t xtensa_submask1[] = { { 43, 1, 1 } };
|
||||
const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
|
||||
xtensa_reg_mask_t xtensa_submask2[] = { { 43, 2, 1 } };
|
||||
const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
|
||||
xtensa_reg_mask_t xtensa_submask3[] = { { 43, 3, 1 } };
|
||||
const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
|
||||
xtensa_reg_mask_t xtensa_submask4[] = { { 43, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
|
||||
xtensa_reg_mask_t xtensa_submask5[] = { { 43, 5, 1 } };
|
||||
const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
|
||||
xtensa_reg_mask_t xtensa_submask6[] = { { 43, 6, 1 } };
|
||||
const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
|
||||
xtensa_reg_mask_t xtensa_submask7[] = { { 43, 7, 1 } };
|
||||
const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
|
||||
xtensa_reg_mask_t xtensa_submask8[] = { { 43, 8, 1 } };
|
||||
const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
|
||||
xtensa_reg_mask_t xtensa_submask9[] = { { 43, 9, 1 } };
|
||||
const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
|
||||
xtensa_reg_mask_t xtensa_submask10[] = { { 43, 10, 1 } };
|
||||
const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
|
||||
xtensa_reg_mask_t xtensa_submask11[] = { { 43, 11, 1 } };
|
||||
const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
|
||||
xtensa_reg_mask_t xtensa_submask12[] = { { 43, 12, 1 } };
|
||||
const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
|
||||
xtensa_reg_mask_t xtensa_submask13[] = { { 43, 13, 1 } };
|
||||
const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
|
||||
xtensa_reg_mask_t xtensa_submask14[] = { { 43, 14, 1 } };
|
||||
const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
|
||||
xtensa_reg_mask_t xtensa_submask15[] = { { 43, 15, 1 } };
|
||||
const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
|
||||
xtensa_reg_mask_t xtensa_submask16[] = { { 41, 0, 4 } };
|
||||
const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
|
||||
xtensa_reg_mask_t xtensa_submask17[] = { { 41, 5, 1 } };
|
||||
const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
|
||||
xtensa_reg_mask_t xtensa_submask18[] = { { 41, 18, 1 } };
|
||||
const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
|
||||
xtensa_reg_mask_t xtensa_submask19[] = { { 41, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
|
||||
xtensa_reg_mask_t xtensa_submask20[] = { { 41, 16, 2 } };
|
||||
const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
|
||||
xtensa_reg_mask_t xtensa_submask21[] = { { 41, 8, 4 } };
|
||||
const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
|
||||
xtensa_reg_mask_t xtensa_submask22[] = { { 45, 0, 32 }, { 46, 0, 8 } };
|
||||
const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };
|
||||
xtensa_reg_mask_t xtensa_submask23[] = { { 105, 8, 4 } };
|
||||
const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
|
||||
xtensa_reg_mask_t xtensa_submask24[] = { { 70, 7, 1 } };
|
||||
const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 };
|
||||
xtensa_reg_mask_t xtensa_submask25[] = { { 68, 32, 32 } };
|
||||
const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };
|
||||
xtensa_reg_mask_t xtensa_submask26[] = { { 68, 0, 32 } };
|
||||
const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
|
||||
xtensa_reg_mask_t xtensa_submask27[] = { { 70, 0, 7 } };
|
||||
const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
|
||||
xtensa_reg_mask_t xtensa_submask28[] = { { 70, 8, 1 } };
|
||||
const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
|
||||
xtensa_reg_mask_t xtensa_submask29[] = { { 70, 17, 32 } };
|
||||
const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
|
||||
xtensa_reg_mask_t xtensa_submask30[] = { { 70, 13, 4 } };
|
||||
const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
|
||||
xtensa_reg_mask_t xtensa_submask31[] = { { 70, 9, 4 } };
|
||||
const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };
|
||||
xtensa_reg_mask_t xtensa_submask32[] = { { 69, 32, 4 } };
|
||||
const xtensa_mask_t xtensa_mask32 = { 1, xtensa_submask32 };
|
||||
xtensa_reg_mask_t xtensa_submask33[] = { { 69, 28, 4 } };
|
||||
const xtensa_mask_t xtensa_mask33 = { 1, xtensa_submask33 };
|
||||
xtensa_reg_mask_t xtensa_submask34[] = { { 69, 0, 27 } };
|
||||
const xtensa_mask_t xtensa_mask34 = { 1, xtensa_submask34 };
|
||||
xtensa_reg_mask_t xtensa_submask35[] = { { 69, 27, 1 } };
|
||||
const xtensa_mask_t xtensa_mask35 = { 1, xtensa_submask35 };
|
||||
xtensa_reg_mask_t xtensa_submask36[] = { { 71, 5, 2 } };
|
||||
const xtensa_mask_t xtensa_mask36 = { 1, xtensa_submask36 };
|
||||
xtensa_reg_mask_t xtensa_submask37[] = { { 71, 4, 1 } };
|
||||
const xtensa_mask_t xtensa_mask37 = { 1, xtensa_submask37 };
|
||||
xtensa_reg_mask_t xtensa_submask38[] = { { 71, 3, 1 } };
|
||||
const xtensa_mask_t xtensa_mask38 = { 1, xtensa_submask38 };
|
||||
xtensa_reg_mask_t xtensa_submask39[] = { { 71, 2, 1 } };
|
||||
const xtensa_mask_t xtensa_mask39 = { 1, xtensa_submask39 };
|
||||
xtensa_reg_mask_t xtensa_submask40[] = { { 71, 1, 1 } };
|
||||
const xtensa_mask_t xtensa_mask40 = { 1, xtensa_submask40 };
|
||||
xtensa_reg_mask_t xtensa_submask41[] = { { 71, 0, 1 } };
|
||||
const xtensa_mask_t xtensa_mask41 = { 1, xtensa_submask41 };
|
||||
|
||||
|
||||
/* Register map. */
|
||||
xtensa_register_t rmap[] =
|
||||
{
|
||||
/* idx ofs bi sz al targno flags cp typ group name */
|
||||
XTREG_END
|
||||
};
|
||||
|
||||
|
||||
|
||||
#ifdef XTENSA_CONFIG_INSTANTIATE
|
||||
XTENSA_CONFIG_INSTANTIATE(rmap,16)
|
||||
#endif
|
||||
|
||||
xtensa_gdbarch_tdep xtensa_tdep (rmap);
|
|
@ -0,0 +1,42 @@
|
|||
/* Customized table mapping between kernel xtregset and GDB register cache.
|
||||
|
||||
Copyright (c) 2007-2010 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
typedef struct {
|
||||
int gdb_regnum;
|
||||
int gdb_offset;
|
||||
int ptrace_cp_offset;
|
||||
int ptrace_offset;
|
||||
int size;
|
||||
int coproc;
|
||||
int dbnum;
|
||||
char* name
|
||||
;} xtensa_regtable_t;
|
||||
|
||||
#define XTENSA_ELF_XTREG_SIZE 192
|
||||
|
||||
const xtensa_regtable_t xtensa_regmap_table[] = {
|
||||
/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
|
||||
{ 0 }
|
||||
};
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
/* Xtensa configuration settings.
|
||||
Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2, or (at your option)
|
||||
any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
|
||||
|
||||
#ifndef XTENSA_CONFIG_H
|
||||
#define XTENSA_CONFIG_H
|
||||
|
||||
/* The macros defined here match those with the same names in the Xtensa
|
||||
compile-time HAL (Hardware Abstraction Layer). Please refer to the
|
||||
Xtensa System Software Reference Manual for documentation of these
|
||||
macros. */
|
||||
|
||||
#undef XCHAL_HAVE_BE
|
||||
#define XCHAL_HAVE_BE 0
|
||||
|
||||
#undef XCHAL_HAVE_DENSITY
|
||||
#define XCHAL_HAVE_DENSITY 1
|
||||
|
||||
#undef XCHAL_HAVE_CONST16
|
||||
#define XCHAL_HAVE_CONST16 0
|
||||
|
||||
#undef XCHAL_HAVE_ABS
|
||||
#define XCHAL_HAVE_ABS 1
|
||||
|
||||
#undef XCHAL_HAVE_ADDX
|
||||
#define XCHAL_HAVE_ADDX 1
|
||||
|
||||
#undef XCHAL_HAVE_L32R
|
||||
#define XCHAL_HAVE_L32R 1
|
||||
|
||||
#undef XSHAL_USE_ABSOLUTE_LITERALS
|
||||
#define XSHAL_USE_ABSOLUTE_LITERALS 0
|
||||
|
||||
#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
|
||||
#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
|
||||
|
||||
#undef XCHAL_HAVE_MAC16
|
||||
#define XCHAL_HAVE_MAC16 1
|
||||
|
||||
#undef XCHAL_HAVE_MUL16
|
||||
#define XCHAL_HAVE_MUL16 0
|
||||
|
||||
#undef XCHAL_HAVE_MUL32
|
||||
#define XCHAL_HAVE_MUL32 0
|
||||
|
||||
#undef XCHAL_HAVE_MUL32_HIGH
|
||||
#define XCHAL_HAVE_MUL32_HIGH 0
|
||||
|
||||
#undef XCHAL_HAVE_DIV32
|
||||
#define XCHAL_HAVE_DIV32 1
|
||||
|
||||
#undef XCHAL_HAVE_NSA
|
||||
#define XCHAL_HAVE_NSA 1
|
||||
|
||||
#undef XCHAL_HAVE_MINMAX
|
||||
#define XCHAL_HAVE_MINMAX 1
|
||||
|
||||
#undef XCHAL_HAVE_SEXT
|
||||
#define XCHAL_HAVE_SEXT 1
|
||||
|
||||
#undef XCHAL_HAVE_LOOPS
|
||||
#define XCHAL_HAVE_LOOPS 1
|
||||
|
||||
#undef XCHAL_HAVE_THREADPTR
|
||||
#define XCHAL_HAVE_THREADPTR 1
|
||||
|
||||
#undef XCHAL_HAVE_RELEASE_SYNC
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1
|
||||
|
||||
#undef XCHAL_HAVE_S32C1I
|
||||
#define XCHAL_HAVE_S32C1I 1
|
||||
|
||||
#undef XCHAL_HAVE_BOOLEANS
|
||||
#define XCHAL_HAVE_BOOLEANS 1
|
||||
|
||||
#undef XCHAL_HAVE_FP
|
||||
#define XCHAL_HAVE_FP 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_DIV
|
||||
#define XCHAL_HAVE_FP_DIV 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_RECIP
|
||||
#define XCHAL_HAVE_FP_RECIP 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_SQRT
|
||||
#define XCHAL_HAVE_FP_SQRT 0
|
||||
|
||||
#undef XCHAL_HAVE_FP_RSQRT
|
||||
#define XCHAL_HAVE_FP_RSQRT 0
|
||||
|
||||
#undef XCHAL_HAVE_DFP_ACCEL
|
||||
#define XCHAL_HAVE_DFP_ACCEL 0
|
||||
/* For backward compatibility */
|
||||
#undef XCHAL_HAVE_DFP_accel
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
|
||||
|
||||
#undef XCHAL_HAVE_WINDOWED
|
||||
#define XCHAL_HAVE_WINDOWED 1
|
||||
|
||||
#undef XCHAL_NUM_AREGS
|
||||
#define XCHAL_NUM_AREGS 32
|
||||
|
||||
#undef XCHAL_HAVE_WIDE_BRANCHES
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0
|
||||
|
||||
#undef XCHAL_HAVE_PREDICTED_BRANCHES
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0
|
||||
|
||||
|
||||
#undef XCHAL_ICACHE_SIZE
|
||||
#define XCHAL_ICACHE_SIZE 0
|
||||
|
||||
#undef XCHAL_DCACHE_SIZE
|
||||
#define XCHAL_DCACHE_SIZE 0
|
||||
|
||||
#undef XCHAL_ICACHE_LINESIZE
|
||||
#define XCHAL_ICACHE_LINESIZE 16
|
||||
|
||||
#undef XCHAL_DCACHE_LINESIZE
|
||||
#define XCHAL_DCACHE_LINESIZE 16
|
||||
|
||||
#undef XCHAL_ICACHE_LINEWIDTH
|
||||
#define XCHAL_ICACHE_LINEWIDTH 4
|
||||
|
||||
#undef XCHAL_DCACHE_LINEWIDTH
|
||||
#define XCHAL_DCACHE_LINEWIDTH 4
|
||||
|
||||
#undef XCHAL_DCACHE_IS_WRITEBACK
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 0
|
||||
|
||||
|
||||
#undef XCHAL_HAVE_MMU
|
||||
#define XCHAL_HAVE_MMU 0
|
||||
|
||||
|
||||
#undef XCHAL_HAVE_DEBUG
|
||||
#define XCHAL_HAVE_DEBUG 1
|
||||
|
||||
#undef XCHAL_NUM_IBREAK
|
||||
#define XCHAL_NUM_IBREAK 2
|
||||
|
||||
#undef XCHAL_NUM_DBREAK
|
||||
#define XCHAL_NUM_DBREAK 2
|
||||
|
||||
#undef XCHAL_DEBUGLEVEL
|
||||
#define XCHAL_DEBUGLEVEL 4
|
||||
|
||||
|
||||
#undef XCHAL_MAX_INSTRUCTION_SIZE
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 6
|
||||
|
||||
#undef XCHAL_INST_FETCH_WIDTH
|
||||
#define XCHAL_INST_FETCH_WIDTH 8
|
||||
|
||||
|
||||
#undef XSHAL_ABI
|
||||
#undef XTHAL_ABI_WINDOWED
|
||||
#undef XTHAL_ABI_CALL0
|
||||
#define XSHAL_ABI XTHAL_ABI_WINDOWED
|
||||
#define XTHAL_ABI_WINDOWED 0
|
||||
#define XTHAL_ABI_CALL0 1
|
||||
|
||||
|
||||
#undef XCHAL_M_STAGE
|
||||
#define XCHAL_M_STAGE 3
|
||||
|
||||
#undef XTENSA_MARCH_LATEST
|
||||
#define XTENSA_MARCH_LATEST 260004
|
||||
|
||||
#undef XTENSA_MARCH_EARLIEST
|
||||
#define XTENSA_MARCH_EARLIEST 260004
|
||||
|
||||
|
||||
#endif /* !XTENSA_CONFIG_H */
|
|
@ -0,0 +1,828 @@
|
|||
/*
|
||||
* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
|
||||
* processor CORE configuration
|
||||
*
|
||||
* See <xtensa/config/core.h>, which includes this file, for more details.
|
||||
*/
|
||||
|
||||
/* Xtensa processor core configuration information.
|
||||
|
||||
Copyright (c) 1999-2022 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef XTENSA_CORE_CONFIGURATION_H_
|
||||
#define XTENSA_CORE_CONFIGURATION_H_
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for Any Code, USER or PRIVILEGED
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
|
||||
* configured, and a value of 0 otherwise. These macros are always defined.
|
||||
*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
ISA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
|
||||
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
|
||||
#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
|
||||
#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
|
||||
#define XCHAL_MAX_INSTRUCTION_SIZE 6 /* max instr bytes (3..8) */
|
||||
#define XCHAL_HAVE_DEBUG 1 /* debug option */
|
||||
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
|
||||
#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
|
||||
#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */
|
||||
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
|
||||
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
|
||||
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
|
||||
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
|
||||
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
|
||||
#define XCHAL_HAVE_MUL16 0 /* MUL16S/MUL16U instructions */
|
||||
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
|
||||
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
|
||||
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
|
||||
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
|
||||
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
|
||||
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
|
||||
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
|
||||
#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
|
||||
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
|
||||
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
|
||||
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
|
||||
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
|
||||
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
|
||||
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
|
||||
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
|
||||
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
|
||||
#define XCHAL_NUM_CONTEXTS 1 /* */
|
||||
#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
|
||||
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
|
||||
#define XCHAL_HAVE_PRID 1 /* processor ID register */
|
||||
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
|
||||
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
|
||||
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
|
||||
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
|
||||
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
|
||||
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
|
||||
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
|
||||
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
|
||||
#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
|
||||
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
|
||||
#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */
|
||||
#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
|
||||
#define XCHAL_HAVE_LX 1 /* LX core */
|
||||
#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */
|
||||
#define XCHAL_HAVE_RNX 0 /* RNX core (starting RJ) */
|
||||
|
||||
#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */
|
||||
|
||||
#define XCHAL_HAVE_FUSION 1 /* Fusion */
|
||||
#define XCHAL_HAVE_FUSION_FP 1 /* Fusion FP option */
|
||||
#define XCHAL_HAVE_FUSION_LOW_POWER 1 /* Fusion Low Power option */
|
||||
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
|
||||
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
|
||||
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
|
||||
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
|
||||
#define XCHAL_HAVE_FUSION_AVS 1 /* Fusion AVS option */
|
||||
#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 1 /* Fusion 16-bit Baseband option */
|
||||
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
|
||||
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
|
||||
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */
|
||||
#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */
|
||||
#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */
|
||||
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3 1
|
||||
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
|
||||
#define XCHAL_HAVE_HIFI1 0 /* HiFi1 */
|
||||
#define XCHAL_HAVE_HIFI1_VFPU 0 /* HiFi1 VFPU option */
|
||||
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
|
||||
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
|
||||
#define XCHAL_HAVE_HIFI_MINI 0
|
||||
|
||||
|
||||
|
||||
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
|
||||
#define XCHAL_HAVE_USER_SPFPU 1 /* user SP floating-point pkg */
|
||||
#define XCHAL_HAVE_FP 1 /* single prec floating point */
|
||||
#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
|
||||
#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
|
||||
#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
|
||||
#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
|
||||
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
|
||||
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
|
||||
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
|
||||
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
|
||||
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
|
||||
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
|
||||
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
|
||||
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
|
||||
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
|
||||
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
|
||||
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
|
||||
|
||||
#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
|
||||
#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
|
||||
#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
|
||||
#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
|
||||
#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
|
||||
#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
|
||||
|
||||
#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */
|
||||
#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */
|
||||
#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */
|
||||
#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */
|
||||
#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */
|
||||
|
||||
#define XCHAL_HAVE_PDX 0 /* PDX-LX */
|
||||
#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
|
||||
#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */
|
||||
#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */
|
||||
#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */
|
||||
#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */
|
||||
|
||||
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
|
||||
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
|
||||
#define XCHAL_HAVE_BALL 0
|
||||
#define XCHAL_HAVE_BALLAP 0
|
||||
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
|
||||
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
|
||||
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
|
||||
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
|
||||
#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/
|
||||
#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/
|
||||
#define XCHAL_HAVE_CONNX_B_DP_VFPU 0 /* Double-precision Vector Floating-point option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_DPX_VFPU 0 /* Double-precision Vector Floating-point option on FP Machine*/
|
||||
#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_HP_VFPU 0 /* Half-precision Vector Floating-point option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */
|
||||
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
|
||||
#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
|
||||
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
|
||||
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
|
||||
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
|
||||
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
|
||||
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
|
||||
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
|
||||
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
|
||||
#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
|
||||
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
|
||||
|
||||
#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
|
||||
#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
|
||||
#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6, Q7 or Q8 */
|
||||
#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
|
||||
#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
|
||||
#define XCHAL_HAVE_VISION_DP_VFPU 0 /* dp_vfpu option on Vision Q7/Q8 */
|
||||
#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
|
||||
#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */
|
||||
#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */
|
||||
#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */
|
||||
|
||||
#define XCHAL_HAVE_VISIONC 0 /* Vision C */
|
||||
|
||||
#define XCHAL_HAVE_XNNE 0 /* XNNE */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MISC
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
|
||||
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */
|
||||
#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
|
||||
#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
|
||||
#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay
|
||||
(1 = 5-stage, 2 = 7-stage) */
|
||||
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
|
||||
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
|
||||
/* In T1050, applies to selected core load and store instructions (see ISA): */
|
||||
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
|
||||
#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
|
||||
#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
|
||||
#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
|
||||
|
||||
#define XCHAL_UNIFIED_LOADSTORE 0
|
||||
|
||||
#define XCHAL_SW_VERSION 1408000 /* sw version of this header */
|
||||
#define XCHAL_SW_VERSION_MAJOR 14000 /* major ver# of sw */
|
||||
#define XCHAL_SW_VERSION_MINOR 8 /* minor ver# of sw */
|
||||
#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */
|
||||
#define XCHAL_SW_MINOR_VERSION 1408000 /* with zeroed micro */
|
||||
#define XCHAL_SW_MICRO_VERSION 1408000
|
||||
|
||||
#define XCHAL_CORE_ID "nxp_rt500_RI2021_8_newlib" /* alphanum core name
|
||||
(CoreID) set in the Xtensa
|
||||
Processor Generator */
|
||||
|
||||
#define XCHAL_BUILD_UNIQUE_ID 0x0009B383 /* 22-bit sw build ID */
|
||||
|
||||
/*
|
||||
* These definitions describe the hardware targeted by this software.
|
||||
*/
|
||||
#define XCHAL_HW_CONFIGID0 0xC2B0F7FE /* ConfigID hi 32 bits*/
|
||||
#define XCHAL_HW_CONFIGID1 0x1D076D35 /* ConfigID lo 32 bits*/
|
||||
#define XCHAL_HW_VERSION_NAME "LX6.0.4" /* full version name */
|
||||
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */
|
||||
#define XCHAL_HW_VERSION 260004 /* major*100+(major<2810 ? minor : minor*10+micro) */
|
||||
#define XCHAL_HW_REL_LX6 1
|
||||
#define XCHAL_HW_REL_LX6_0 1
|
||||
#define XCHAL_HW_REL_LX6_0_4 1
|
||||
#define XCHAL_HW_CONFIGID_RELIABLE 1
|
||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 260004 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 260004 /* latest targeted hw */
|
||||
|
||||
/* Config is enabled for functional safety: */
|
||||
#define XCHAL_HAVE_FUNC_SAFETY 0
|
||||
|
||||
/* Config is enabled for secure operation: */
|
||||
#define XCHAL_HAVE_SECURE 0
|
||||
|
||||
#define XCHAL_HAVE_APB 0
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 8 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 8 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 3 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 3 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_ICACHE_SIZE_LOG2 0
|
||||
#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE_LOG2 0
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
|
||||
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 cache */
|
||||
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
|
||||
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
|
||||
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
|
||||
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
|
||||
#define XCHAL_HAVE_CME_DOWNGRADES 0
|
||||
#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
|
||||
#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_ENABLE 0 /* Icache enabled via MEMCTL */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_ENABLE 0 /* Dcache enabled via MEMCTL */
|
||||
|
||||
#define XCHAL_L1SCACHE_SIZE 0
|
||||
#define XCHAL_L1SCACHE_SIZE_LOG2 0
|
||||
#define XCHAL_L1SCACHE_WAYS 1
|
||||
#define XCHAL_L1SCACHE_WAYS_LOG2 0
|
||||
#define XCHAL_L1SCACHE_ACCESS_SIZE 0
|
||||
#define XCHAL_L1SCACHE_BANKS 1
|
||||
|
||||
#define XCHAL_L1VCACHE_SIZE 0
|
||||
|
||||
#define XCHAL_HAVE_L2 0 /* NX L2 cache controller */
|
||||
#define XCHAL_HAVE_L2_CACHE 0
|
||||
#define XCHAL_NUM_CORES_IN_CLUSTER 0
|
||||
|
||||
/* PRID_ID macros are for internal use only ... subject to removal */
|
||||
#define PRID_ID_SHIFT 0
|
||||
#define PRID_ID_BITS 4
|
||||
#define PRID_ID_MASK 0x0000000F
|
||||
|
||||
/* This one is a form of caching, though not architecturally visible: */
|
||||
#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
|
||||
|
||||
#define XCHAL_HAVE_AXI 0 /* AXI bus */
|
||||
#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
|
||||
#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
|
||||
|
||||
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
|
||||
#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 0
|
||||
#define XCHAL_DCACHE_SETWIDTH 0
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 1
|
||||
#define XCHAL_ICACHE_WAYS_LOG2 0
|
||||
#define XCHAL_DCACHE_WAYS 1
|
||||
#define XCHAL_DCACHE_WAYS_LOG2 0
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 0
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 0
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
#define XCHAL_ICACHE_ECC_WIDTH 1
|
||||
#define XCHAL_DCACHE_ECC_WIDTH 1
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 1
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 1
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 0 /* number of banks */
|
||||
|
||||
/* The number of Cache lines associated with a single cache tag */
|
||||
#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
/* Extended memory attributes supported. */
|
||||
#define XCHAL_HAVE_EXT_CA 0
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */
|
||||
#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */
|
||||
|
||||
/* Instruction RAM 0: */
|
||||
#define XCHAL_INSTRAM0_VADDR 0x00000000 /* virtual address */
|
||||
#define XCHAL_INSTRAM0_PADDR 0x00000000 /* physical address */
|
||||
#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */
|
||||
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_HAVE_INSTRAM0 1
|
||||
#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* Instruction RAM 1: */
|
||||
#define XCHAL_INSTRAM1_VADDR 0x00400000 /* virtual address */
|
||||
#define XCHAL_INSTRAM1_PADDR 0x00400000 /* physical address */
|
||||
#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */
|
||||
#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_HAVE_INSTRAM1 1
|
||||
#define XCHAL_INSTRAM1_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* Data RAM 0: */
|
||||
#define XCHAL_DATARAM0_VADDR 0x00800000 /* virtual address */
|
||||
#define XCHAL_DATARAM0_PADDR 0x00800000 /* physical address */
|
||||
#define XCHAL_DATARAM0_SIZE 4194304 /* size in bytes */
|
||||
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
|
||||
#define XCHAL_HAVE_DATARAM0 1
|
||||
#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
/* Data RAM 1: */
|
||||
#define XCHAL_DATARAM1_VADDR 0x00C00000 /* virtual address */
|
||||
#define XCHAL_DATARAM1_PADDR 0x00C00000 /* physical address */
|
||||
#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */
|
||||
#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
|
||||
#define XCHAL_DATARAM1_BANKS 1 /* number of banks */
|
||||
#define XCHAL_HAVE_DATARAM1 1
|
||||
#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
IDMA
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_IDMA 0
|
||||
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 28 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
|
||||
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_EXCM_LEVEL 2 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x0000FFE0
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00FF0006
|
||||
#define XCHAL_INTLEVEL3_MASK 0xFF000018
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00000001
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00000000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x0000FFE0
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00FFFFE6
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0xFFFFFFFE
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0xFFFFFFFE
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFFFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFFFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 5
|
||||
#define XCHAL_INT1_LEVEL 2
|
||||
#define XCHAL_INT2_LEVEL 2
|
||||
#define XCHAL_INT3_LEVEL 3
|
||||
#define XCHAL_INT4_LEVEL 3
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 1
|
||||
#define XCHAL_INT9_LEVEL 1
|
||||
#define XCHAL_INT10_LEVEL 1
|
||||
#define XCHAL_INT11_LEVEL 1
|
||||
#define XCHAL_INT12_LEVEL 1
|
||||
#define XCHAL_INT13_LEVEL 1
|
||||
#define XCHAL_INT14_LEVEL 1
|
||||
#define XCHAL_INT15_LEVEL 1
|
||||
#define XCHAL_INT16_LEVEL 2
|
||||
#define XCHAL_INT17_LEVEL 2
|
||||
#define XCHAL_INT18_LEVEL 2
|
||||
#define XCHAL_INT19_LEVEL 2
|
||||
#define XCHAL_INT20_LEVEL 2
|
||||
#define XCHAL_INT21_LEVEL 2
|
||||
#define XCHAL_INT22_LEVEL 2
|
||||
#define XCHAL_INT23_LEVEL 2
|
||||
#define XCHAL_INT24_LEVEL 3
|
||||
#define XCHAL_INT25_LEVEL 3
|
||||
#define XCHAL_INT26_LEVEL 3
|
||||
#define XCHAL_INT27_LEVEL 3
|
||||
#define XCHAL_INT28_LEVEL 3
|
||||
#define XCHAL_INT29_LEVEL 3
|
||||
#define XCHAL_INT30_LEVEL 3
|
||||
#define XCHAL_INT31_LEVEL 3
|
||||
#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 5 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_PROFILING
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0xFFFFFFE0
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00000001
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000002
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x0000000C
|
||||
#define XCHAL_INTTYPE_MASK_ETIE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_TRAX 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000010
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_WWDT 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_FXLK 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 2 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 3 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 0 /* non-maskable interrupt */
|
||||
#define XCHAL_PROFILING_INTERRUPT 4
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL5_NUM 0
|
||||
/* (There are many interrupts each at level(s) 1, 2, 3.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 5) */
|
||||
#define XCHAL_EXTINT1_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 6 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 7 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 8 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 9 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT7_NUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT9_NUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT10_NUM 14 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 15 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 16 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT13_NUM 17 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT14_NUM 18 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT15_NUM 19 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT16_NUM 20 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT17_NUM 21 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT18_NUM 22 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT19_NUM 23 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT20_NUM 24 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT21_NUM 25 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT22_NUM 26 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT23_NUM 27 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT24_NUM 28 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT25_NUM 29 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT26_NUM 30 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT27_NUM 31 /* (intlevel 3) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 5) */
|
||||
#define XCHAL_INT5_EXTNUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_INT6_EXTNUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_INT7_EXTNUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_INT8_EXTNUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_INT9_EXTNUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_INT10_EXTNUM 6 /* (intlevel 1) */
|
||||
#define XCHAL_INT11_EXTNUM 7 /* (intlevel 1) */
|
||||
#define XCHAL_INT12_EXTNUM 8 /* (intlevel 1) */
|
||||
#define XCHAL_INT13_EXTNUM 9 /* (intlevel 1) */
|
||||
#define XCHAL_INT14_EXTNUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_INT15_EXTNUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_INT16_EXTNUM 12 /* (intlevel 2) */
|
||||
#define XCHAL_INT17_EXTNUM 13 /* (intlevel 2) */
|
||||
#define XCHAL_INT18_EXTNUM 14 /* (intlevel 2) */
|
||||
#define XCHAL_INT19_EXTNUM 15 /* (intlevel 2) */
|
||||
#define XCHAL_INT20_EXTNUM 16 /* (intlevel 2) */
|
||||
#define XCHAL_INT21_EXTNUM 17 /* (intlevel 2) */
|
||||
#define XCHAL_INT22_EXTNUM 18 /* (intlevel 2) */
|
||||
#define XCHAL_INT23_EXTNUM 19 /* (intlevel 2) */
|
||||
#define XCHAL_INT24_EXTNUM 20 /* (intlevel 3) */
|
||||
#define XCHAL_INT25_EXTNUM 21 /* (intlevel 3) */
|
||||
#define XCHAL_INT26_EXTNUM 22 /* (intlevel 3) */
|
||||
#define XCHAL_INT27_EXTNUM 23 /* (intlevel 3) */
|
||||
#define XCHAL_INT28_EXTNUM 24 /* (intlevel 3) */
|
||||
#define XCHAL_INT29_EXTNUM 25 /* (intlevel 3) */
|
||||
#define XCHAL_INT30_EXTNUM 26 /* (intlevel 3) */
|
||||
#define XCHAL_INT31_EXTNUM 27 /* (intlevel 3) */
|
||||
|
||||
#define XCHAL_HAVE_ISB 0 /* No ISB */
|
||||
#define XCHAL_ISB_VADDR 0 /* N/A */
|
||||
#define XCHAL_HAVE_ITB 0 /* No ITB */
|
||||
#define XCHAL_ITB_VADDR 0 /* N/A */
|
||||
|
||||
#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */
|
||||
#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */
|
||||
#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (until T1050)
|
||||
2 == XEA2 (T1040 onwards)
|
||||
3 == XEA3 (LX8/NX/SX onwards)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */
|
||||
#define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 (RNX) */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */
|
||||
#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x00000400 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x00000400
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0x00000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0x00000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x00400000
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x00400000
|
||||
#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR0_VADDR
|
||||
#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR0_PADDR
|
||||
#define XCHAL_USER_VECOFS 0x0000021C
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x0000061C
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x0000061C
|
||||
#define XCHAL_KERNEL_VECOFS 0x000001FC
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x000005FC
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x000005FC
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x0000023C
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x0000063C
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x0000063C
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x00000400
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x00000400
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x0000017C
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x0000057C
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x0000057C
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x0000019C
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x0000059C
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x0000059C
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x000001BC
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x000005BC
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x000005BC
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000001DC
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x000005DC
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x000005DC
|
||||
#define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
|
||||
/* If none of the above last 5 are set, it's a custom TLB configuration. */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MPU
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_MPU 0
|
||||
#define XCHAL_MPU_ENTRIES 0
|
||||
#define XCHAL_MPU_LOCK 0
|
||||
|
||||
#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
|
||||
#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
|
||||
#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
|
||||
|
||||
#define XCHAL_MPU_ALIGN_BITS 0
|
||||
#define XCHAL_MPU_ALIGN 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
CSR Parity
|
||||
------------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_CSR_PARITY 0
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
FLEX-LOCK
|
||||
------------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_FXLK 0
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
WWDT (Windowed Watchdog Timer)
|
||||
------------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_WWDT 0
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* XTENSA_CORE_CONFIGURATION_H_ */
|
||||
|
Loading…
Reference in New Issue