The counter-timer Frequency register is common to all types of counters.
There is no need to pass the type of timer in parameter.
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
The current ARM_TIMER API's Start and EnableIRQ are not working as
expected:
- Start always enables IRQ's
- EnableIRQ always disables the timer
Fix by removing the standalone EnableIRQ API and adding an irq enable
flag to Start API.
Signed-off-by: Rui Sousa <rui.sousa@nxp.com>
Increase the number of MMU translation tables. For the audio
application with ivshmem support, the current limit was being reached.
Signed-off-by: Rui Sousa <rui.sousa@nxp.com>
The MMU config is best known by the application iteself, depending on
the SoC, RTOS and use case being executed. Let the MMU intialization API
function take the config as a paramter for a better flexibility.
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
TODO: Remove dependency on this file by inserting MSR/MRS instructions
directly in the source code.
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
We usually pass a pointer to a variable to get value ; let's do this
with the __MRS() macro as well.
Suggested-by: Rui Sousa <rui.sousa@nxp.com>
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Zephyr has its own implementation of __ISB() and friends ; let's not
redefine them if already defined.
This _workaround_ consists in defining the macros only if they are not
defined yet.
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Ths current parameter (mainCore) is unused ; instead of imposing core 0
as the main code, let the caller decide what core shall initialize the
GIC Distributor.
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
GNU GCC (AS) is not aware of all Aarch64 symbolic system registers names.
Fetch their definitions from the ARM documentation (instruction encoding
from register descriptions).
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
A wrapper of the MU driver into the new Zephyr MBOX model is being
added to the main Zephyr repository. Projects that use the MBOX
driver on i.MX boards need the MU driver in the include paths.
Signed-off-by: Yicheng Li <yichengli@google.com>
The shim driver for eMIOS uses eMIOS_INSTANCE_COUNT as
argument of LISTIFY, therefore the integer literal suffix
must be removed in order for the macros to work correctly
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This relocates an array with base addresses for eMIOS
instances that is supposed to read only as a constant
variable
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Relocate uninitialized non-cacheable variables of Mcl and
Pwm drivers into .nocache (NOLOAD) section defined by Zephyr
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Update RT1170 and RT1160 header options to have correct pin type
information.
Note that due to changes in source data, the following changes have also
been made to the headers:
- the names of SNVS pins have been updated to align with the RM
- XBAR_INOUT mux options now set the associated GPR bit to select the
XBAR pin as an output, while XBAR_IN options leave the GPR bit clear.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update SOC header script for IMX parts to handle configuration register
type correctly. RT11xx SOCs have multiple types of configuration
registers for pins, and this needs to be encoded in the devicetree for
the MUX options. Fix the header generation script to correctly evaluate
the config type based on which bitfields are in the register, instead of
based on the pin name (as this pattern is not valid for all GPIO_DISP
pins)
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP HAL is licensed under the terms of BSD-3. For clarity, the
license file is moved to the root of the NXP HAL repository
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Rename module from `S32` to `NXP_S32` to avoid ambiguity. All other
files and symbols have been already renamed but this was missing to
update.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Set executable bit on board pinctrl script for MCUX. This script
can be run directly on Linux systems, and the execute bit should be set
within file permissions to indicate this.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
And a new clock configuration group for EMAC0 clocks that skips all
other clocks except for EMAC0 Tx/Rx clocks. EMAC0 TS clock is
sourced from FIRC because is not used currently.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The GMAC shim driver uses FEATURE_GMAC_NUM_INSTANCES as argument of
LISTIFY, therefore the integer literal suffix must be removed in order
for the macros to concatenate correctly. This way we can keep the shim
driver generic enough when other SoC is supported and there is no need
to redefine the macro there.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
These files are autogenerated with S32 Design Studio for S32 Platform
using RTD 3.0.0 P01 for S32K3 devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Stephane Viau