Rename the PIT struct from TIMER to CHANNEL so that the MCUX PIT driver
can be reused for S32Z.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce necessary glue code and definitions to build MCUX with S32Z27
devices so that we can leverage existing shim drivers for common NXP hw
blocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
On S32K344 device, there is a backdoor of DTCM that can be
used by the DMA. At application, the source/destination
address and the TCD can be put in to dtcm, then the DMA
driver will access them over backdoor
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Define memory map and configure DMA/DMAMUX features for S32K344.
Note that for compatible with mcux dma3 driver:
- Increasing DMA channel from 32 to 148 in which 12 --> 127
are offset channels. Due to this, the memory map need to
be redefined
- Rename some macros, those's value inherited from RTD's
definition
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
There's already a definition of this register in the main repo code
base, add a guard around it so it does not get redefined, fixes a build
warning.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Patch Icu/Wkpu tool-generated configuration for S32K344 SoCs to
integrate with Zephyr's WKPU interrupt controller shim driver.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The flexcomm and flexio driver structure has changed to
include sub folder for the individual component drivers.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Move used job descriptors in the CAAM driver from the stack to
noncacheable section.
This change has not been accepted by the SDK team and needs to
be maintained here.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The KB define is unnecessarily polluting the namespace (clashes with
zephyr/sys/util.h definition) since it is only used once in a source
file. To fix the problem, definition has been moved to the source file.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Rebased to Core_AArch64.
Signed-off-by: Jiafei Pan <jiafei.pan@nxp.com>
Refine the CPU interface initialization sequence according to the
GIC CPU interface configration guide.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
To mark the connected PE as being online, software must:
- Clear GICR_WAKER.ProcessorSleep to 0.
- Poll GICR_WAKER.ChildrenAsleep until it reads 0.
It is important that software performs these steps before configuring
the CPU interface, otherwise behavior can be UNPREDICTABLE.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
In the processors, which integrates the multi-threaded cores, the
definition of the affinity fields in MPIDR_EL1 is different, the
Affinity0 is used to indicate Thread ID instead of Core ID.
However, the current implementation hard-code to use Affinity0 to
identify Core ID and then index the Redistributor, so it does't
work anymore on these platforms.
This patch remove the hard-code indenification of Redistributor
and change to use the core/thread's affinity fields to match the
Redistributor.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
In some cases, the lower half of available priorities values are reserved by the OS
for critical functions, as part of the legacy security extension feature (for example
in FreeRTOS). By using 2/3 of the max priority of the GIC, we ensure that we have a
valid default value.
Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
In the case of using an hypervisor, we should not setup the affinity
to a specific CPU, as it depends on the CPU used for the guest OS.
Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
Add polling of RWP bit of Distributor and Redistributor CTRL registers to
make sure the effects of previous register writes to the affected register
fields are visible to all logical components of the GIC architecture.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
likely/unlikely() branch prediction macros give some hints to the
compiler to favor either side of a jump instruction and may improve
performances in certain conditions.
Signed-off-by: Stephane Viau <stephane.viau@nxp.com>
Manuel Arguelles