Commit 1be7718c59 wrongly set the RTC
clock source to an external oscillator which is not present in the only
board using this SoC at the moment. Instead use the 32 KHz internal
oscillator which is enabled at PoR and always available.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
SoC S32Z27 folder is renamed to S32Z270 to align with
changes to `CONFIG_SOC_S32Z270`.
Compatibility with hwmv1 is maintained until support is merged to
main.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The following patches are applied to the headers in order to make them
compatible with MCUX FlexCAN driver:
- Substitute regex pattern \bFLEXCAN_ with CAN_
- Replace message buffer RAMn array with a struct for 64-byte payloads
(the only paylod length supported at the moment in MCUX FlexCAN
driver).
- Replace macros for RAM array bytes with macros for message buffer
fields CS, ID, WORD0 and WORD1.
- Define MCR_WAKSRC, MCR_SLFWAK, MCR_WAKMSK and ESR1_WAKINT register
access macros to be able to build with MCUX driver. These fields are
reserved in S32K1xx and not used.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
In order to reuse existing device header with MCUX SDK FTM driver,
is needed to redefine CONTROLS.CSC/CV to CONTROLS.CnSC/CnV.
The change is applied to all devices to allow future use of it, although
for now only will be used on S32K146 devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Removes the S32K3X4-0P55A-1P55A-ERRATA by disabling
FSL_FEATURE_LPSPI_HAS_ERRATA_050456. This allows for
lpspi to work correctly on mr_canhubk3.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Netc shim driver uses 'Netc_Eth_Ip_MSIX_Rx' function.
Need to remove 'static inline' keywords from this function
so that it can be used as an extern function outside of the
file declaration.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Add definitions to use MCUX SDK cache driver for LMEM controller on
S32K146 devices.
Note that `LMEM_PCCCR_ENWRBUF` is not present on S32K1xx devices so it
is defined to have no effect if used in the cache driver.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Netc shim driver uses the macro
FEATURE_NETC_ETH_NUMBER_OF_CTRLS with LISTIFY.
Remove 'u' suffix from macro so that it
can be used with LISTIFY.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Add S32K146 device definitions and overlays in order to reuse
existing MCUX SDK drivers on this SoC.
Drivers enabled: SYSMPU, GPIO, PORT, LPUART.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Configuration generated with S32 Design Studio for S32 Platform,
including Real-Time Drivers package for S32K1xx.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Relocate uninitialized non-cacheable variables
into .nocache (NOLOAD) section defined by Zephyr.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Device headers are instructing CMSIS to configure the MPU,
but S32k1xx devices have an NXP SYSMPU and not an standard Arm MPU.
Defining `__MPU_PRESENT` to 0 so that SYSMPU driver can be used.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Based on S32K1_S32M24_-_R21-11_RTD_2_0_0_D2308.
Components included: device headers, OSIF, Mcu/Clock.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Relocate uninitialized non-cacheable variables of Lcu and Trgmux Mcl
drivers into .nocache (NOLOAD) section defined by Zephyr
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
This commit adds S32DS generated headers to Lcu and Trgmux RTDs
to support Quadrature decoder
Co-authored-by: Mayank Mahajan <mayankmahajan.x@nxp.com>
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Rename the PIT struct from TIMER to CHANNEL so that
the MCUX PIT driver can be reused for S32Z.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Remove 'u' suffix from macros so that they
can be used with LISTIFY in shim drivers.
Set the number of UART LINFlexD instances configured
that bases on the number of devicetree UART nodes enabled.
Set the number of SPI instances configured that bases
on the number of devicetree SPI nodes enabled.
Enable SPI slave support bases on CONFIG_SPI_SLAVE.
Wrap the defined macros of each MRU instance base on
devicetree MRU node so that it is built when node enabled.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Shim drivers use these macros with LISTIFY.
Remove 'u' suffix from macros so that they
can be used with LISTIFY.
Base on commit 3731aefd
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Relocate uninitialized non-cacheable variables
into .nocache (NOLOAD) section defined by Zephyr.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Switch to use `CONFIG_SOC` to define the device name and CPU name
needed to build MCUX drivers and device sources.
The SoC part number for S32 now makes reference to the actual
part number of device as defined in datasheets and should't be
used to define the CPU name.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
As a prerequisite to refactor all those shim drivers to use the
instance-based DT macros and to obtain the peripheral instance index
at compile time as done in f809614136, remove the `u` prefix from
the HAL instance count macros so that they can be used with `LISTIFY`.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This adds specific code for emios icu code which generated
from S32 Design Studio for S32 platform
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
If a channel configured to be use in SAIC, means that the PWM
channel will be used for capture mode which is managed by
eMIOS ICU, do not consider it as used by eMIOS PWM driver
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Rename the PIT struct from TIMER to CHANNEL so that the MCUX PIT driver
can be reused for S32Z.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce necessary glue code and definitions to build MCUX with S32Z27
devices so that we can leverage existing shim drivers for common NXP hw
blocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
On S32K344 device, there is a backdoor of DTCM that can be
used by the DMA. At application, the source/destination
address and the TCD can be put in to dtcm, then the DMA
driver will access them over backdoor
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Define memory map and configure DMA/DMAMUX features for S32K344.
Note that for compatible with mcux dma3 driver:
- Increasing DMA channel from 32 to 148 in which 12 --> 127
are offset channels. Due to this, the memory map need to
be redefined
- Rename some macros, those's value inherited from RTD's
definition
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Patch Icu/Wkpu tool-generated configuration for S32K344 SoCs to
integrate with Zephyr's WKPU interrupt controller shim driver.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Manuel Argüelles