s32: convert to hwmv2

SoC S32Z27 folder is renamed to S32Z270 to align with
changes to `CONFIG_SOC_S32Z270`.
Compatibility with hwmv1 is maintained until support is merged to
main.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>

s32/CMakeLists.txt

@@ -1,20 +1,17 @@
-# Copyright 2022-2023 NXP
+# Copyright 2022-2024 NXP
 
 # Set the SoC specific drivers and configuration to build
-if(${CONFIG_SOC} STREQUAL "s32z27")
+if(HWMv2)
   set(SOC_BASE ${CONFIG_SOC})
-  set(DRIVERS_BASE s32ze)
-elseif(${CONFIG_SOC} MATCHES "s32k3.*")
-  set(SOC_BASE ${CONFIG_SOC})
-  set(DRIVERS_BASE s32k3)
-elseif(${CONFIG_SOC} MATCHES "s32k1.*")
-  set(SOC_BASE ${CONFIG_SOC})
-  set(DRIVERS_BASE s32k1)
 else()
-  message(FATAL_ERROR "SoC ${CONFIG_SOC} not supported")
+  if(${CONFIG_SOC} STREQUAL "s32z27")
+    set(SOC_BASE "s32z270")
+  else()
+    set(SOC_BASE ${CONFIG_SOC})
+  endif()
 endif()
 
-add_subdirectory(drivers/${DRIVERS_BASE})
+add_subdirectory(drivers/${SOC_SERIES})
 add_subdirectory(soc/${SOC_BASE})
 
 if(CONFIG_HAS_MCUX)
@@ -60,7 +57,7 @@ if(CONFIG_HAS_MCUX)
   set(MCUX_SDK_PROJECT_NAME ${ZEPHYR_CURRENT_LIBRARY})
 
   # Translate the SoC name into the MCUX device
-  string(TOUPPER ${CONFIG_SOC} MCUX_DEVICE)
+  string(TOUPPER ${SOC_BASE} MCUX_DEVICE)
 
   # This is normally done in mcux/hal_nxp.cmake, but we need to point to the
   # path on this directory instead

s32/mcux/devices/S32Z270/S32Z270_features.h

@@ -1,11 +1,11 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023-2024 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _S32Z27_FEATURES_H_
-#define _S32Z27_FEATURES_H_
+#ifndef _S32Z270_FEATURES_H_
+#define _S32Z270_FEATURES_H_
 
 /* SOC module features */
 
@@ -41,4 +41,4 @@
 /* @brief Has ERRATA_051617. */
 #define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1)
 
-#endif /* _S32Z27_FEATURES_H_ */
+#endif /* _S32Z270_FEATURES_H_ */

s32/mcux/devices/S32Z270/S32Z270_glue_mcux.h

@@ -1,11 +1,11 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023-2024 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _S32Z27_GLUE_MCUX_H_
-#define _S32Z27_GLUE_MCUX_H_
+#ifndef _S32Z270_GLUE_MCUX_H_
+#define _S32Z270_GLUE_MCUX_H_
 
 /* PIT - Peripheral instance base addresses */
 /** Peripheral PIT0 base address */
@@ -48,4 +48,4 @@
 #define I3C_IBIEXT2_EXT6(x)                     0
 #define I3C_IBIEXT2_EXT7(x)                     0
 
-#endif /* _S32Z27_GLUE_MCUX_H_ */
+#endif /* _S32Z270_GLUE_MCUX_H_ */

s32/mcux/devices/S32Z270/fsl_device_registers.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023-2024 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,12 +13,12 @@
  * The CPU macro should be declared in the project or makefile.
  */
 
-#if defined(CPU_S32Z27)
+#if defined(CPU_S32Z270)
 
 /* CMSIS-style register definitions */
 #include "S32Z2.h"
 /* CPU specific feature definitions */
-#include "S32Z27_features.h"
+#include "S32Z270_features.h"
 
 /* Define the IRQ types for RTU sub-system */
 #define IRQn_Type       RTU_IRQn_Type
@@ -28,7 +28,7 @@
  * In order to reuse RTD CMSIS-based headers for the MCUX drivers, is needed
  * to redefine the peripheral macros from IP_PERIPHERAL_n to PERIPHERALn.
  */
-#include "S32Z27_glue_mcux.h"
+#include "S32Z270_glue_mcux.h"
 
 /* Dummy implementations just to build mcux/mcux-sdk/drivers/common/fsl_common_arm.h */
 #define __GIC_PRESENT   0