s32: drivers: s32k1: patch FlexCAN header for compatibility with MCUX

The following patches are applied to the headers in order to make them
compatible with MCUX FlexCAN driver:

- Substitute regex pattern \bFLEXCAN_ with CAN_
- Replace message buffer RAMn array with a struct for 64-byte payloads
  (the only paylod length supported at the moment in MCUX FlexCAN
   driver).
- Replace macros for RAM array bytes with macros for message buffer
  fields CS, ID, WORD0 and WORD1.
- Define MCR_WAKSRC, MCR_SLFWAK, MCR_WAKMSK and ESR1_WAKINT register
  access macros to be able to build with MCUX driver. These fields are
  reserved in S32K1xx and not used.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>

s32/README

@@ -41,6 +41,7 @@ Patch List for S32K1:
    - Define __MPU_PRESENT as 0 to be able to use NXP SYSMPU driver.
    - Relocate uninitialized non-cacheable variables into .nocache section defined by Zephyr.
    - Rename fields and macros of FTM device headers to allow compatibility with MCUX FTM driver.
+   - Rename fields and macros of FlexCAN device headers to allow compatibility with MCUX FlexCAN driver.
 
 Patch List for S32K3:
    - Relocate uninitialized non-cacheable variables into .nocache section defined by Zephyr.