411 lines
14 KiB
ReStructuredText
411 lines
14 KiB
ReStructuredText
.. _v2m_musca_b1_board:
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ARM V2M Musca B1
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################
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Overview
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********
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The v2m_musca_b1 board configuration is used by Zephyr applications that run
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on the V2M Musca B1 board. It provides support for the Musca B1 ARM Cortex-M33
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CPU and the following devices:
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- Nested Vectored Interrupt Controller (NVIC)
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- System Tick System Clock (SYSTICK)
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- Cortex-M System Design Kit GPIO
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- Cortex-M System Design Kit UART
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.. image:: img/v2m_musca_b1.png
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:width: 435px
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:align: center
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:height: 362px
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:alt: ARM V2M Musca B1
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More information about the board can be found at the `V2M Musca B1 Website`_.
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Hardware
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********
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ARM V2M MUSCA B1 provides the following hardware components:
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- ARM Cortex-M33
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- ARM IoT Subsystem for Cortex-M33
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- Memory
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- 512KB on-chip system memory SRAM.
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- 8MB of external QSPI flash.
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- 4MB on-chip boot eFlash.
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- Debug
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- JTAG, SWD & 4 bit TRACE.
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- DAPLink with a virtual UART port.
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- Arduino interface
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- 16 3V3 GPIO.
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- UART.
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- SPI.
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- I2C.
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- I2S.
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- 3-channel PWM.
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- 6-channel analog interface.
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- On-board Peripherals
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- User RGB LED.
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- Gyro sensor.
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- Combined ADC/DAC/temperature sensor.
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- Secure Digital I/O (SDIO) microSD card.
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User push buttons
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=================
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The v2m_musca_b1 board provides the following user push buttons:
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- PBON power on/off.
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- nSRST: Cortex-M33 system reset and CoreSight debug reset.
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- ISP: Updates DAPLink firmware.
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Supported Features
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===================
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The v2m_musca_b1 board configuration supports the following hardware features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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| WATCHDOG | on-chip | watchdog |
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+-----------+------------+-------------------------------------+
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| TIMER | on-chip | timer |
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+-----------+------------+-------------------------------------+
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Other hardware features are not currently supported by the port.
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See the `V2M Musca B1 Website`_ for a complete list of V2M Musca board hardware
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features.
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The default configuration can be found in the defconfig file:
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``boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig``.
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Interrupt Controller
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====================
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Musca B1 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs.
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A Cortex-M33-based board uses vectored exceptions. This means each exception
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calls a handler directly from the vector table.
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Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed
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in the following table:
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+------+------------+----------------+--------------------------+
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| Exc# | Name | Remarks | Used by Zephyr Kernel |
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+======+============+================+==========================+
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| 1 | Reset | | system initialization |
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+------+------------+----------------+--------------------------+
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| 2 | NMI | | system fatal error |
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+------+------------+----------------+--------------------------+
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| 3 | Hard fault | | system fatal error |
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+------+------------+----------------+--------------------------+
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| 4 | MemManage | MPU fault | system fatal error |
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+------+------------+----------------+--------------------------+
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| 5 | Bus | | system fatal error |
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+------+------------+----------------+--------------------------+
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| 6 | Usage | Undefined | system fatal error |
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| | fault | instruction, | |
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| | | or switch | |
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| | | attempt to ARM | |
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| | | mode | |
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+------+------------+----------------+--------------------------+
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| 7 | SecureFault| Unauthorized | system fatal error |
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| | | access to | |
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| | | secure region | |
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| | | from ns space | |
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+------+------------+----------------+--------------------------+
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| 8 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 9 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 10 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 11 | SVC | | system calls, kernel |
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| | | | run-time exceptions, |
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| | | | and IRQ offloading |
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+------+------------+----------------+--------------------------+
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| 12 | Debug | | system fatal error |
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| | monitor | | |
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+------+------------+----------------+--------------------------+
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| 13 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 14 | PendSV | | context switch |
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+------+------------+----------------+--------------------------+
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| 15 | SYSTICK | | system clock |
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+------+------------+----------------+--------------------------+
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| 16 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 17 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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| 18 | Reserved | | not handled |
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+------+------------+----------------+--------------------------+
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Pin Mapping
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===========
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The ARM V2M Musca B1 Board has 4 GPIO controllers. These controllers are
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responsible for pin-muxing, input/output, pull-up, etc.
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All GPIO controller pins are exposed via the following sequence of pin numbers:
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- Pins 0 - 15 are for GPIO
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Mapping from the ARM V2M Musca B1 Board pins to GPIO controllers:
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.. rst-class:: rst-columns
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- D0 : P0_0
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- D1 : P0_1
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- D2 : P0_2
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- D3 : P0_3
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- D4 : P0_4
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- D5 : P0_5
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- D6 : P0_6
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- D7 : P0_7
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- D8 : P0_8
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- D9 : P0_9
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- D10 : P0_10
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- D11 : P0_11
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- D12 : P0_12
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- D13 : P0_13
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- D14 : P0_14
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- D15 : P0_15
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Peripheral Mapping:
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.. rst-class:: rst-columns
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- UART_0_RX : D0
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- UART_0_TX : D1
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- SPI_0_CS : D10
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- SPI_0_MOSI : D11
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- SPI_0_MISO : D12
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- SPI_0_SCLK : D13
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- I2C_0_SDA : D14
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- I2C_0_SCL : D15
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For mode details please refer to `Musca B1 Technical Reference Manual (TRM)`_.
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RGB LED
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============
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Musca B1 has a built-in RGB LED connected to GPIO[4:2] pins.
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- Red LED connected at GPIO[2] pin,with optional PWM0.
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- Green LED connected at GPIO[3] pin,with optional PWM1.
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- Blue LED connected at GPIO[4] pin,with optional PWM2.
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.. note:: The SCC registers select the functions of pins GPIO[4:2].
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System Clock
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============
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V2M Musca B1 has a 32.768kHz crystal clock. The clock goes to a PLL and is
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multiplied to drive the Cortex-M33 processors and SSE-200 subsystem. The
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default is 40MHz but can be increased to 160MHz maximum for the secondary
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processor (CPU1) via software configuration. The maximum clock frequency
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for the primary processor (CPU0) is 40MHz.
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Serial Port
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===========
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The ARM Musca B1 processor has two UARTs. Both the UARTs have only two wires
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for RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output,
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by default, uses UART1.
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Security components
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===================
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- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define
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secure and non-secure memory maps. By default, all of the memory space is
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defined to be secure accessible only.
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- Secure and Non-secure peripherals via the Peripheral Protection Controller
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(PPC). Peripherals can be assigned as secure or non-secure accessible.
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- Secure boot.
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- Secure `AMBA®`_ interconnect.
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Serial Configuration Controller (SCC)
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=====================================
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The ARM Musca B1 test chip implements a Serial Configuration Control (SCC)
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register. The purpose of this register is to allow individual control of
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clocks, reset-signals and interrupts to peripherals, and pin-muxing.
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Boot memory
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================
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Normal Musca-B1 test chip boot operation is from 4MB eFlash by default, and
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it offers the fastest boot method.
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Musca-B1 test chip also support to boot from 8MB QSPI. You can update the
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DAPLink firmware for either QSPI or eFlash for booting.
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Programming and Debugging
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*************************
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Musca B1 supports the v8m security extension, and by default boots to the
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secure state.
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When building a secure/non-secure application, the secure application will
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have to set the idau/sau and mpc configuration to permit access from the
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non-secure application before jumping.
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The following system components are required to be properly configured during the
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secure firmware:
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- AHB5 TrustZone Memory Protection Controller (MPC).
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- AHB5 TrustZone Peripheral Protection Controller (PPC).
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- Implementation-Defined Attribution Unit (IDAU).
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For more details please refer to `Corelink SSE-200 Subsystem`_.
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Flashing
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========
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DAPLink
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---------
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V2M Musca B1 provides:
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- A USB connection to the host computer, which exposes a Mass Storage and an
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USB Serial Port.
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- A Serial Flash device, which implements the USB flash disk file storage.
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- A physical UART connection which is relayed over interface USB Serial port.
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This interfaces are exposed via DAPLink which provides:
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- Serial Wire Debug (SWD).
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- USB Mass Storage Device (USBMSD).
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- UART.
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- Remote reset.
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For more details please refer
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to the `DAPLink Website`_.
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Building a secure only application
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----------------------------------
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You can build applications in the usual way. Here is an example for
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the :ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: v2m_musca_b1
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:goals: build
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Open a serial terminal (minicom, putty, etc.) with the following settings:
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- Speed: 115200
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- Data: 8 bits
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- Parity: None
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- Stop bits: 1
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Reset the board, and you should see the following message on the corresponding
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serial port:
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.. code-block:: console
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Hello World! musca_b1
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Building a secure/non-secure with Trusted Firmware
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--------------------------------------------------
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The process requires five steps:
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1. Build Trusted Firmware (tfm).
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2. Import it as a library to the Zephyr source folder.
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3. Build Zephyr with a non-secure configuration.
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4. Merge the two binaries together and sign them.
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5. Concatenate the bootloader with the signed image blob.
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In order to build tfm please refer to `Trusted Firmware M Guide`_.
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Follow the build steps for AN521 target while replacing the platform with
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``-DTARGET_PLATFORM=MUSCA_B1`` and compiler (if required) with ``-DCOMPILER=GNUARM``
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Copy over tfm as a library to the Zephyr project source and create a shortcut
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for the secure veneers and necessary header files. All files are in the install
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folder after TF-M built.
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Uploading an application to V2M Musca B1
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----------------------------------------
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Applications must be converted to Intel's hex format before being flashed to a
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V2M Musca B1. An optional bootloader can be prepended to the image.
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The QSPI flash base address alias is 0x0, and the eFlash base address alias is
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0xA000000.
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The image offset is calculated by adding the flash offset to the
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bootloader partition size.
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A third-party tool (srecord) is used to generate the Intel formatted hex image.
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For more information refer to the `Srecord Manual`_.
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.. code-block:: bash
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srec_cat $BIN_BOOTLOADER -Binary -offset $FLASH_OFFSET $BIN_SNS -Binary -offset $IMAGE_OFFSET -o $HEX_FLASHABLE -Intel
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# For a 128K bootloader IMAGE_OFFSET = $FLASH_OFFSET + 0x20000
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srec_cat $BIN_BOOTLOADER -Binary -offset 0xA000000 $BIN_SNS -Binary -offset 0xA020000 -o $HEX_FLASHABLE -Intel
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Connect the V2M Musca B1 to your host computer using the USB port. You should
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see a USB connection exposing a Mass Storage (MUSCA_B) and a USB Serial Port.
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Copy the generated ``zephyr.hex`` in the MUSCA_B drive.
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Reset the board, and you should see the following message on the corresponding
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serial port:
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.. code-block:: console
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Hello World! musca_b1
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.. _V2M Musca B1 Website:
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https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-b-test-chip-board
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.. _Musca B1 Technical Reference Manual (TRM):
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http://infocenter.arm.com/help/topic/com.arm.doc.101312_0000_00_en/arm_musca_b1_test_chip_and_board_technical_reference_manual_101312_0000_00_en.pdf
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.. _DAPLink Website:
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https://github.com/ARMmbed/DAPLink
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.. _Cortex M33 Generic User Guide:
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http://infocenter.arm.com/help/topic/com.arm.doc.100235_0004_00_en/arm_cortex_m33_dgug_100235_0004_00_en.pdf
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.. _Trusted Firmware M Guide:
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https://git.trustedfirmware.org/trusted-firmware-m.git/about/docs/user_guides/tfm_build_instruction.md
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.. _Corelink SSE-200 Subsystem:
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https://developer.arm.com/products/system-design/subsystems/corelink-sse-200-subsystem
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.. _Srecord Manual:
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http://srecord.sourceforge.net/man/man1/srec_cat.html
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.. _IDAU:
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https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau
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.. _AMBA®:
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https://developer.arm.com/products/architecture/system-architectures/amba
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