230 lines
8.0 KiB
ReStructuredText
230 lines
8.0 KiB
ReStructuredText
.. _arty:
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Digilent Arty
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#############
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Overview
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********
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The `Digilent Arty`_ is a line of FPGA-based development boards aimed for makers
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and hobbyists. The Arty is available in several configurations, each with a
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different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series).
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Each board is equipped with on-board JTAG for FPGA programming and debugging,
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LEDs, switches, buttons, DDR3 RAM, and QSPI flash for storing the FPGA
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bitstream.
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.. figure:: ./arty_a7-35.png
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:width: 500px
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:align: center
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:alt: Digilent Arty A7-35
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Digilent Arty A7-35 (Credit: Digilent Inc)
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The Spartan-7 and Artix-7 based Arty board do not contain a CPU, but require a
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so-called soft processor to be instantiated within the FPGA in order to run
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Zephyr. The Zynq-7000 based Arty boards are not yet supported by Zephyr.
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ARM Cortex-M1/M3 DesignStart FPGA
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*********************************
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One way of instantiating soft processors on the Arty is using the `ARM
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DesignStart FPGA`_ Xilinx edition reference designs from ARM. Zephyr supports
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both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design
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targets either the Spartan-7 or Artix-7 based Arty boards, whereas the Cortex-M3
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design only targets the Artix-7 based boards. Zephyr only supports the Artix-7
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targeted designs for now.
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For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the
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following websites:
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- `Technical Resources for DesignStart FPGA`_
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- `Technical Resources for DesignStart FPGA on Xilinx`_
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- `ARM DesignStart FPGA Xilinx FAQs`_
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Supported Features
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==================
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The ``arty_a7_arm_designstart_m1`` board configuration supports the following
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hardware features of the Cortex-M1 reference design:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio, non-interrupt |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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| QSPI | on-chip | QSPI flash |
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+-----------+------------+-------------------------------------+
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The default configuration for the Cortex-M1 can be found in the defconfig file:
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:file:`boards/arm/arty/arty_a7_arm_designstart_m1_defconfig`.
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In addition to the above, the ``arty_a7_arm_designstart_m3`` board configuration
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supports the following hardware features of the Cortex-M3 reference design:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| MPU | on-chip | Memory Protection Unit |
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+-----------+------------+-------------------------------------+
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The default configuration for the Cortex-M3 can be found in the defconfig file:
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:file:`boards/arm/arty/arty_a7_arm_designstart_m3_defconfig`.
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Other hardware features are not currently supported by the port.
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System Clock
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============
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The Cortex-M1 reference design is configured to use the 100 MHz external
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oscillator on the board as CPU system clock whereas the Cortex-M3 reference
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design is configured for 50MHz CPU system clock.
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Serial Port
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===========
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The reference design contains one Xilinx UART Lite. This UART is configured as
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console and is accessible through the on-board JTAG adapter via USB connector
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``J10``.
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Connecting the Debug Probes
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===========================
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Two different debug probes are needed in order to program the board; the
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on-board Digilent JTAG connected to the FPGA, and an external Serial Wire Debug
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(SWD) capable debug probe connected to the ARM Cortex-M1 CPU.
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The on-board JTAG is used for configuring and debugging the Xilinx FPGA
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itself. It is available on USB connector ``J10``.
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The external SWD debug probe can be connected to connector ``J4`` (``nSRST`` on
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``IO39``, ``SWDIO`` on ``IO40``, and ``SWCLK`` on ``IO41``). Another option is
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to use the dedicated :ref:`v2c_daplink_shield`.
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Programming and Debugging
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*************************
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First, configure the FPGA with the selected reference design FPGA bitstream
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using Xilinx Vivado as described in the ARM Cortex-M1/Cortex-M3 DesignStart FPGA
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Xilinx edition user guide (available as part of the reference design download
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from `Technical Resources for DesignStart FPGA on Xilinx`_).
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Another option for configuring the FPGA with the reference design bitstream is
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to use the :ref:`openocd-debug-host-tools`:
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.. code-block:: console
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openocd -f board/arty_s7.cfg -c "init;\
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pld load 0 m1_for_arty_a7_reference.bit;\
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shutdown"
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or:
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.. code-block:: console
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openocd -f board/arty_s7.cfg -c "init;\
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pld load 0 m3_for_arty_a7_reference.bit;\
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shutdown"
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.. note::
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The pre-built FPGA bitstream only works for Arty boards equipped with an
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Artix-35T FPGA. For other Arty variants (e.g. the Arty A7-100) the bitstream
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must be rebuilt.
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Next, build and flash applications as usual (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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Configuring a Console
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=====================
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The UART console is available via the on-board JTAG on USB connector
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``J10``. The on-board JTAG will enumerate as two USB serial ports. The UART is
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typically available on the second serial port.
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Use the following settings with your serial terminal of choice (minicom, putty,
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etc.):
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- Speed: 115200
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- Data: 8 bits
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- Parity: None
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- Stop bits: 1
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Flashing
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========
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Here is an example for building and flashing the :ref:`hello_world` application
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for the Cortex-M1 reference design:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: arty_a7_arm_designstart_m1
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:goals: flash
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After flashing, you should see message similar to the following in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build zephyr-v2.3.99 ***
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Hello World! arty_a7_arm_designstart_m1
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The same procedure can be used for the Cortex-M3 reference design.
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Note, however, that the application was not persisted in flash memory by the
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above steps. It was merely written to internal block RAM in the FPGA. It will
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revert to the application stored in the block RAM within the FPGA bitstream
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the next time the FPGA is configured.
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The steps to persist the application within the FPGA bitstream are covered by
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the ARM Cortex-M1/M3 DesignStart FPGA Xilinx edition user guide. If the
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:kconfig:option:`CONFIG_BUILD_OUTPUT_BIN` is enabled and the `SiFive elf2hex`_ package
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is available, the build system will automatically generate a Verilog memory hex
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dump :file:`zephyr.mem` file suitable for initialising the block RAM using
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`Xilinx Vivado`_.
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Debugging
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=========
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Here is an example for the :ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: arty_a7_arm_designstart_m1
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:goals: debug
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Step through the application in your debugger, and you should see a message
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similar to the following in the terminal:
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.. code-block:: console
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*** Booting Zephyr OS build zephyr-v2.3.99 ***
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Hello World! arty_a7_arm_designstart_m1
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.. _Digilent Arty:
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https://store.digilentinc.com/arty
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.. _ARM DesignStart FPGA:
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https://www.arm.com/resources/designstart/designstart-fpga
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.. _Technical Resources for DesignStart FPGA:
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https://developer.arm.com/ip-products/designstart/fpga
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.. _Technical Resources for DesignStart FPGA on Xilinx:
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https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx
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.. _ARM DesignStart FPGA Xilinx FAQs:
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https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx-faqs
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.. _SiFive elf2hex:
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https://github.com/sifive/elf2hex
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.. _Xilinx Vivado:
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https://www.xilinx.com/products/design-tools/vivado.html
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