97 lines
2.1 KiB
C
97 lines
2.1 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Exception/interrupt context helpers for Cortex-M CPUs
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*
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* Exception/interrupt context helpers.
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*/
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#ifndef _ARM_CORTEXM_ISR__H_
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#define _ARM_CORTEXM_ISR__H_
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#include <arch/cpu.h>
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#include <asm_inline.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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/* nothing */
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#else
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/**
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*
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* @brief Find out if running in an ISR context
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*
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* The current executing vector is found in the IPSR register. We consider the
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* IRQs (exception 16 and up), and the SVC, PendSV, and SYSTICK exceptions,
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* to be interrupts. Taking a fault within an exception is also considered in
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* interrupt context.
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*
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* @return 1 if in ISR, 0 if not.
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*/
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static ALWAYS_INLINE int _IsInIsr(void)
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{
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uint32_t vector = _IpsrGet();
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/*
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* IRQs + PendSV (14) + SVC (11) + SYSTICK (15) are interrupts.
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* Vectors 12 and 13 are reserved, we'll never be in there
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* On ARMv6-M there is no nested execution bit, so we check exception 3,
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* hard fault, to a detect a nested exception.
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*/
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#if defined(CONFIG_ARMV6_M)
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return (vector > 10) || (vector == 3);
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#elif defined(CONFIG_ARMV7_M)
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return (vector > 10) || (vector && _ScbIsNestedExc());
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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}
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/**
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* @brief Setup system exceptions
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*
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* Set exception priorities to conform with the BASEPRI locking mechanism.
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* Set PendSV priority to lowest possible.
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*
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* Enable fault exceptions.
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void _ExcSetup(void)
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{
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_ScbExcPrioSet(_EXC_PENDSV, _EXC_PRIO(0xff));
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#ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
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_ScbExcPrioSet(_EXC_SVC, _EXC_PRIO(_EXC_SVC_PRIO));
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#endif
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#ifdef CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
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_ScbExcPrioSet(_EXC_MPU_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
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_ScbExcPrioSet(_EXC_BUS_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
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_ScbExcPrioSet(_EXC_USAGE_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
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_ScbUsageFaultEnable();
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_ScbBusFaultEnable();
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_ScbMemFaultEnable();
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#endif
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}
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ARM_CORTEXM_ISR__H_ */
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