201 lines
4.0 KiB
ArmAsm
201 lines
4.0 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM CORTEX-M3 power management
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*
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*/
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#define _ASMLANGUAGE
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#include <offsets_short.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <arch/cpu.h>
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#ifdef CONFIG_TICKLESS_IDLE
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#include <kernel_structs.h>
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#endif
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_ASM_FILE_PROLOGUE
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GTEXT(_CpuIdleInit)
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#ifdef CONFIG_SYS_POWER_MANAGEMENT
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GTEXT(_NanoIdleValGet)
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GTEXT(_NanoIdleValClear)
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#endif
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GTEXT(k_cpu_idle)
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GTEXT(k_cpu_atomic_idle)
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#define _SCR_INIT_BITS _SCB_SCR_SEVONPEND
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/**
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*
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* @brief Initialization of CPU idle
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*
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* Only called by nanoArchInit(). Sets SEVONPEND bit once for the system's
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* duration.
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*
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* @return N/A
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*
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* C function prototype:
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*
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* void _CpuIdleInit (void);
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*/
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SECTION_FUNC(TEXT, _CpuIdleInit)
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ldr r1, =_SCB_SCR
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movs.n r2, #_SCR_INIT_BITS
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str r2, [r1]
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bx lr
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#ifdef CONFIG_SYS_POWER_MANAGEMENT
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/**
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*
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* @brief Get the kernel idle setting
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*
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* Returns the kernel idle setting, in ticks. Only called by __systick().
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*
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* @return the requested number of ticks for the kernel to be idle
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*
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* C function prototype:
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*
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* int32_t _NanoIdleValGet (void);
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*/
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SECTION_FUNC(TEXT, _NanoIdleValGet)
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ldr r0, =_kernel
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ldr r0, [r0, #_kernel_offset_to_idle]
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bx lr
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/**
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*
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* @brief Clear the kernel idle setting
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*
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* Sets the kernel idle setting to 0. Only called by __systick().
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*
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* @return N/A
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*
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* C function prototype:
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*
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* void _NanoIdleValClear (void);
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*/
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SECTION_FUNC(TEXT, _NanoIdleValClear)
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ldr r0, =_kernel
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eors.n r1, r1
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str r1, [r0, #_kernel_offset_to_idle]
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bx lr
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#endif /* CONFIG_SYS_POWER_MANAGEMENT */
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/**
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*
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* @brief Power save idle routine for ARM Cortex-M
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*
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* This function will be called by the ernel idle loop or possibly within
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* an implementation of _sys_power_save_idle in the kernel when the
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* '_sys_power_save_flag' variable is non-zero. The ARM 'wfi' instruction
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* will be issued, causing a low-power consumption sleep mode.
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*
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* @return N/A
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*
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* C function prototype:
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*
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* void k_cpu_idle (void);
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*/
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SECTION_FUNC(TEXT, k_cpu_idle)
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
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push {lr}
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bl _sys_k_event_logger_enter_sleep
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pop {r0}
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mov lr, r0
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#endif
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#if defined(CONFIG_ARMV6_M)
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cpsie i
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#elif defined(CONFIG_ARMV7_M)
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/* clear BASEPRI so wfi is awakened by incoming interrupts */
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eors.n r0, r0
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msr BASEPRI, r0
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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wfi
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bx lr
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/**
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*
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* @brief Atomically re-enable interrupts and enter low power mode
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*
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* INTERNAL
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* The requirements for k_cpu_atomic_idle() are as follows:
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* 1) The enablement of interrupts and entering a low-power mode needs to be
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* atomic, i.e. there should be no period of time where interrupts are
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* enabled before the processor enters a low-power mode. See the comments
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* in k_lifo_get(), for example, of the race condition that occurs
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* if this requirement is not met.
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*
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* 2) After waking up from the low-power mode, the interrupt lockout state
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* must be restored as indicated in the 'imask' input parameter.
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*
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* @return N/A
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*
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* C function prototype:
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*
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* void k_cpu_atomic_idle (unsigned int imask);
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*/
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SECTION_FUNC(TEXT, k_cpu_atomic_idle)
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
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push {lr}
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bl _sys_k_event_logger_enter_sleep
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pop {r1}
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mov lr, r1
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#endif
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/*
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* Lock PRIMASK while sleeping: wfe will still get interrupted by
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* incoming interrupts but the CPU will not service them right away.
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*/
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cpsid i
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/*
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* No need to set SEVONPEND, it's set once in _CpuIdleInit() and never
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* touched again.
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*/
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/* r0: interrupt mask from caller */
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#if defined(CONFIG_ARMV6_M)
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/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
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wfe
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cmp r0, #0
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bne _irq_disabled
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cpsie i
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_irq_disabled:
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#elif defined(CONFIG_ARMV7_M)
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/* r1: zero, for setting BASEPRI (needs a register) */
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eors.n r1, r1
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/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
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msr BASEPRI, r1
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wfe
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msr BASEPRI, r0
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cpsie i
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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bx lr
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