273 lines
7.6 KiB
Plaintext
273 lines
7.6 KiB
Plaintext
# Kconfig - ARM Cortex-M platform configuration options
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#
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config ISA_THUMB2
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bool
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# Omit prompt to signify "hidden" option
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default n
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help
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From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
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Thumb-2 technology is the instruction set underlying the ARM Cortex
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architecture which provides enhanced levels of performance, energy
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efficiency, and code density for a wide range of embedded
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applications.
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Thumb-2 technology builds on the success of Thumb, the innovative
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high code density instruction set for ARM microprocessor cores, to
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increase the power of the ARM microprocessor core available to
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developers of low cost, high performance systems.
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The technology is backwards compatible with existing ARM and Thumb
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solutions, while significantly extending the features available to
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the Thumb instructions set. This allows more of the application to
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benefit from the best in class code density of Thumb.
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For performance optimised code Thumb-2 technology uses 31 percent
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less memory to reduce system cost, while providing up to 38 percent
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higher performance than existing high density code, which can be used
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to prolong battery-life or to enrich the product feature set. Thumb-2
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technology is featured in the processor, and in all ARMv7
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architecture-based processors.
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config CPU_CORTEX_M_HAS_BASEPRI
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bool
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# Omit prompt to signify "hidden" option
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default n
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help
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This option signifies the CPU has the BASEPRI register.
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config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
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bool
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# Omit prompt to signify "hidden" option
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default n
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help
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This option signifies the CPU faults other than the hard fault, and
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needs to reserve a priority for them.
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config ARMV6_M
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bool
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# Omit prompt to signify "hidden" option
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default n
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select ATOMIC_OPERATIONS_C
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select ISA_THUMB2
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help
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This option signifies the use of an ARMv6-M processor implementation.
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config ARMV7_M
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bool
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# Omit prompt to signify "hidden" option
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default n
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select ATOMIC_OPERATIONS_BUILTIN
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select ISA_THUMB2
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select CPU_CORTEX_M_HAS_BASEPRI
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select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
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help
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This option signifies the use of an ARMv7-M processor implementation.
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config CPU_CORTEX_M0
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bool
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# Omit prompt to signify "hidden" option
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select ARMV6_M
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help
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This option signifies the use of a Cortex-M0 CPU
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config CPU_CORTEX_M0PLUS
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bool
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# Omit prompt to signify "hidden" option
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select ARMV6_M
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help
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This option signifies the use of a Cortex-M0+ CPU
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config CPU_CORTEX_M3
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bool
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# Omit prompt to signify "hidden" option
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select ARMV7_M
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help
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This option signifies the use of a Cortex-M3 CPU
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config CPU_CORTEX_M4
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bool
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# Omit prompt to signify "hidden" option
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select ARMV7_M
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help
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This option signifies the use of a Cortex-M4 CPU
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config CPU_CORTEX_M7
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bool
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# Omit prompt to signify "hidden" option
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select ARMV7_M
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default n
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help
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This option signifies the use of a Cortex-M7 CPU
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menu "ARM Cortex-M options"
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depends on CPU_CORTEX_M
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config LDREX_STREX_AVAILABLE
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bool
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default y
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config DATA_ENDIANNESS_LITTLE
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bool
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default y
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help
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This is driven by the processor implementation, since it is fixed in
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hardware. The board should set this value to 'n' if the data is
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implemented as big endian.
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config STACK_ALIGN_DOUBLE_WORD
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bool
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prompt "Align stacks on double-words (8 octets)"
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default y
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help
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This is needed to conform to AAPCS, the procedure call standard for
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the ARM. It wastes stack space.
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config NUM_IRQ_PRIO_BITS
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int
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#hidden option, implemented by board
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help
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Cortex-M chips can implement up to 8 bits of interrupt priorities,
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for a maximum of 256 priorities. Most chips implement fewer than 8.
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The board must define the correct value.
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config RUNTIME_NMI
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bool
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prompt "Attach an NMI handler at runtime"
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select REBOOT
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default n
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help
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The kernel provides a simple NMI handler that simply hangs in a tight
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loop if triggered. This fills the requirement that there must be an
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NMI handler installed when the CPU boots. If a custom handler is
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needed, enable this option and attach it via _NmiHandlerSet().
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config FAULT_DUMP
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int
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prompt "Fault dump level"
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default 2
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range 0 2
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help
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Different levels for display information when a fault occurs.
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2: The default. Display specific and verbose information. Consumes
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the most memory (long strings).
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1: Display general and short information. Consumes less memory
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(short strings).
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0: Off.
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config XIP
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default y
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config SRAM_SIZE
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int "SRAM Size in kB"
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help
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This option specifies the size of the SRAM in kB. It is normally set by
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the board's defconfig file and the user should generally avoid modifying
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it via the menu configuration.
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config SRAM_BASE_ADDRESS
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hex "SRAM Base Address"
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help
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This option specifies the base address of the SRAM on the board. It is
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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config FLASH_SIZE
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int "Flash Size in kB"
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help
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This option specifies the size of the flash in kB. It is normally set by
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the board's defconfig file and the user should generally avoid modifying
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it via the menu configuration.
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config FLASH_BASE_ADDRESS
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hex "Flash Base Address"
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help
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This option specifies the base address of the flash on the board. It is
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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endmenu
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menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
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depends on ARMV6_M || ARMV7_M
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config IRQ_OFFLOAD
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bool "Enable IRQ offload"
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default n
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help
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Enable irq_offload() API which allows functions to be synchronously
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run in interrupt context. Adds some overhead to context switching.
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Mainly useful for test cases.
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config SW_ISR_TABLE
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bool
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prompt "Enable software interrupt handler table"
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default y
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help
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Enable an interrupt handler table implemented in software. This
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table, unlike ISRs connected directly in the vector table, allow
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a parameter to be passed to the interrupt handlers. Also, invoking
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the exeception/interrupt exit stub is automatically done.
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config IRQ_VECTOR_TABLE_CUSTOM
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bool
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prompt "Projects provide a custom static IRQ part of vector table"
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depends on !SW_ISR_TABLE
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default n
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help
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Projects, not the board, provide the IRQ part of the vector table.
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This is the table of interrupt handlers with the best potential
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performance, but is the less flexible.
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The ISRs are installed directly in the vector table, thus are
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directly called by the CPU when an interrupt is taken. This adds
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the least overhead when handling an interrupt.
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Downsides:
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- ISRs cannot have a parameter
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- ISRs cannot be connected at runtime
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- ISRs must notify the kernel manually by invoking _IntExit() when
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then are about to return.
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config IRQ_VECTOR_TABLE_SOC
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bool
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# omit prompt to signify a "hidden" option
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depends on SW_ISR_TABLE || !IRQ_VECTOR_TABLE_CUSTOM
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default y
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help
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Not user-selectable, helps build system logic.
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config ZERO_LATENCY_IRQS
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bool
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prompt "Enable zero-latency interrupts"
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default n
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depends on CPU_CORTEX_M_HAS_BASEPRI
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help
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Interrupt locking is done by setting exception masking to priority
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one, thus allowing exception of priority zero to still come in. By
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default, the kernel verifies, via __ASSERT() statements, that the
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interrupt priority is not set to zero when either connecting them or
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setting their priority. Enabling this option disables the check,
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thus allowing setting the priority of interrupts to zero.
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Note that this is a somewhat dangerous option: ISRs of priority zero
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interrupts cannot use any kernel functionality.
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config ARCH_HAS_THREAD_ABORT
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bool
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# omit prompt to signify a "hidden" option
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default y
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endmenu
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