72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_POWER_H_
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#define _SOC_POWER_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum power_states {
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SYS_POWER_STATE_CPU_LPS, /* SS2 with LPSS enabled state */
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SYS_POWER_STATE_CPU_LPS_1, /* SS2 state */
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SYS_POWER_STATE_CPU_LPS_2, /* SS1 state with Timer ON */
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SYS_POWER_STATE_DEEP_SLEEP, /* DEEP SLEEP state */
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SYS_POWER_STATE_DEEP_SLEEP_1, /* SLEEP state */
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SYS_POWER_STATE_MAX
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};
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/**
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* @brief Put processor into low power state
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*
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* This function implements the SoC specific details necessary
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* to put the processor into available power states.
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*
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* Wake up considerations:
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* -----------------------
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*
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* SYS_POWER_STATE_CPU_LPS_2: Any interrupt works as wake event.
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*
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* SYS_POWER_STATE_CPU_LPS_1: Any interrupt works as wake event except
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* the ARC TIMER which is disabled.
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*
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* SYS_POWER_STATE_CPU_LPS: SYS_POWER_STATE_DEEP_SLEEP wake events applies.
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*
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* SYS_POWER_STATE_DEEP_SLEEP: Only Always-On peripherals can wake up
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* the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
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*
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* SYS_POWER_STATE_DEEP_SLEEP_1: Only Always-On peripherals can wake up
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* the SoC. This consists of the Counter, RTC, GPIO 1 and AIO Comparator.
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*
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* Considerations around SYS_POWER_STATE_CPU_LPS (LPSS state):
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* -----------------------------------------------------------
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*
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* LPSS is a common power state between the x86 and ARC.
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* When the two applications enter SYS_POWER_STATE_CPU_LPS,
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* the SoC will enter this lower consumption mode.
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* After wake up, this state can only be entered again
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* if the ARC wakes up and transitions again to
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* SYS_POWER_STATE_CPU_LPS. This is not required on the x86 side.
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*/
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void _sys_soc_set_power_state(enum power_states state);
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/**
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* @brief Do any SoC or architecture specific post ops after low power states.
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*
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* This function is a place holder to do any operations that may
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* be needed to be done after deep sleep exits. Currently it enables
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* interrupts after resuming from deep sleep. In future, the enabling
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* of interrupts may be moved into the kernel.
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*/
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void _sys_soc_power_state_post_ops(enum power_states state);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SOC_POWER_H_ */
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