104 lines
2.3 KiB
C
104 lines
2.3 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr.h>
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#include <sys_io.h>
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#include <misc/__assert.h>
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#include <power.h>
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#include <soc_power.h>
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#include <init.h>
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#include <kernel_structs.h>
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#include "power_states.h"
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#include "ss_power_states.h"
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#include "vreg.h"
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#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
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extern void _power_soc_sleep(void);
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extern void _power_soc_deep_sleep(void);
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static void _deep_sleep(enum power_states state)
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{
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power_soc_set_ss_restore_flag();
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switch (state) {
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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_power_soc_sleep();
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break;
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case SYS_POWER_STATE_DEEP_SLEEP:
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_power_soc_deep_sleep();
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break;
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default:
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break;
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}
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}
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#endif
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#define SLEEP_MODE_CORE_OFF (0x0)
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#define SLEEP_MODE_CORE_TIMERS_RTC_OFF (0x60)
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#define ENABLE_INTERRUPTS (BIT(4) | _ARC_V2_STATUS32_E(_ARC_V2_DEF_IRQ_LEVEL))
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#define ARC_SS1 (SLEEP_MODE_CORE_OFF | ENABLE_INTERRUPTS)
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#define ARC_SS2 (SLEEP_MODE_CORE_TIMERS_RTC_OFF | ENABLE_INTERRUPTS)
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/* QMSI does not set the interrupt enable bit in the sleep operand.
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* For the time being, implement this in Zephyr.
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* This will be removed once QMSI is fixed.
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*/
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static void enter_arc_state(int mode)
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{
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/* Enter SSx */
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__asm__ volatile("sleep %0"
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: /* No output operands. */
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: /* Input operands. */
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"r"(mode) : "memory", "cc");
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}
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void _sys_soc_set_power_state(enum power_states state)
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{
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switch (state) {
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case SYS_POWER_STATE_CPU_LPS:
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ss_power_soc_lpss_enable();
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enter_arc_state(ARC_SS2);
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break;
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case SYS_POWER_STATE_CPU_LPS_1:
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enter_arc_state(ARC_SS2);
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break;
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case SYS_POWER_STATE_CPU_LPS_2:
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enter_arc_state(ARC_SS1);
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break;
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#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
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case SYS_POWER_STATE_DEEP_SLEEP:
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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_deep_sleep(state);
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break;
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#endif
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default:
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break;
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}
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}
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void _sys_soc_power_state_post_ops(enum power_states state)
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{
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uint32_t limit;
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switch (state) {
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case SYS_POWER_STATE_CPU_LPS:
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ss_power_soc_lpss_disable();
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case SYS_POWER_STATE_CPU_LPS_1:
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/* Expire the timer as it is disabled in SS2. */
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limit = _arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
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_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, limit - 1);
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break;
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case SYS_POWER_STATE_DEEP_SLEEP:
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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__builtin_arc_seti(0);
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break;
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default:
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break;
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}
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}
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