350 lines
10 KiB
ArmAsm
350 lines
10 KiB
ArmAsm
/*
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Wrapper around ISRs with logic for context switching
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*
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*
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* Wrapper installed in vector table for handling dynamic interrupts that accept
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* a parameter.
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*/
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#define _ASMLANGUAGE
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#include <offsets_short.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <sw_isr_table.h>
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#include <kernel_structs.h>
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#include <arch/cpu.h>
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GTEXT(_isr_enter)
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GTEXT(_isr_demux)
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#if CONFIG_RGF_NUM_BANKS == 1
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GDATA(saved_r0)
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.balign 4
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SECTION_VAR(BSS, saved_r0)
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.word 0
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#endif
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#if defined(CONFIG_SYS_POWER_MANAGEMENT)
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GTEXT(_sys_power_save_idle_exit)
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#endif
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/*
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The symbols in this file are not real functions, and neither are
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_rirq_enter/_firq_enter: they are jump points.
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The flow is the following:
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ISR -> _isr_enter -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
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+ -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
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Context switch explanation:
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The context switch code is spread in these files:
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isr_wrapper.s, swap.s, swap_macros.s, fast_irq.s, regular_irq.s
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IRQ stack frame layout:
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high address
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status32
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pc
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lp_count
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lp_start
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lp_end
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blink
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r13
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...
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sp -> r0
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low address
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Registers not taken into account in the current implementation.
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jli_base
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ldi_base
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ei_base
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accl
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acch
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The context switch code adopts this standard so that it is easier to follow:
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- r1 contains _kernel ASAP and is not overwritten over the lifespan of
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the functions.
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- r2 contains _kernel.current ASAP, and the incoming thread when we
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transition from outgoing thread to incoming thread
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Not loading _kernel into r0 allows loading _kernel without stomping on
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the parameter in r0 in _Swap().
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ARCv2 processors have two kinds of interrupts: fast (FIRQ) and regular. The
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official documentation calls the regular interrupts 'IRQs', but the internals
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of the kernel call them 'RIRQs' to differentiate from the 'irq' subsystem,
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which is the interrupt API/layer of abstraction.
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For FIRQ, there are two cases, depending upon the value of
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CONFIG_RGF_NUM_BANKS.
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CONFIG_RGF_NUM_BANKS==1 case:
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Scratch registers are pushed onto the current stack just as they are with
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RIRQ. See the above frame layout. Unlike RIRQ, the status32_p0 and ilink
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registers are where status32 and the program counter are located, so these
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need to be pushed.
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CONFIG_RGF_NUM_BANKS!=1 case:
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The FIRQ handler has its own register bank for general purpose registers,
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and thus it doesn't have to save them on a stack. The 'loop' registers
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(lp_count, lp_end, lp_start), however, are not present in the
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second bank. The handler saves these special registers in unused callee saved
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registers (to avoid stack accesses). It is possible to register a FIRQ
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handler that operates outside of the kernel, but care must be taken to only
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use instructions that only use the banked registers.
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The kernel is able to handle transitions to and from FIRQ, RIRQ and threads
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(fibers/task). The contexts are saved 'lazily': the minimum amount of work is
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done upfront, and the rest is done when needed:
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o RIRQ
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All needed regisers to run C code in the ISR are saved automatically
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on the outgoing thread's stack: loop, status32, pc, and the caller-
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saved GPRs. That stack frame layout is pre-determined. If returning
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to a fiber, the stack is popped and no registers have to be saved by
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the kernel. If a context switch is required, the callee-saved GPRs
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are then saved in the thread control structure (TCS).
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o FIRQ
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First, a FIRQ can be interrupting a lower-priority RIRQ: if this is the case,
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the FIRQ does not take a scheduling decision and leaves it the RIRQ to
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handle. This limits the amount of code that has to run at interrupt-level.
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CONFIG_RGF_NUM_BANKS==1 case:
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Registers are saved on the stack frame just as they are for RIRQ.
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Context switch can happen just as it does in the RIRQ case, however,
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if the FIRQ interrupted a RIRQ, the FIRQ will return from interrupt and
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let the RIRQ do the context switch. At entry, one register is needed in order
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to have code to save other registers. r0 is saved first in a global called
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saved_r0.
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CONFIG_RGF_NUM_BANKS!=1 case:
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During early initialization, the sp in the 2nd register bank is made to
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refer to _firq_stack. This allows for the FIRQ handler to use its own stack.
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GPRs are banked, loop registers are saved in unused callee saved regs upon
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interrupt entry. If returning to a fiber, loop registers are restored and the
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CPU switches back to bank 0 for the GPRs. If a context switch is
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needed, at this point only are all the registers saved. First, a
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stack frame with the same layout as the automatic RIRQ one is created
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and then the callee-saved GPRs are saved in the TCS. status32_p0 and
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ilink are saved in this case, not status32 and pc.
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To create the stack frame, the FIRQ handling code must first go back to using
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bank0 of registers, since that is where the registers containing the exiting
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thread are saved. Care must be taken not to touch any register before saving
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them: the only one usable at that point is the stack pointer.
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o coop
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When a coop context switch is done, the callee-saved registers are
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saved in the TCS. The other GPRs do not need to be saved, since the
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compiler has already placed them on the stack.
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For restoring the contexts, there are six cases. In all cases, the
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callee-saved registers of the incoming thread have to be restored. Then, there
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are specifics for each case:
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From coop:
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o to coop
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Restore interrupt lock level and do a normal function call return.
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o to any irq
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The incoming interrupted thread has an IRQ stack frame containing the
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caller-saved registers that has to be popped. status32 has to be restored,
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then we jump to the interrupted instruction.
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From FIRQ:
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When CONFIG_RGF_NUM_BANKS==1, context switch is done as it is for RIRQ.
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When CONFIG_RGF_NUM_BANKS!=1, the processor is put back to using bank0,
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not bank1 anymore, because it had to save the outgoing context from bank0,
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and now has to load the incoming one
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into bank0.
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o to coop
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The address of the returning instruction from _Swap() is loaded in ilink and
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the saved status32 in status32_p0, taking care to adjust the interrupt lock
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state desired in status32_p0. The return value is put in r0.
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o to any irq
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The IRQ has saved the caller-saved registers in a stack frame, which must be
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popped, and statu32 and pc loaded in status32_p0 and ilink.
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From RIRQ:
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o to coop
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The interrupt return mechanism in the processor expects a stack frame, but
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the outgoing context did not create one. A fake one is created here, with
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only the relevant values filled in: pc, status32 and the return value in r0.
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There is a discrepancy between the ABI from the ARCv2 docs, including the
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way the processor pushes GPRs in pairs in the IRQ stack frame, and the ABI
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GCC uses. r13 should be a callee-saved register, but GCC treats it as
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caller-saved. This means that the processor pushes it in the stack frame
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along with r12, but the compiler does not save it before entering a
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function. So, it is saved as part of the callee-saved registers, and
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restored there, but the processor restores it _a second time_ when popping
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the IRQ stack frame. Thus, the correct value must also be put in the fake
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stack frame when returning to a thread that context switched out
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cooperatively.
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o to any irq
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Both types of IRQs already have an IRQ stack frame: simply return from
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interrupt.
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*/
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SECTION_FUNC(TEXT, _isr_enter)
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#if CONFIG_RGF_NUM_BANKS == 1
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st r0,[saved_r0]
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#endif
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lr r0, [_ARC_V2_AUX_IRQ_ACT]
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ffs r0, r0
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cmp r0, 0
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#if CONFIG_RGF_NUM_BANKS == 1
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bnz rirq_path
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/* 1-register bank FIRQ handling must save registers on stack */
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lr r0,[_ARC_V2_STATUS32_P0]
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push_s r0
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mov r0,ilink
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push_s r0
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mov r0,lp_count
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push_s r0
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lr r0, [_ARC_V2_LP_START]
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push_s r0
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lr r0, [_ARC_V2_LP_END]
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push_s r0
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push_s blink
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push_s r13
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push_s r12
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push r11
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push r10
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push r9
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push r8
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push r7
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push r6
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push r5
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push r4
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push_s r3
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push_s r2
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push_s r1
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ld r0,[saved_r0]
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push_s r0
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mov r3, _firq_exit
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mov r2, _firq_enter
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j_s [r2]
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rirq_path:
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mov r3, _rirq_exit
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mov r2, _rirq_enter
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j_s [r2]
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#else
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mov.z r3, _firq_exit
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mov.z r2, _firq_enter
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mov.nz r3, _rirq_exit
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mov.nz r2, _rirq_enter
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j_s [r2]
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#endif
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
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GTEXT(_sys_k_event_logger_exit_sleep)
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.macro log_sleep_k_event
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clri r0 /* do not interrupt event logger operations */
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push_s r0
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push_s blink
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jl _sys_k_event_logger_exit_sleep
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pop_s blink
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pop_s r0
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seti r0
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.endm
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#else
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#define log_sleep_k_event
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#endif
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#if defined(CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT)
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GTEXT(_sys_k_event_logger_interrupt)
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.macro log_interrupt_k_event
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clri r0 /* do not interrupt event logger operations */
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push_s r0
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push_s blink
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jl _sys_k_event_logger_interrupt
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pop_s blink
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pop_s r0
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seti r0
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.endm
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#else
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#define log_interrupt_k_event
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#endif
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#if defined(CONFIG_SYS_POWER_MANAGEMENT)
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.macro exit_tickless_idle
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clri r0 /* do not interrupt exiting tickless idle operations */
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push_s r1
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push_s r0
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mov_s r1, _kernel
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ld_s r0, [r1, _kernel_offset_to_idle] /* requested idle duration */
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breq r0, 0, _skip_sys_power_save_idle_exit
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st 0, [r1, _kernel_offset_to_idle] /* zero idle duration */
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push_s blink
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jl _sys_power_save_idle_exit
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pop_s blink
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_skip_sys_power_save_idle_exit:
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pop_s r0
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pop_s r1
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seti r0
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.endm
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#else
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#define exit_tickless_idle
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#endif
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/* when getting here, r3 contains the interrupt exit stub to call */
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SECTION_FUNC(TEXT, _isr_demux)
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push_s r3
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/* cannot be done before this point because we must be able to run C */
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/* r0 is available to be stomped here, and exit_tickless_idle uses it */
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exit_tickless_idle
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log_interrupt_k_event
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log_sleep_k_event
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lr r0, [_ARC_V2_ICAUSE]
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sub r0, r0, 16
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mov r1, _sw_isr_table
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add3 r0, r1, r0 /* table entries are 8-bytes wide */
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ld_s r1, [r0, 4] /* ISR into r1 */
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jl_s.d [r1]
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ld_s r0, [r0] /* delay slot: ISR parameter into r0 */
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/* back from ISR, jump to exit stub */
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pop_s r3
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j_s [r3]
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nop
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