373 lines
8.2 KiB
ArmAsm
373 lines
8.2 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Handling of transitions to-and-from fast IRQs (FIRQ)
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*
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* This module implements the code for handling entry to and exit from Fast IRQs.
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*
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* See isr_wrapper.S for details.
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*/
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#define _ASMLANGUAGE
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#include <kernel_structs.h>
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#include <offsets_short.h>
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#include <toolchain.h>
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#include <arch/cpu.h>
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#include <swap_macros.h>
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GTEXT(_firq_enter)
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GTEXT(_firq_exit)
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GTEXT(_firq_stack_setup)
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GTEXT(_firq_stack_suspend)
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GTEXT(_firq_stack_resume)
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#if CONFIG_RGF_NUM_BANKS != 1
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GDATA(_firq_stack)
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GDATA(_saved_firq_stack)
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SECTION_VAR(NOINIT, _firq_stack)
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.space CONFIG_FIRQ_STACK_SIZE
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#else
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GDATA(saved_r0)
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#endif
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.macro _firq_return
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#if CONFIG_RGF_NUM_BANKS == 1
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b _firq_no_reschedule
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#else
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rtie
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#endif
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.endm
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/**
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*
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* @brief Work to be done before handing control to a FIRQ ISR
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*
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* The processor switches to a second register bank so registers from the
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* current bank do not have to be preserved yet. The only issue is the LP_START/
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* LP_COUNT/LP_END registers, which are not banked. These can be saved
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* in available callee saved registers.
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*
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* If all FIRQ ISRs are programmed such that there are no use of the LP
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* registers (ie. no LPcc instruction), and CONFIG_ARC_STACK_CHECKING is
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* not set, then the kernel can be configured to not save and restore them.
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*
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* When entering a FIRQ, interrupts might as well be locked: the processor is
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* running at its highest priority, and cannot be interrupted by any other
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* interrupt. An exception, however, can be taken.
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*
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* Assumption by _isr_demux: r3 is untouched by _firq_enter.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _firq_enter)
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/*
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* ATTENTION:
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* If CONFIG_RGF_NUM_BANKS>1, firq uses a 2nd register bank so GPRs do
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* not need to be saved.
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* If CONFIG_RGF_NUM_BANKS==1, firq must use the stack to save registers.
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* This has already been done by _isr_enter.
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*/
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#ifdef CONFIG_ARC_STACK_CHECKING
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/* disable stack checking */
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lr r2, [_ARC_V2_STATUS32]
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bclr r2, r2, _ARC_V2_STATUS32_SC_BIT
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kflag r2
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#endif
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#if CONFIG_RGF_NUM_BANKS != 1
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#ifndef CONFIG_FIRQ_NO_LPCC
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/*
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* Save LP_START/LP_COUNT/LP_END because called handler might use.
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* Save these in callee saved registers to avoid using memory.
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* These will be saved by the compiler if it needs to spill them.
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*/
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mov r23,lp_count
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lr r24, [_ARC_V2_LP_START]
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lr r25, [_ARC_V2_LP_END]
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#endif
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#endif
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j @_isr_demux
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/**
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*
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* @brief Work to be done exiting a FIRQ
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _firq_exit)
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#if CONFIG_RGF_NUM_BANKS != 1
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#ifndef CONFIG_FIRQ_NO_LPCC
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/* restore lp_count, lp_start, lp_end from r23-r25 */
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mov lp_count,r23
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sr r24, [_ARC_V2_LP_START]
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sr r25, [_ARC_V2_LP_END]
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#endif
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#endif
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#ifdef CONFIG_PREEMPT_ENABLED
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mov_s r1, _kernel
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ld_s r2, [r1, _kernel_offset_to_current]
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#if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
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/* check if we're a nested interrupt: if so, let the interrupted
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* interrupt handle the reschedule */
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lr r3, [_ARC_V2_AUX_IRQ_ACT]
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/* the OS on ARCv2 always runs in kernel mode, so assume bit31 [U] in
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* AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is not 1, it
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* means that another bit is set so an interrupt was interrupted.
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*/
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breq r3, 1, _firq_check_for_swap
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_firq_return
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#endif
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.balign 4
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_firq_check_for_swap:
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/*
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* Non-preemptible thread ? Do not schedule (see explanation of
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* preempt field in kernel_struct.h).
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*/
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ldh_s r0, [r2, _thread_offset_to_preempt]
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brhs r0, _NON_PREEMPT_THRESHOLD, _firq_no_reschedule
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/* Check if the current thread (in r2) is the cached thread */
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ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
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brne r0, r2, _firq_reschedule
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/* fall to no rescheduling */
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#endif /* CONFIG_PREEMPT_ENABLED */
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.balign 4
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_firq_no_reschedule:
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/*
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* Keeping this code block close to those that use it allows using brxx
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* instruction instead of a pair of cmp and bxx
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*/
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#if CONFIG_RGF_NUM_BANKS == 1
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add sp,sp,4 /* don't need r0 from stack */
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pop_s r1
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pop_s r2
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pop_s r3
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pop r4
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pop r5
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pop r6
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pop r7
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pop r8
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pop r9
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pop r10
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pop r11
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pop_s r12
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pop_s r13
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pop_s blink
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pop_s r0
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sr r0, [_ARC_V2_LP_END]
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pop_s r0
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sr r0, [_ARC_V2_LP_START]
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pop_s r0
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mov lp_count,r0
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ld r0,[saved_r0]
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add sp,sp,8 /* don't need ilink & status32_po from stack */
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#endif
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rtie
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#ifdef CONFIG_PREEMPT_ENABLED
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.balign 4
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_firq_reschedule:
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#if CONFIG_RGF_NUM_BANKS != 1
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/*
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* We know there is no interrupted interrupt of lower priority at this
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* point, so when switching back to register bank 0, it will contain the
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* registers from the interrupted thread.
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*/
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/* chose register bank #0 */
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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kflag r0
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/* we're back on the outgoing thread's stack */
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_create_irq_stack_frame
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/*
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* In a FIRQ, STATUS32 of the outgoing thread is in STATUS32_P0 and the
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* PC in ILINK: save them in status32/pc respectively.
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*/
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lr r0, [_ARC_V2_STATUS32_P0]
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st_s r0, [sp, ___isf_t_status32_OFFSET]
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st ilink, [sp, ___isf_t_pc_OFFSET] /* ilink into pc */
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#endif
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mov_s r1, _kernel
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ld_s r2, [r1, _kernel_offset_to_current]
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_save_callee_saved_regs
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st _CAUSE_FIRQ, [r2, _thread_offset_to_relinquish_cause]
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ld_s r2, [r1, _kernel_offset_to_ready_q_cache]
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st_s r2, [r1, _kernel_offset_to_current]
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#ifdef CONFIG_ARC_STACK_CHECKING
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/* Use stack top and down registers from restored context */
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add r3, r2, _K_THREAD_NO_FLOAT_SIZEOF
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sr r3, [_ARC_V2_KSTACK_TOP]
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ld_s r3, [r2, _thread_offset_to_stack_top]
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sr r3, [_ARC_V2_KSTACK_BASE]
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#endif
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/*
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* _load_callee_saved_regs expects incoming thread in r2.
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* _load_callee_saved_regs restores the stack pointer.
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*/
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_load_callee_saved_regs
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ld_s r3, [r2, _thread_offset_to_relinquish_cause]
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breq r3, _CAUSE_RIRQ, _firq_return_from_rirq
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nop
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breq r3, _CAUSE_FIRQ, _firq_return_from_firq
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nop
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/* fall through */
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.balign 4
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_firq_return_from_coop:
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ld_s r3, [r2, _thread_offset_to_intlock_key]
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st 0, [r2, _thread_offset_to_intlock_key]
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/* pc into ilink */
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pop_s r0
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mov ilink, r0
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pop_s r0 /* status32 into r0 */
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/*
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* There are only two interrupt lock states: locked and unlocked. When
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* entering _Swap(), they are always locked, so the IE bit is unset in
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* status32. If the incoming thread had them locked recursively, it
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* means that the IE bit should stay unset. The only time the bit
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* has to change is if they were not locked recursively.
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*/
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and.f r3, r3, (1 << 4)
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or.nz r0, r0, _ARC_V2_STATUS32_IE
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sr r0, [_ARC_V2_STATUS32_P0]
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ld_s r0, [r2, _thread_offset_to_return_value]
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rtie
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.balign 4
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_firq_return_from_rirq:
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_firq_return_from_firq:
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_pop_irq_stack_frame
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ld ilink, [sp, -4] /* status32 into ilink */
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sr ilink, [_ARC_V2_STATUS32_P0]
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ld ilink, [sp, -8] /* pc into ilink */
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/* LP registers are already restored, just switch back to bank 0 */
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rtie
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#endif /* CONFIG_PREEMPT_ENABLED */
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/**
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*
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* @brief Install the FIRQ stack in register bank 1 if CONFIG_RGF_NUM_BANK!=1
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _firq_stack_setup)
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#if CONFIG_RGF_NUM_BANKS != 1
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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or r0, r0, _ARC_V2_STATUS32_RB(1)
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kflag r0
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mov sp, _firq_stack
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add sp, sp, CONFIG_FIRQ_STACK_SIZE
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/*
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* We have to reload r0 here, because it is bank1 r0 which contains
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* garbage, not bank0 r0 containing the previous value of status32.
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*/
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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kflag r0
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#endif
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j_s [blink]
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/**
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*
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* @brief Save the FIRQ context if CONFIG_RGF_NUM_BANK!=1
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _firq_stack_suspend)
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#if CONFIG_RGF_NUM_BANKS != 1
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/* Switch to bank 1 */
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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or r0, r0, _ARC_V2_STATUS32_RB(1)
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kflag r0
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st sp, [_saved_firq_stack]
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/* Switch back to bank 0 */
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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kflag r0
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#endif
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j_s [blink]
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/**
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*
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* @brief Restore the FIRQ context if CONFIG_RGF_NUM_BANK!=1
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT, _firq_stack_resume)
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#if CONFIG_RGF_NUM_BANKS != 1
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/* Switch to bank 1 */
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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or r0, r0, _ARC_V2_STATUS32_RB(1)
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kflag r0
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ld sp, [_saved_firq_stack]
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/* Switch back to bank 0 */
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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kflag r0
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#endif
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j_s [blink]
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