175 lines
4.3 KiB
C
175 lines
4.3 KiB
C
/* cache.c - d-cache support for ARC CPUs */
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/*
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* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief d-cache manipulation
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*
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* This module contains functions for manipulation of the d-cache.
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <misc/util.h>
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#include <toolchain.h>
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#include <cache.h>
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#include <linker-defs.h>
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#include <arch/arc/v2/aux_regs.h>
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#include <nano_internal.h>
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#include <misc/__assert.h>
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#include <init.h>
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#if defined(CONFIG_CACHE_FLUSHING)
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#if (CONFIG_CACHE_LINE_SIZE == 0) && !defined(CONFIG_CACHE_LINE_SIZE_DETECT)
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#error Cannot use this implementation with a cache line size of 0
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#endif
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#if defined(CONFIG_CACHE_LINE_SIZE_DETECT)
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#define DCACHE_LINE_SIZE sys_cache_line_size
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#else
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#define DCACHE_LINE_SIZE CONFIG_CACHE_LINE_SIZE
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#endif
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#define DC_CTRL_DC_ENABLE 0x0 /* enable d-cache */
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#define DC_CTRL_DC_DISABLE 0x1 /* disable d-cache */
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#define DC_CTRL_INVALID_ONLY 0x0 /* invalid d-cache only */
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#define DC_CTRL_INVALID_FLUSH 0x40 /* invalid and flush d-cache */
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#define DC_CTRL_ENABLE_FLUSH_LOCKED 0x80 /* locked d-cache can be flushed */
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#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0 /* locked d-cache cannot be flushed */
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#define DC_CTRL_FLUSH_STATUS 0x100/* flush status */
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#define DC_CTRL_DIRECT_ACCESS 0x0 /* direct access mode */
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#define DC_CTRL_INDIRECT_ACCESS 0x20 /* indirect access mode */
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#define DC_CTRL_OP_SUCCEEDED 0x4 /* d-cache operation succeeded */
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static int dcache_available(void)
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{
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unsigned long val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
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val &= 0xff; /* extract version */
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return (val == 0)?0:1;
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}
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static void dcache_dc_ctrl(uint32_t dcache_en_mask)
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{
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if (!dcache_available())
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return;
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_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, dcache_en_mask);
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}
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static void dcache_enable(void)
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{
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dcache_dc_ctrl(DC_CTRL_DC_ENABLE);
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}
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/**
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*
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* @brief Flush multiple d-cache lines to memory
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*
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* No alignment is required for either <start_addr> or <size>, but since
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* dcache_flush_mlines() iterates on the d-cache lines, a cache line
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* alignment for both is optimal.
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*
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* The d-cache line size is specified either via the CONFIG_CACHE_LINE_SIZE
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* kconfig option or it is detected at runtime.
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*
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* @param start_addr the pointer to start the multi-line flush
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* @param size the number of bytes that are to be flushed
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*
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* @return N/A
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*/
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static void dcache_flush_mlines(uint32_t start_addr, uint32_t size)
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{
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uint32_t end_addr;
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unsigned int key;
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if (!dcache_available() || (size == 0)) {
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return;
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}
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end_addr = start_addr + size - 1;
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start_addr &= (uint32_t)(~(DCACHE_LINE_SIZE - 1));
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key = irq_lock(); /* --enter critical section-- */
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do {
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_arc_v2_aux_reg_write(_ARC_V2_DC_FLDL, start_addr);
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__asm__ volatile("nop_s");
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__asm__ volatile("nop_s");
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__asm__ volatile("nop_s");
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/* wait for flush completion */
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do {
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if ((_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) &
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DC_CTRL_FLUSH_STATUS) == 0)
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break;
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} while (1);
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start_addr += DCACHE_LINE_SIZE;
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} while (start_addr <= end_addr);
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irq_unlock(key); /* --exit critical section-- */
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}
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/**
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*
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* @brief Flush d-cache lines to main memory
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*
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* No alignment is required for either <virt> or <size>, but since
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* sys_cache_flush() iterates on the d-cache lines, a d-cache line alignment for
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* both is optimal.
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*
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* The d-cache line size is specified either via the CONFIG_CACHE_LINE_SIZE
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* kconfig option or it is detected at runtime.
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*
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* @param start_addr the pointer to start the multi-line flush
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* @param size the number of bytes that are to be flushed
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*
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* @return N/A
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*/
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void sys_cache_flush(vaddr_t start_addr, size_t size)
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{
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dcache_flush_mlines((uint32_t)start_addr, (uint32_t)size);
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}
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#if defined(CONFIG_CACHE_LINE_SIZE_DETECT)
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size_t sys_cache_line_size;
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static void init_dcache_line_size(void)
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{
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uint32_t val;
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val = _arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
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__ASSERT((val&0xff) != 0, "d-cache is not present");
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val = ((val>>16) & 0xf) + 1;
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val *= 16;
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sys_cache_line_size = (size_t) val;
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}
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#endif
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static int init_dcache(struct device *unused)
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{
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ARG_UNUSED(unused);
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dcache_enable();
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#if defined(CONFIG_CACHE_LINE_SIZE_DETECT)
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init_dcache_line_size();
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#endif
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return 0;
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}
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SYS_INIT(init_dcache, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_CACHE_FLUSHING */
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