292 lines
7.5 KiB
Plaintext
292 lines
7.5 KiB
Plaintext
# ARC EM4 options
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#
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# Copyright (c) 2014 Wind River Systems, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "ARC SoC Selection"
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depends on ARC
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source "arch/arc/soc/*/Kconfig.soc"
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endchoice
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menu "ARC Options"
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depends on ARC
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config ARCH
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default "arc"
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config ARCH_DEFCONFIG
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string
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default "arch/arc/defconfig"
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menu "ARC EM4 processor options"
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config CPU_ARCEM4
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bool
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default y
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select CPU_ARCV2
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select ATOMIC_OPERATIONS_C
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help
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This option signifies the use of an ARC EM4 CPU
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endmenu
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menu "ARCv2 Family Options"
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config CPU_ARCV2
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bool
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default y
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select TICKLESS_IDLE_SUPPORTED
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help
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This option signifies the use of a CPU of the ARCv2 family.
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config NSIM
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prompt "Running on the MetaWare nSIM simulator"
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bool
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default n
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help
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For running on nSIM simulator.
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a) Uses non-XIP to run in RAM.
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b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
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a pc_size of 16 (default).
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config DATA_ENDIANNESS_LITTLE
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bool
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default y
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help
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This is driven by the processor implementation, since it is fixed in
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hardware. The BSP should set this value to 'n' if the data is
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implemented as big endian.
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config NUM_IRQ_PRIO_LEVELS
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int
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prompt "Number of supported interrupt priority levels"
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range 1 16
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help
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Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
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The minimum value is 1.
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The BSP must provide a valid default for proper operation.
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config NUM_IRQS
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int
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prompt "Upper limit of interrupt numbers/IDs used"
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range 17 256
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help
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Interrupts available will be 0 to NUM_IRQS-1.
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The minimum value is 17 as the first 16 entries in the vector
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table are for CPU exceptions.
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The BSP must provide a valid default. This drives the size of the
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vector table.
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config RGF_NUM_BANKS
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int
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prompt "Number of General Purpose Register Banks"
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depends on CPU_ARCV2
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range 1 2
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default 2
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help
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The ARC CPU can be configured to have more than one register
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bank. If fast interrupts are supported (FIRQ), the 2nd
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register bank, in the set, will be used by FIRQ interrupts.
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If fast interrupts are supported but there is only 1
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register bank, the fast interrupt handler must save
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and restore general purpose regsiters.
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config FIRQ_STACK_SIZE
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int
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prompt "Size of stack for FIRQs (in bytes)"
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depends on CPU_ARCV2
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default 1024
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help
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FIRQs and regular IRQs have different stacks so that a FIRQ can start
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running without doing stack switching in software.
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config ARC_STACK_CHECKING
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bool "Enable Stack Checking"
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depends on CPU_ARCV2
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default n
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help
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ARCV2 has a special feature allowing to check stack overflows. This
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enables code that allows using this debug feature
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config FAULT_DUMP
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int
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prompt "Fault dump level"
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default 2
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range 0 2
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help
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Different levels for display information when a fault occurs.
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2: The default. Display specific and verbose information. Consumes
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the most memory (long strings).
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1: Display general and short information. Consumes less memory
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(short strings).
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0: Off.
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config IRQ_OFFLOAD
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bool "Enable IRQ offload"
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default n
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help
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Enable irq_offload() API which allows functions to be synchronously
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run in interrupt context. Uses one entry in the IDT. Mainly useful
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for test cases.
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config XIP
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default n if NSIM
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default y
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config HARVARD
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prompt "Harvard Architecture"
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bool
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default n
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help
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The ARC CPU can be configured to have two busses;
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one for instruction fetching and another that serves as a data bus.
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config ICCM_SIZE
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int "ICCM Size in kB"
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help
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This option specifies the size of the ICCM in kB. It is normally set by
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the board's defconfig file and the user should generally avoid modifying
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it via the menu configuration.
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config ICCM_BASE_ADDRESS
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hex "ICCM Base Address"
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help
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This option specifies the base address of the ICCM on the board. It is
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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config DCCM_SIZE
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int "DCCM Size in kB"
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help
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This option specifies the size of the DCCM in kB. It is normally set by
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the board's defconfig file and the user should generally avoid modifying
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it via the menu configuration.
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config DCCM_BASE_ADDRESS
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hex "DCCM Base Address"
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help
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This option specifies the base address of the DCCM on the board. It is
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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config SRAM_SIZE
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int "SRAM Size in kB"
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help
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This option specifies the size of the SRAM in kB. It is normally set by
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the board's defconfig file and the user should generally avoid modifying
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it via the menu configuration.
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config SRAM_BASE_ADDRESS
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hex "SRAM Base Address"
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help
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This option specifies the base address of the SRAM on the board. It is
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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config FLASH_SIZE
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int "Flash Size in kB"
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help
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This option specifies the size of the flash in kB. It is normally set by
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the board's defconfig file and the user should generally avoid modifying
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it via the menu configuration.
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config FLASH_BASE_ADDRESS
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hex "Flash Base Address"
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help
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This option specifies the base address of the flash on the board. It is
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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config SW_ISR_TABLE
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bool
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prompt "Enable software interrupt handler table"
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default y
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help
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Enable an interrupt handler table implemented in software. This
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table, unlike ISRs connected directly in the vector table, allow
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a parameter to be passed to the interrupt handlers. Also, invoking
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the exeception/interrupt exit stub is automatically done.
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config IRQ_VECTOR_TABLE_CUSTOM
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bool
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prompt "Projects provide a custom static IRQ part of vector table"
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depends on !SW_ISR_TABLE
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default n
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help
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Projects, not the BSP, provide the IRQ part of the vector table.
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This is the table of interrupt handlers with the best potential
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performance, but is the less flexible.
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The ISRs are installed directly in the vector table, thus are
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directly called by the CPU when an interrupt is taken. This adds
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the least overhead when handling an interrupt.
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Downsides:
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- ISRs cannot have a parameter
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- ISRs cannot be connected at runtime
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- ISRs must notify the kernel manually by invoking _ExcExit() when
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then are about to return.
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config IRQ_VECTOR_TABLE_BSP
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bool
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# omit prompt to signify a "hidden" option
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depends on SW_ISR_TABLE || !IRQ_VECTOR_TABLE_CUSTOM
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default y
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help
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Not user-selectable, helps build system logic.
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config CACHE_LINE_SIZE_DETECT
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bool
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prompt "Detect d-cache line size at runtime"
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default n
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help
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This option enables querying the d-cache build register for finding
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the d-cache line size at the expense of taking more memory and code
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and a slightly increased boot time.
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If the CPU's d-cache line size is known in advance, disable this
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option and manually enter the value for CACHE_LINE_SIZE.
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config CACHE_LINE_SIZE
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int
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prompt "Cache line size" if !CACHE_LINE_SIZE_DETECT
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default 32
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help
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Size in bytes of a CPU d-cache line.
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Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
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config ARCH_CACHE_FLUSH_DETECT
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bool
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default n
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config CACHE_FLUSHING
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bool
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default n
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prompt "Enable d-cache flushing mechanism"
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help
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This links in the sys_cache_flush() function, which provides a
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way to flush multiple lines of the d-cache.
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If the d-cache is present, set this to y.
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If the d-cache is NOT present, set this to n.
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endmenu
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source "arch/arc/soc/*/Kconfig"
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endmenu
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