526 lines
15 KiB
ArmAsm
526 lines
15 KiB
ArmAsm
/* intstub.s - VxMicro interrupt management support for IA-32 architecture */
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/*
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* Copyright (c) 2010-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This module implements assembly routines to manage interrupts in VxMicro on
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the Intel IA-32 architecture. More specifically, the interrupt (asynchronous
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exception) stubs are implemented in this module. The stubs are invoked when
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entering and exiting a C interrupt handler.
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*/
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#define _ASMLANGUAGE
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#ifndef CONFIG_NO_ISRS
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#include <nanok.h>
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#include <nanokernel/x86/asm.h>
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#include <offsets.h> /* nanokernel structure offset definitions */
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#include <nanokernel/cpu.h> /* _NANO_ERR_SPURIOUS_INT */
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/* exports (internal APIs) */
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GTEXT(_IntEnt)
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GTEXT(_IntExit)
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GTEXT(_SpuriousIntNoErrCodeHandler)
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GTEXT(_SpuriousIntHandler)
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/* exports (public APIs) */
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GTEXT(irq_lock)
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GTEXT(irq_unlock)
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/* externs */
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GTEXT(_Swap)
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#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
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GTEXT(_SysPowerSaveIdleExit)
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#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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GTEXT(_IntLatencyStart)
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GTEXT(_IntLatencyStop)
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#endif
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/*******************************************************************************
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*
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* _IntEnt - inform the VxMicro kernel of an interrupt
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*
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* This function is called from the interrupt stub created by irq_connect()
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* to inform the VxMicro kernel of an interrupt. This routine increments
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* _NanoKernel.nested (to support interrupt nesting), switches to the
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* base of the interrupt stack, if not already on the interrupt stack, and then
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* saves the volatile integer registers onto the stack. Finally, control is
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* returned back to the interrupt stub code (which will then invoke the
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* "application" interrupt service routine).
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*
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* Only the volatile integer registers are saved since ISRs are assumed not to
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* utilize floating point (or SSE) instructions. If an ISR requires the usage
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* of floating point (or SSE) instructions, it must first invoke nanoCpuFpSave()
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* (or nanoCpuSseSave()) at the beginning of the ISR. A subsequent
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* nanoCpuFpRestore() (or nanoCpuSseRestore()) is needed just prior to returning
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* from the ISR. Note that the nanoCpuFpSave(), nanoCpuSseSave(),
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* nanoCpuFpRestore(), and nanoCpuSseRestore() APIs have not been
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* implemented yet.
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*
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* WARNINGS
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*
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* Host-based tools and the target-based GDB agent depend on the stack frame
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* created by this routine to determine the locations of volatile registers.
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* These tools must be updated to reflect any changes to the stack frame.
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*
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* RETURNS: N/A
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*
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* C function prototype:
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*
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* void _IntEnt (void);
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*
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* NOMANUAL
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*/
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SECTION_FUNC(TEXT, _IntEnt)
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/*
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* The _IntVecSet() routine creates an interrupt-gate descriptor for
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* all connections. The processor will automatically clear the IF
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* bit in the EFLAGS register upon execution of the handler, thus
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* _IntEnt() (and _ExcEnt) need not issue an 'cli' as the first
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* instruction.
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*
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* Clear the direction flag. It is automatically restored when the
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* interrupt exits via the IRET instruction.
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*/
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cld
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/*
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* Note that the processor has pushed both the EFLAGS register
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* and the logical return address (cs:eip) onto the stack prior
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* to invoking the handler specified in the IDT
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*/
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/*
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* swap eax and return address on the current stack;
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* this saves eax on the stack without losing knowledge
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* of how to get back to the interrupt stub
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*/
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#ifdef CONFIG_LOCK_INSTRUCTION_UNSUPPORTED
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pushl (%esp)
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movl %eax, 4(%esp)
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popl %eax
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#else
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xchgl %eax, (%esp)
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#endif /* CONFIG_LOCK_INSTRUCTION_UNSUPPORTED*/
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/*
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* The remaining volatile registers are pushed onto the current
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* stack.
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*/
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pushl %ecx
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pushl %edx
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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/*
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* Volatile registers are now saved it is safe to start measuring
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* how long interrupt are disabled.
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* The interrupt gate created by irq_connect disables the
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* interrupt.
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*
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* Preserve EAX as it contains the stub return address.
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*/
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pushl %eax
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call _IntLatencyStart
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popl %eax
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#endif
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/* load %ecx with &_NanoKernel */
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movl $_NanoKernel, %ecx
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/* switch to the interrupt stack for the non-nested case */
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incl __tNANO_nested_OFFSET(%ecx) /* inc interrupt nest count */
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cmpl $1, __tNANO_nested_OFFSET(%ecx) /* use int stack if !nested */
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jne alreadyOnIntStack
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/* switch to base of the interrupt stack */
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movl %esp, %edx /* save current context stack pointer */
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movl __tNANO_common_isp_OFFSET(%ecx), %esp /* load new sp value */
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/* save context stack pointer onto base of interrupt stack */
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pushl %edx /* Save stack pointer */
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#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
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cmpl $0, __tNANO_idle_OFFSET(%ecx)
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jne _HandleIdle
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/* fast path is !idle, in the pipeline */
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#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
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/* fall through to nested case */
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BRANCH_LABEL(alreadyOnIntStack)
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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/* preserve eax which contain stub return address */
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pushl %eax
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call _IntLatencyStop
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popl %eax
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#endif
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sti /* re-enable interrupts */
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jmp *%eax /* "return" back to stub */
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#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
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BRANCH_LABEL(_HandleIdle)
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pushl %eax
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push __tNANO_idle_OFFSET(%ecx)
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movl $0, __tNANO_idle_OFFSET(%ecx)
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/*
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* Beware that a timer driver's _SysPowerSaveIdleExit() implementation might
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* expect that interrupts are disabled when invoked. This ensures that
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* the calculation and programming of the device for the next timer
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* deadline is not interrupted.
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*/
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call _SysPowerSaveIdleExit
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add $0x4, %esp
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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call _IntLatencyStop
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#endif
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sti /* re-enable interrupts */
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popl %eax
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jmp *%eax /* "return" back to stub */
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#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
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/*******************************************************************************
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*
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* _IntExit - inform the VxMicro kernel of an interrupt exit
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*
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* This function is called from the interrupt stub created by irq_connect()
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* to inform the VxMicro kernel that the processing of an interrupt has
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* completed. This routine decrements _NanoKernel.nested (to support interrupt
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* nesting), restores the volatile integer registers, and then switches
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* back to the interrupted context's stack, if this isn't a nested interrupt.
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*
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* Finally, control is returned back to the interrupted fiber context or ISR.
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* A context switch _may_ occur if the interrupted context was a task context,
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* in which case one or more other fiber and task contexts will execute before
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* this routine resumes and control gets returned to the interrupted task.
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*
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* RETURNS: N/A
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*
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* C function prototype:
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*
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* void _IntExit (void);
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*
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* NOMANUAL
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*/
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SECTION_FUNC(TEXT, _IntExit)
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cli /* disable interrupts */
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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call _IntLatencyStart
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#endif
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/* determine whether exiting from a nested interrupt */
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movl $_NanoKernel, %ecx
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decl __tNANO_nested_OFFSET(%ecx) /* dec interrupt nest count */
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jne nestedInterrupt /* 'iret' if nested case */
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/*
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* Determine whether the execution of the ISR requires a context
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* switch. If the interrupted context is PREEMPTIBLE and
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* _NanoKernel.fiber is non-NULL, a _Swap() needs to occur.
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*/
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movl __tNANO_current_OFFSET (%ecx), %eax
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testl $PREEMPTIBLE, __tCCS_flags_OFFSET(%eax)
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je noReschedule
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cmpl $0, __tNANO_fiber_OFFSET (%ecx)
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je noReschedule
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/*
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* Set the INT_ACTIVE bit in the tCCS to allow the upcoming call to
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* _Swap() to determine whether non-floating registers need to be
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* preserved using the lazy save/restore algorithm, or to indicate to
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* debug tools that a preemptive context switch has occurred.
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*
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* Setting the NO_METRICS bit tells _Swap() that the per-context
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* [totalRunTime] calculation has already been performed and that
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* there is no need to do it again.
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*/
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#if defined(CONFIG_FP_SHARING) || defined(CONFIG_GDB_INFO)
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orl $INT_ACTIVE, __tCCS_flags_OFFSET(%eax)
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#endif
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/*
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* A context reschedule is required: keep the volatile registers of
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* the interrupted context on the context's stack. Utilize
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* the existing _Swap() primitive to save the remaining
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* thread's registers (including floating point) and perform
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* a switch to the new context.
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*/
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popl %esp /* switch back to kernel stack */
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pushfl /* push KERNEL_LOCK_KEY argument */
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call _Swap
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/*
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* The interrupted context thread has now been scheduled,
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* as the result of a _later_ invocation of _Swap().
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*
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* Now need to restore the interrupted context's environment before
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* returning control to it at the point where it was interrupted ...
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*/
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#if ( defined(CONFIG_FP_SHARING) || \
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defined(CONFIG_GDB_INFO) )
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/*
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* _Swap() has restored the floating point registers, if needed.
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* Clear the INT_ACTIVE bit of the interrupted context's tCCS
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* since it has served its purpose.
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*/
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movl _NanoKernel + __tNANO_current_OFFSET, %eax
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andl $~INT_ACTIVE, __tCCS_flags_OFFSET (%eax)
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#endif /* CONFIG_FP_SHARING || CONFIG_GDB_INFO */
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addl $4, %esp /* pop KERNEL_LOCK_KEY argument */
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/* Restore volatile registers and return to the interrupted context */
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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call _IntLatencyStop
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#endif
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popl %edx
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popl %ecx
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popl %eax
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/* Pop of EFLAGS will re-enable interrupts and restore direction flag */
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iret
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BRANCH_LABEL(noReschedule)
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/*
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* A thread reschedule is not required; switch back to the
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* interrupted thread's stack and restore volatile registers
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*/
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popl %esp /* pop thread stack pointer */
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/* fall through to 'nestedInterrupt' */
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/*
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* For the nested interrupt case, the interrupt stack must still be
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* utilized, and more importantly, a rescheduling decision must
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* not be performed.
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*/
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BRANCH_LABEL(nestedInterrupt)
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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call _IntLatencyStop
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#endif
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popl %edx /* pop volatile registers in reverse order */
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popl %ecx
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popl %eax
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/* Pop of EFLAGS will re-enable interrupts and restore direction flag */
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iret
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/*******************************************************************************
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*
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* _SpuriousIntHandler -
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* _SpuriousIntNoErrCodeHandler - spurious interrupt handler stubs
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*
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* Interrupt-gate descriptors are statically created for all slots in the IDT
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* that point to _SpuriousIntHandler() or _SpuriousIntNoErrCodeHandler(). The
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* former stub is connected to exception vectors where the processor pushes an
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* error code onto the stack (or kernel stack) in addition to the EFLAGS/CS/EIP
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* records.
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*
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* A spurious interrupt is considered a fatal condition, thus this routine
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* merely sets up the 'reason' and 'pEsf' parameters to the BSP provided
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* routine: _SysFatalHwErrorHandler(). In other words, there is no provision
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* to return to the interrupted context and thus the volatile registers
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* are not saved.
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*
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* RETURNS: Never returns
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*
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* C function prototype:
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*
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* void _SpuriousIntHandler (void);
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*
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* INTERNAL
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* The _IntVecSet() routine creates an interrupt-gate descriptor for all
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* connections. The processor will automatically clear the IF bit
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* in the EFLAGS register upon execution of the handler,
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* thus _SpuriousIntNoErrCodeHandler()/_SpuriousIntHandler() shall be
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* invoked with interrupts disabled.
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*
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* NOMANUAL
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*/
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SECTION_FUNC(TEXT, _SpuriousIntNoErrCodeHandler)
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pushl $0 /* push dummy err code onto stk */
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/* fall through to _SpuriousIntHandler */
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SECTION_FUNC(TEXT, _SpuriousIntHandler)
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cld /* Clear direction flag */
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/*
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* The task's regular stack is being used, but push the value of ESP
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* anyway so that _ExcExit can "recover the stack pointer"
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* without determining whether the exception occured while CPL=3
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*/
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pushl %esp /* push cur stack pointer: pEsf arg */
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BRANCH_LABEL(finishSpuriousInt)
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/* re-enable interrupts */
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sti
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/* push the 'unsigned int reason' parameter */
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pushl $_NANO_ERR_SPURIOUS_INT
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BRANCH_LABEL(callFatalHandler)
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/* call the fatal error handler */
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call _NanoFatalErrorHandler
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/* handler shouldn't return, but call it again if it does */
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jmp callFatalHandler
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/*******************************************************************************
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*
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* irq_lock - disable interrupts on the local CPU
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*
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* This routine disables interrupts. It can be called from either interrupt
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* or context level. This routine returns an architecture-dependent
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* lock-out key representing the "interrupt disable state" prior to the call;
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* this key can be passed to fiber_enable_ints() to re-enable interrupts.
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*
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* The lock-out key should only be used as the argument to the
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* fiber_enable_ints() API. It should never be used to manually re-enable
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* interrupts or to inspect or manipulate the contents of the source register.
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*
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* WARNINGS
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* Invoking a VxMicro system routine with interrupts locked may result in
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* interrupts being re-enabled for an unspecified period of time. If the
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* called routine blocks, interrupts will be re-enabled while another
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* context executes, or while the system is idle.
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*
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* The "interrupt disable state" is an attribute of a context, i.e. it's part
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* of the context context. Thus, if a context disables interrupts and
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* subsequently invokes a VxMicro system routine that causes the calling context
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* to block, the interrupt disable state will be restored when the context is
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* later rescheduled for execution.
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*
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* RETURNS: An architecture-dependent lock-out key representing the
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* "interrupt disable state" prior to the call.
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*/
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SECTION_FUNC(TEXT, irq_lock)
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pushfl
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cli
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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call _IntLatencyStart
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#endif
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popl %eax
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ret
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/*******************************************************************************
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*
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* irq_unlock - enable interrupts on the local CPU
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*
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* This routine re-enables interrupts on the local CPU. The <key> parameter
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* is an architecture-dependent lock-out key that is returned by a previous
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* invocation of irq_lock().
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*
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* This routine can be called from either a context or ISR context.
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*/
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SECTION_FUNC(TEXT, irq_unlock)
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testl $0x200, SP_ARG1(%esp)
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jz skipIntEnable
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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call _IntLatencyStop
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#endif
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sti
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BRANCH_LABEL(skipIntEnable)
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ret
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#endif /* CONFIG_NO_ISRS */
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