152 lines
4.8 KiB
ArmAsm
152 lines
4.8 KiB
ArmAsm
/* i8259Boi.s - Intel 8259A PIC BOI Handler */
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/*
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* Copyright (c) 2013-2015 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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The PIC BOI handler determines if the IRQ in question is a spurious or real
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interrupt. The IRQ inputs must remain high until after the falling edge of the
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first INTA. A spurious interrupt on IRQ 7 can occur if the IRQ input goes low
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before this time when the CPU acknowledges the interrupt. In this case, the
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interrupt handler should simply return without sending an EOI command.
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The distinction between a spurious interrupt and a real one is detected by
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looking at the in service register (ISR). The bit (bit 7) will be 1 indicating
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a real IRQ has been inserted.
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*/
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/* includes */
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#define _ASMLANGUAGE
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#include <nanokernel/cpu.h>
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#include <nanokernel/x86/asm.h>
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#include <drivers/pic.h>
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#include <board.h>
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/* externs */
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GTEXT(_IntExit)
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GDATA(_I8259SpuriousIntCount)
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/*******************************************************************************
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*
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* _i8259_boi_master - detect whether it is spurious interrupt or not
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*
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* This routine is called before the user's interrupt handler to detect the
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* spurious interrupt on the master PIC. If a spurious interrupt condition is
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* detected, a global variable is incremented and the execution of the interrupt
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* stub is "short circuited", i.e. a return to the interrupted context
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* occurs.
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*
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* void _i8259_boi_master (void)
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*
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* RETURNS: N/A
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*/
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SECTION_FUNC(TEXT, _i8259_boi_master)
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/* disable interrupts */
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pushfl
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cli
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/* Master PIC, get contents of in serivce register */
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PLB_BYTE_REG_WRITE (0x0b, PIC_PORT1(PIC_MASTER_BASE_ADRS))
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PLB_BYTE_REG_READ (PIC_PORT1(PIC_MASTER_BASE_ADRS))
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/* enable interrupts */
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popfl
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/* Contents of ISR in %AL */
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andb $0x80, %al
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je spur_isr
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ret
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/*******************************************************************************
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*
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* _i8259_boi_slave - detect whether it is spurious interrupt or not
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*
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* This routine is called before the user's interrupt handler to detect the
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* spurious interrupt on the slave PIC. If a spurious interrupt condition is
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* detected, a global variable is incremented and the execution of the interrupt
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* stub is "short circuited", i.e. a return to the interrupted context
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* occurs.
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*
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* void _i8259_boi_slave (void)
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*
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* RETURNS: N/A
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*/
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SECTION_FUNC(TEXT, _i8259_boi_slave)
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/* disable interrupts */
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pushfl
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cli
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/* Slave PIC, get contents of in serivce register */
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PLB_BYTE_REG_WRITE (0x0b, PIC_PORT1 (PIC_SLAVE_BASE_ADRS))
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PLB_BYTE_REG_READ (PIC_PORT1 (PIC_SLAVE_BASE_ADRS))
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/* Contents of ISR in EAX */
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testb %al, %al
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jne check_isr
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/* Check the master PIC's in service register for slave PIC IRQ */
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PLB_BYTE_REG_WRITE (0x0b, PIC_PORT1(PIC_MASTER_BASE_ADRS))
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PLB_BYTE_REG_READ (PIC_PORT1(PIC_MASTER_BASE_ADRS))
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/* Slave connected to IRQ2 on master */
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testb $0x4, %al
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je check_isr
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/* Send non-specific EOI to the master PIC IRQ2 */
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PLB_BYTE_REG_WRITE (I8259_EOI, PIC_IACK (PIC_MASTER_BASE_ADRS));
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BRANCH_LABEL(check_isr)
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/* unlock interrupts */
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popfl
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/* Contents of ISR for either PIC in %AL */
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andb $0x80, %al
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je spur_isr
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ret
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BRANCH_LABEL(spur_isr)
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/* An actual spurious interrupt. Increment counter and short circuit */
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incl _I8259SpuriousIntCount
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/* Pop the return address */
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addl $4, %esp
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jmp _IntExit
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