663 lines
19 KiB
ArmAsm
663 lines
19 KiB
ArmAsm
/* crt0.s - crt0 module for the IA-32 boards */
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/*
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* Copyright (c) 2010-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This module contains the initial code executed by the VxMicro ELF image
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after having been loaded into RAM.
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INTERNAL
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The CONFIG_PROT_MODE_SWITCH configuration option was once required when
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booting/loading an image into a Simics simulation environment, since the
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invocation technique involved halting the BIOS code (via a breakpoint) before
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it attempted to load a bootloader from disk, and then dumping the VxMicro ELF
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image into memory. This meant that the IA-32 processor was executing in 16-bit
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real mode (aka real mode) when __start() was called, thus requiring __start()
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to perform the 16-bit to 32-bit transition code and other sundry PC-related
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initialization steps (eg. enabling address line A20).
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Later advances now allow a VxMicro image to be loaded into the Simics environment
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after the system is already in 32-bit protected mode and address line A20 is
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enabled. Consequently, the CONFIG_PROT_MODE_SWITCH configuration option
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is no longer used by this BSP, and *all* booting scenarios for the BSP (e.g.
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via GRUB or any other multiboot compliant bootloader) now assume that the
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system is already in 32-bit protected mode and address line A20 is enabled.
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However, the code associated with CONFIG_PROT_MODE_SWITCH has been left
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in place in case future booting scenarios arise which require its use.
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POMS memory model
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When a kernel configured for POMS starts, it runs at a physical address that
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is different from the logical address it has been linked at. So, symbols are not
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accessible without doing some translation. It is best then to run at a logical
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address ASAP to access give access to symbols, especially to be able to run C
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code. To do that, we start using segment selectors for CS/DS/SS that are mapping
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the physical location to the logical location at which the kernel is linked, ie.
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0x1000. Those segment selectors are 0x18 for CS and 0x20 for DS/SS.
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Before these are used, the startup code uses physical address locations of
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some key symbols (eg. the gdt) provided by the linker script.
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*/
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#define _ASMLANGUAGE
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#include <nanokernel/x86/asm.h>
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/* exports (private APIs) */
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GTEXT(__start)
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/* externs */
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GTEXT(_Cstart)
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GDATA(_IdtBaseAddress)
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GDATA(_InterruptStack)
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#if defined(CONFIG_SSE)
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GDATA(_Mxcsr)
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#endif /* CONFIG_SSE */
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#if defined(CONFIG_BOOT_TIME_MEASUREMENT)
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GDATA(__start_tsc)
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#endif
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#ifdef CONFIG_ADVANCED_IDLE
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GDATA(_AdvIdleCheckSleep)
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GDATA(_AdvIdleStart)
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#endif /* CONFIG_ADVANCED_IDLE */
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#ifdef CONFIG_PROT_MODE_SWITCH
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/* cold start code in 16-bit real mode */
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/*
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* Switch 'gas' into 16-bit mode, i.e. use a default operand and
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* address size of 16 bits since the processor is executing in
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* 16-bit real mode. The prevents the assembler from inserting
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* 0x66 or 0x67 instruction prefixes when using 16-bit data values
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* or 16-bit pointers.
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*/
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.code16
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.section ".xreset", "ax"
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.balign 16,0x90
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__start:
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#ifdef CONFIG_BOOT_TIME_MEASUREMENT
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/*
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* Record BootTime from start of Kernel.
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* Store value temporarily in Register EDI & ESI and
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* write to memory once memory access is allowed.
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* That is, once the data segment register has been setup to access
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* the .data/.rodata/.bss section of the linked image.
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*/
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rdtsc
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mov %eax, %esi /* low value */
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mov %edx, %edi /* high value */
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#endif
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/*
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* Ensure interrupts are disabled. Interrupts are enabled when
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* the first VxMicro thread context switch occurs.
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*/
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cli
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/*
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* BSPs that need to enable the A20 line to boot properly wil enable this
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* option.
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*/
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#ifdef CONFIG_BOOT_A20_ENABLE
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/*
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* Set the stack pointer to just before the start of the .text
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* section. This needs to be performed before any BIOS invocations.
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*
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* Note that attempting to set the stack pointer to beyond the end of
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* the static ELF image (indicated via the _end symbol) may result
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* in pointer wrap-around for images with large BSS sections
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* (since the processor is still in "real" mode and thus the stack
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* pointer is only a 16 bits).
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*/
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movl $__start, %esp
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/*
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* Before switching to 32-bit protected mode, Gate-A20 must be
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* enabled (legacy PC hardware issue).
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*
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* The classical method of enabling address line A20 via the 8042
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* keyboard controller will not be performed. Instead, it will be
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* assumed that the board has a relatively modern BIOS which supports
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* the following int 15h function:
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*
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* - int 15h: ax=2400 -> disable A20
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* - int 15h: ax=2401 -> enable A20
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* If successful: CF clear, AH = 00h
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* On error: CF set, AH = status
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* Status: 01h keyboard controller is in secure mode
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* 86h function not supported
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* - int 15h: ax=2402 -> query status A20
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* status (0: disabled, 1: enabled) is returned in AL
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* - int 15h: ax=2403 -> query A20 support (kbd or port 92)
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* status (bit 0: kbd, bit 1: port 92) is returned in BX
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*
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* Return values:
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* If successful: carry flag (CF) clear, AH = 00h
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* On error: carry flag (CF) set, AH = status
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* Status: 01h keyboard controller is in secure mode
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* 86h function not supported
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*
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* If the int15h method fails, then the system control port A
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* (I/O port 0x92) method will be used.
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*/
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movw $0x2401, %ax /* ax=2401 -> enable A20 */
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int $0x15
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jnc A20Enabled /* CF = 1 -> try I/O port 0x92 method */
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/* try enabling Gate-A20 via system control port A (I/O port 0x92) */
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movb $0x02, %al
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outb %al, $0x92
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xorl %ecx, %ecx
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A20EnableWait:
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inb $0x92, %al
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andb $0x02, %al
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loopz A20EnableWait
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A20Enabled:
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#endif /* CONFIG_BOOT_A20_ENABLE */
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/* load Interrupt Descriptor and Global Descriptor tables (IDT & GDT) */
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lgdt %cs:_GdtRom /* load 32-bit operand size GDT */
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movl %cr0, %eax /* move CR0 to EAX */
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orl $0x1, %eax /* set the Protection Enable (PE) bit */
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andl $0x9fffffff, %eax /* Enable write-back caching */
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movl %eax, %cr0 /* move EAX to CR0 */
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jmp %cs:vstartProtMode /* flush prefetch input queue */
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vstartProtMode:
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/*
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* At this point, the processor is executing in 32-bit protected
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* mode, but the CS selector hasn't been loaded yet, i.e. the
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* processor is still effectively executing instructions from a
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* 16-bit code segment (thus the .code16 assembler directive still
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* needs to be in effect.
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*/
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movw $0x10,%ax /* data segment selector (entry = 3) */
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movw %ax,%ds /* set DS */
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movw %ax,%es /* set ES */
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movw %ax,%fs /* set FS */
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movw %ax,%gs /* set GS */
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movw %ax,%ss /* set SS */
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/* this is 'ljmp $0x08:$vstart32BitCode': diab 5.9.1.0 does not encode
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* it correctly */
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.byte 0xea
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.long vstart32BitCode
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.byte 0x08
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.byte 0x00
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/*
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* Switch 'gas' back to 32-bit data and address defaults. This
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* can only be performed after loading the CS segment register
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* (via an lcall instruction, for example) with a segment selector
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* that describes a 32-bit code segment.
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*/
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.code32
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SECTION_FUNC(TEXT_START, vstart32BitCode)
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#else /* !CONFIG_PROT_MODE_SWITCH */
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/* processor is executing in 32-bit protected mode */
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.balign 16,0x90
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SECTION_FUNC(TEXT_START, __start)
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#ifdef CONFIG_BOOT_TIME_MEASUREMENT
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/*
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* Record BootTime from start of Kernel.
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* Store value temporarily in Register edi & esi and
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* write to memory once memory access is allowed.
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* That is, once the data segment register has been setup to access
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* the .data/.rodata/.bss section of the linked image.
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*/
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rdtsc
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mov %eax, %esi /* low value */
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mov %edx, %edi /* high value */
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#endif
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/* Enable write-back caching by clearing the NW and CD bits */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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/*
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* Ensure interrupts are disabled. Interrupts are enabled when
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* the first VxMicro thread context switch occurs.
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*/
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cli
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/*
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* Although the bootloader sets up an Interrupt Descriptor Table (IDT)
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* and a Global Descriptor Table (GDT), the specification encourages
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* booted operating systems to setup their own IDT and GDT.
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*/
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lgdt _GdtRom /* load 32-bit operand size GDT */
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#endif /* !CONFIG_PROT_MODE_SWITCH */
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lidt _Idt /* load 32-bit operand size IDT */
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#ifndef CONFIG_PROT_MODE_SWITCH
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#ifdef CONFIG_BOOTLOADER_UNKNOWN
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/*
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* Where we do not do the protected mode switch and the
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* bootloader is unknown, do not make the assumption that the segment
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* registers are set correctly.
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*
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* This is a special case for the generic_pc BSP, which must work for
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* multiple platforms (QEMU, SIMICS, generic PC board, etc.). With other
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* BSPs the bootloader is well known so assumptions can be made.
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*/
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movw $0x10, %ax /* data segment selector (entry = 3) */
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movw %ax, %ds /* set DS */
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movw %ax, %es /* set ES */
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movw %ax, %fs /* set FS */
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movw %ax, %gs /* set GS */
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movw %ax, %ss /* set SS */
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/* this is 'ljmp $0x08:$_csSet': diab 5.9.1.0 does not encode
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* it correctly */
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.byte 0xea
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.long __csSet
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.byte 0x08
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.byte 0x00
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__csSet:
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#endif /* CONFIG_BOOTLOADER_UNKNOWN */
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#endif /* CONFIG_PROT_MODE_SWITCH */
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#ifdef CONFIG_BOOT_TIME_MEASUREMENT
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/*
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* Store rdtsc result from temporary regiter ESI & EDI into memory.
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*/
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mov %esi, __start_tsc /* low value */
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mov %edi, __start_tsc+4 /* high value */
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#endif
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#ifdef CONFIG_ADVANCED_IDLE
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/*
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* Set up the temporary stack to call the _AdvIdleCheckSleep routine
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* We use the separate stack here in order to avoid the memory
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* corruption if the system recovers from deep sleep
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*/
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movl $_AdvIdleStack, %esp
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addl $CONFIG_ADV_IDLE_STACK_SIZE, %esp
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/* align to stack boundary: ROUND_DOWN (%esp, 4) */
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andl $0xfffffffc, %esp
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/*
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* Invoke _AdvIdleCheckSleep() routine that checks if we are restoring
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* from deep sleep or not. The routine returns non-zero if the kernel
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* is recovering from deep sleep and to 0 if a cold boot is needed. The
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* kernel can skip floating point initialization, BSS initialization,
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* and data initialization if recovering from deep sleep.
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*/
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call _AdvIdleCheckSleep
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cmpl $0, %eax
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jne memInitDone
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#endif /* CONFIG_ADVANCED_IDLE */
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#if !defined(CONFIG_FLOAT)
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/*
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* Force an #NM exception for floating point instructions
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* since FP support hasn't been configured
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*/
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movl %cr0, %eax /* move CR0 to EAX */
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orl $0x2e, %eax /* CR0[NE+TS+EM+MP]=1 */
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movl %eax, %cr0 /* move EAX to CR0 */
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#else
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/*
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* Permit use of x87 FPU instructions
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*
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* Note that all floating point exceptions are masked by default,
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* and that _no_ handler for x87 FPU exceptions (#MF) is provided.
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*/
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movl %cr0, %eax /* move CR0 to EAX */
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orl $0x22, %eax /* CR0[NE+MP]=1 */
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andl $~0xc, %eax /* CR0[TS+EM]=0 */
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movl %eax, %cr0 /* move EAX to CR0 */
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fninit /* set x87 FPU to its default state */
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#if defined(CONFIG_SSE)
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/*
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* Permit use of SSE instructions
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*
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* Note that all SSE exceptions are masked by default,
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* and that _no_ handler for SSE exceptions (#XM) is provided.
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*/
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movl %cr4, %eax /* move CR4 to EAX */
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orl $0x200, %eax /* CR4[OSFXSR] = 1 */
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andl $~0x400, %eax /* CR4[OSXMMEXCPT] = 0 */
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movl %eax, %cr4 /* move EAX to CR4 */
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ldmxcsr _Mxcsr /* initialize SSE control/status reg */
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#endif /* CONFIG_SSE */
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#endif /* !CONFIG_FLOAT */
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#ifdef CONFIG_XIP
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/*
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* copy DATA section from ROM to RAM region
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* DATA is followed by BSS section.
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* Given that BSS section is initialized after this copy, we can
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* safely over-write into the next section.
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* Note: __data_num_words is a multiple of 4 bytes
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* rounded up to next 4 bytes.
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* Note: the sections might not be 4 byte aligned.
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*/
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movl $__data_ram_start, %edi /* DATA in RAM (dest) */
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movl $__data_rom_start, %esi /* DATA in ROM (src) */
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movl $__data_num_words, %ecx /* Size of DATA in quad bytes */
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je copyDataDone
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#ifdef CONFIG_SSE
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/* copy 16 bytes at a time using XMM until < 16 bytes remain */
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movl %ecx ,%edx /* save number of quad bytes */
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shrl $2, %ecx /* How many 16 bytes? */
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je dataWords
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dataDQ:
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movdqu (%esi), %xmm0
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movdqu %xmm0, (%edi)
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addl $16, %esi
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addl $16, %edi
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loop dataDQ
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dataWords:
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movl %edx, %ecx /* restore # quad bytes */
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andl $0x3, %ecx /* only need to copy at most 3 quad bytes */
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#endif /* CONFIG_SSE */
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rep
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movsl /* copy data 4 bytes at a time */
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copyDataDone:
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#endif /* CONFIG_XIP */
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/*
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* Clear BSS: bzero (__bss_start, __bss_num_words*4)
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*
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* It's assumed that BSS size will be a multiple of a long (4 bytes),
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* and aligned on a double word (32-bit) boundary
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*/
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#ifdef CONFIG_SSE
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/* use XMM register to clear 16 bytes at a time */
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pxor %xmm0, %xmm0 /* zero out xmm0 register */
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movl $__bss_start, %edi /* load BSS start address */
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movl $__bss_num_words, %ecx /* number of quad bytes in .bss */
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movl %ecx, %edx /* make a copy of # quad bytes */
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shrl $2, %ecx /* How many multiples of 16 byte ? */
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je bssWords
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bssDQ:
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movdqu %xmm0, (%edi) /* zero 16 bytes... */
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addl $16, %edi
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loop bssDQ
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/* fall through to handle the remaining double words (32-bit chunks) */
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bssWords:
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xorl %eax, %eax /* fill memory with 0 */
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movl %edx, %ecx /* move # quad bytes into ECX (for rep) */
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andl $0x3, %ecx /* only need to zero at most 3 quad bytes */
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cld
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rep
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stosl /* zero memory per 4 bytes */
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#else /* !CONFIG_SSE */
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/* clear out BSS double words (32-bits at a time) */
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xorl %eax, %eax /* fill memory with 0 */
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movl $__bss_start, %edi /* load BSS start address */
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movl $__bss_num_words, %ecx /* number of quad bytes */
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cld
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rep
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stosl /* zero memory per 4 bytes */
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#endif /* CONFIG_SSE */
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memInitDone:
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/*
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* Set the stack pointer to the area used for the interrupt stack.
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* Note this stack is only used during the execution of __start() and
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* _Cstart(), i.e. only until the multi-tasking VxMicro kernel is
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* initialized. The dual-purposing of this area of memory is safe since
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* interrupts are disabled until the first context switch.
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*/
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movl $_InterruptStack, %esp
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addl $CONFIG_ISR_STACK_SIZE, %esp
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/* align to stack boundary: ROUND_DOWN (%esp, 4) */
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andl $0xfffffffc, %esp
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/* activate RAM-based Global Descriptor Table (GDT) */
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lgdt %ds:_Gdt
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#if defined (CONFIG_ADVANCED_IDLE)
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/*
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* Invoke _AdvIdleStart(_Cstart, _Gdt, _GlobalTss) by jumping to it.
|
|
* If it's a cold boot, this routine jumps to _Cstart and the normal
|
|
* kernel boot sequence continues; otherwise, it uses the TSS info
|
|
* saved in the GDT to resumes kernel processing at the point it was
|
|
* when the system went into deep sleep; that is, _AdvIdleFunc()
|
|
* completes and returns a non-zero value.
|
|
*/
|
|
|
|
pushl $_GlobalTss
|
|
pushl $_Gdt
|
|
pushl $_Cstart
|
|
call _AdvIdleStart
|
|
#else
|
|
/* Jump to C portion of VxMicro kernel initialization and never return */
|
|
|
|
jmp _Cstart
|
|
|
|
#endif /* CONFIG_ADVANCED_IDLE */
|
|
|
|
#if defined(CONFIG_SSE)
|
|
|
|
/* SSE control & status register initial value */
|
|
|
|
_Mxcsr:
|
|
.long 0x1f80 /* all SSE exceptions clear & masked */
|
|
|
|
#endif /* CONFIG_SSE */
|
|
|
|
/* Interrupt Descriptor Table (IDT) definition */
|
|
|
|
_Idt:
|
|
.word (CONFIG_IDT_NUM_VECTORS * 8) - 1 /* limit: size of IDT-1 */
|
|
|
|
/*
|
|
* Physical start address = 0. When executing natively, this
|
|
* will be placed at the same location as the interrupt vector table
|
|
* setup by the BIOS (or GRUB?).
|
|
*/
|
|
|
|
.long _IdtBaseAddress /* physical start address */
|
|
|
|
|
|
#ifdef CONFIG_BOOTLOADER_UNKNOWN
|
|
/* Multiboot header definition is needed for some bootloaders */
|
|
|
|
/*
|
|
* The multiboot header must be in the first 8 Kb of the kernel image
|
|
* (not including the ELF section header(s)) and be aligned on a
|
|
* 4 byte boundary.
|
|
*/
|
|
|
|
.balign 4,0x90
|
|
|
|
.long 0x1BADB002 /* multiboot magic number */
|
|
|
|
/*
|
|
* Flags = no bits are being set, specifically bit 16 is not being
|
|
* set since the supplied kernel image is an ELF file, and the
|
|
* multiboot loader shall use the information from the program and
|
|
* section header to load and boot the kernel image.
|
|
*/
|
|
|
|
.long 0x00000000
|
|
|
|
/*
|
|
* checksum = 32-bit unsigned value which, when added to the other
|
|
* magic fields (i.e. "magic" and "flags"), must have a 32-bit
|
|
* unsigned sum of zero.
|
|
*/
|
|
|
|
.long -(0x1BADB002 + 0)
|
|
#endif /* CONFIG_BOOTLOADER_UNKNOWN */
|
|
|
|
|
|
#ifdef CONFIG_PROT_MODE_SWITCH
|
|
/* Global Descriptor Table (GDT) definition */
|
|
.section ".xreset", "ax"
|
|
.align 8
|
|
#endif /* CONFIG_PROT_MODE_SWITCH */
|
|
|
|
_GdtRom:
|
|
.word _GdtRomEnd - _GdtRomEntries - 1 /* Limit on GDT */
|
|
.long _GdtRomEntries /* table address: _GdtRomEntries */
|
|
|
|
|
|
.balign 16,0x90
|
|
|
|
/*
|
|
* The following 3 GDT entries implement the so-called "basic
|
|
* flat model", i.e. a single code segment descriptor and a single
|
|
* data segment descriptor such that VxMicro has access to a continuous,
|
|
* unsegmented address space. Both segment descriptors map the entire
|
|
* linear address space (i.e. 0 to 4 GB-1), thus the segmentation
|
|
* mechanism will never generate "out of limit memory reference"
|
|
* exceptions even if physical memory does not reside at the referenced
|
|
* address.
|
|
*
|
|
* The 'A' (accessed) bit in the type field is _not_ set for all the
|
|
* data/code segment descriptors to accomodate placing these entries
|
|
* in ROM, since such use is not planned for this platform.
|
|
*/
|
|
|
|
_GdtRomEntries:
|
|
|
|
/* Entry 0 (selector=0x0000): The "NULL descriptor" */
|
|
|
|
.word 0x0000
|
|
.word 0x0000
|
|
.byte 0x00
|
|
.byte 0x00
|
|
.byte 0x00
|
|
.byte 0x00
|
|
|
|
/* Entry 1 (selector=0x0008): Code descriptor: DPL0 */
|
|
|
|
.word 0xffff /* limit: xffff */
|
|
.word 0x0000 /* base : xxxx0000 */
|
|
.byte 0x00 /* base : xx00xxxx */
|
|
.byte 0x9a /* Code e/r, Present, DPL0 */
|
|
.byte 0xcf /* limit: fxxxx, Page Gra, 32bit */
|
|
.byte 0x00 /* base : 00xxxxxx */
|
|
|
|
/* Entry 2 (selector=0x0010): Data descriptor: DPL0 */
|
|
|
|
.word 0xffff /* limit: xffff */
|
|
.word 0x0000 /* base : xxxx0000 */
|
|
.byte 0x00 /* base : xx00xxxx */
|
|
.byte 0x92 /* Data r/w, Present, DPL0 */
|
|
.byte 0xcf /* limit: fxxxx, Page Gra, 32bit */
|
|
.byte 0x00 /* base : 00xxxxxx */
|
|
|
|
|
|
#ifdef CONFIG_PROT_MODE_SWITCH
|
|
/* Reset vector */
|
|
.code16
|
|
.section ".xresetv", "ax"
|
|
_ResetVector:
|
|
jmp __start
|
|
#endif /* CONFIG_PROT_MODE_SWITCH */
|
|
|
|
_GdtRomEnd:
|
|
|
|
#ifdef CONFIG_ADVANCED_IDLE
|
|
.section .NOINIT
|
|
.balign 4,0x90
|
|
_AdvIdleStack:
|
|
.fill CONFIG_ADV_IDLE_STACK_SIZE
|
|
#endif
|