150 lines
4.3 KiB
C
150 lines
4.3 KiB
C
/* board.h - board configuration macros for the ti_lm3s6965 BSP */
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/*
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* Copyright (c) 2013-2015 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This header file is used to specify and describe board-level aspects for
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the 'ti_lm3s6965' BSP.
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*/
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#ifndef _BOARD__H_
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#define _BOARD__H_
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#include <misc/util.h>
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#define SRAM_SIZE KB(64)
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/* default system clock */
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#define SYSCLK_DEFAULT_IOSC_HZ MHZ(12)
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/* address bases */
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#define PERIPH_ADDR_BASE_UART0 0x4000C000
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#define PERIPH_ADDR_BASE_UART1 0x4000D000
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#define PERIPH_ADDR_BASE_UART2 0x4000E000
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/* IRQs */
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#define IRQ_GPIO_PORTA 0
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#define IRQ_GPIO_PORTB 1
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#define IRQ_GPIO_PORTC 2
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#define IRQ_GPIO_PORTD 3
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#define IRQ_GPIO_PORTE 4
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#define IRQ_UART0 5
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#define IRQ_UART1 6
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#define IRQ_SSI0 7
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#define IRQ_I2C0 8
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#define IRQ_PWM_FAULT 9
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#define IRQ_PWM_GEN0 10
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#define IRQ_PWM_GEN1 11
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#define IRQ_PWM_GEN2 12
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#define IRQ_QEI0 13
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#define IRQ_ADC0_SEQ0 14
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#define IRQ_ADC0_SEQ1 15
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#define IRQ_ADC0_SEQ2 16
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#define IRQ_ADC0_SEQ3 17
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#define IRQ_WDOG0 18
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#define IRQ_TIMER0A 19
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#define IRQ_TIMER0B 20
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#define IRQ_TIMER1A 21
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#define IRQ_TIMER1B 22
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#define IRQ_TIMER2A 23
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#define IRQ_TIMER2B 24
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#define IRQ_ANALOG_COMP0 25
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#define IRQ_ANALOG_COMP1 26
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#define IRQ_RESERVED0 27
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#define IRQ_SYS_CONTROL 28
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#define IRQ_FLASH_MEM_CTRL 29
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#define IRQ_GPIO_PORTF 30
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#define IRQ_GPIO_PORTG 31
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#define IRQ_RESERVED1 32
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#define IRQ_UART2 33
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#define IRQ_RESERVED2 34
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#define IRQ_TIMER3A 35
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#define IRQ_TIMER3B 36
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#define IRQ_I2C1 37
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#define IRQ_QEI1 38
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#define IRQ_RESERVED3 39
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#define IRQ_RESERVED4 40
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#define IRQ_RESERVED5 41
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#define IRQ_ETH 42
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#define IRQ_HIBERNATION 43
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#ifndef _ASMLANGUAGE
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#include <misc/util.h>
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#include <drivers/rand32.h>
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/* uart configuration settings */
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#define CONFIG_UART_NUM_SYSTEM_PORTS 2
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#define CONFIG_UART_NUM_EXTRA_PORTS 1
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#define CONFIG_UART_NUM_PORTS \
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(CONFIG_UART_NUM_SYSTEM_PORTS + CONFIG_UART_NUM_EXTRA_PORTS)
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#define CONFIG_UART_CONSOLE_INDEX 0
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#define CONFIG_UART_CONSOLE_BAUDRATE 115200
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#define CONFIG_UART_CONSOLE_IRQ IRQ_UART0
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#define CONFIG_UART_CONSOLE_INT_PRI 3
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#define CONFIG_UART_CONSOLE_REGS PERIPH_ADDR_BASE_UART0
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#define EXC_FROM_IRQ(irq) ((irq) + 16)
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#define VECTOR_FROM_IRQ(irq) EXC_FROM_IRQ(irq)
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#define VECTOR_ADDR(vector) ((uint32_t *)((int)vector << 2))
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/*
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* Device drivers utilize the macros PLB_BYTE_REG_WRITE() and
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* PLB_BYTE_REG_READ() to access byte-wide registers on the processor
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* local bus (PLB), as opposed to a PCI bus, for example. Boards are
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* expected to provide implementations of these macros.
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*/
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static inline void __plbByteRegWrite(unsigned char data, unsigned char *pAddr)
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{
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*pAddr = data;
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}
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#define PLB_BYTE_REG_WRITE(data, address) \
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__plbByteRegWrite((unsigned char)data, (unsigned char *)address)
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static inline unsigned char __plbByteRegRead(unsigned char *pAddr)
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{
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return *pAddr;
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}
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#define PLB_BYTE_REG_READ(address) __plbByteRegRead((unsigned char *)address)
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#endif /* !_ASMLANGUAGE */
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#endif /* _BOARD__H_ */
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