124 lines
3.6 KiB
C
124 lines
3.6 KiB
C
/* exc.h - exception/interrupt context helpers for Cortex-M CPUs */
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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Exception/interrupt context helpers.
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*/
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#ifndef _ARM_CORTEXM_ISR__H_
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#define _ARM_CORTEXM_ISR__H_
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#include <nanokernel/cpu.h>
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#ifdef _ASMLANGUAGE
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/* nothing */
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#else
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/*******************************************************************************
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*
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* _IpsrGet - obtain value of IPSR register
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*
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* Obtain and return current value of IPSR register.
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*
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* RETURNS: the contents of the IPSR register
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*
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* \NOMANUAL
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*/
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#if defined(__GNUC__)
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static ALWAYS_INLINE uint32_t _IpsrGet(void)
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{
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uint32_t vector;
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__asm__ volatile("mrs %0, IPSR\n\t" : "=r"(vector));
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return vector;
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}
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#elif defined(__DCC__)
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__asm volatile uint32_t _IpsrGet(void)
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{
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% !"r0" mrs r0, IPSR
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}
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#endif
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/*******************************************************************************
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*
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* _IsInIsr - find out if running in an ISR context
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*
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* The current executing vector is found in the IPSR register. We consider the
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* IRQs (exception 16 and up), and the PendSV and SYSTICK exceptions, to be
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* interrupts. Taking a fault within an exception is also considered in
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* interrupt context.
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*
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* RETURNS: 1 if in ISR, 0 if not.
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*
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* \NOMANUAL
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*/
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static ALWAYS_INLINE int _IsInIsr(void)
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{
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uint32_t vector = _IpsrGet();
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/* IRQs + PendSV + SYSTICK are interrupts */
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return (vector > 13) || (vector && _ScbIsNestedExc());
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}
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/*******************************************************************************
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* _ExcSetup - setup system exceptions
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*
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* Set exception priorities to conform with the BASEPRI locking mechanism.
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* Set PendSV priority to lowest possible.
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*
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* Enable fault exceptions.
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*
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* RETURNS: N/A
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*
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* \NOMANUAL
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*/
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static ALWAYS_INLINE void _ExcSetup(void)
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{
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_ScbExcPrioSet(_EXC_PENDSV, _EXC_PRIO(0xff));
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_ScbExcPrioSet(_EXC_SVC, _EXC_PRIO(0x01));
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_ScbExcPrioSet(_EXC_MPU_FAULT, _EXC_PRIO(0x01));
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_ScbExcPrioSet(_EXC_BUS_FAULT, _EXC_PRIO(0x01));
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_ScbExcPrioSet(_EXC_USAGE_FAULT, _EXC_PRIO(0x01));
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_ScbUsageFaultEnable();
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_ScbBusFaultEnable();
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_ScbMemFaultEnable();
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}
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#endif /* _ASMLANGUAGE */
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#endif /* _ARM_CORTEXM_ISR__H_ */
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