218 lines
6.5 KiB
C
218 lines
6.5 KiB
C
/* board.h - board configuration macros for the fsl_frdm_k64f BSP */
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/*
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This header file is used to specify and describe board-level aspects for the
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'fsl_frdm_k64f' BSP.
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*/
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#ifndef _BOARD__H_
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#define _BOARD__H_
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#include <misc/util.h>
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#define SRAM_SIZE KB(192) /* 64K in code space (ignored) + 192K in SRAM space \
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*/
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/* default system clock */
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#define SYSCLK_DEFAULT_IOSC_HZ MHZ(120)
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/* address bases */
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#define PERIPH_ADDR_BASE_MPU 0x4000D000 /* Memory Protection Unit */
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#define PERIPH_ADDR_BASE_PCR 0x40049000 /* Port and pin Configuration */
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#define PERIPH_ADDR_BASE_SIM 0x40047000 /* System Integration module */
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#define PERIPH_ADDR_BASE_WDOG 0x40052000 /* Watchdog Timer module */
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#define PERIPH_ADDR_BASE_MCG 0x40064000 /* Multipurpose Clock Generator */
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#define PERIPH_ADDR_BASE_OSC 0x40065000 /* Oscillator module */
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#define PERIPH_ADDR_BASE_UART0 0x4006A000 /* UART0 connected to SDA USB */
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#define PERIPH_ADDR_BASE_UART1 0x4006B000 /* not supported */
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#define PERIPH_ADDR_BASE_UART2 0x4006C000 /* not supported */
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#define PERIPH_ADDR_BASE_UART3 0x4006D000 /* not supported */
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#define PERIPH_ADDR_BASE_UART4 0x400EA000 /* not supported - for Bluetooth */
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#define PERIPH_ADDR_BASE_PMC 0x4007D000 /* Power Mgt Controller module */
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/* IRQs */
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#define IRQ_DMA_CHAN0 0
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#define IRQ_DMA_CHAN1 1
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#define IRQ_DMA_CHAN2 2
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#define IRQ_DMA_CHAN3 3
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#define IRQ_DMA_CHAN4 4
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#define IRQ_DMA_CHAN5 5
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#define IRQ_DMA_CHAN6 6
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#define IRQ_DMA_CHAN7 7
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#define IRQ_DMA_CHAN8 8
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#define IRQ_DMA_CHAN9 9
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#define IRQ_DMA_CHAN10 10
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#define IRQ_DMA_CHAN11 11
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#define IRQ_DMA_CHAN12 12
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#define IRQ_DMA_CHAN13 13
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#define IRQ_DMA_CHAN14 14
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#define IRQ_DMA_CHAN15 15
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#define IRQ_DMA_ERR 16
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#define IRQ_MCM 17
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#define IRQ_FLASH_CMD 18
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#define IRQ_FLASH_COLLISION 19
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#define IRQ_LOW_VOLTAGE 20
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#define IRQ_LOW_LEAKAGE 21
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#define IRQ_WDOG_OR_EVM 22
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#define IRQ_RAND_NUM_GEN 23
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#define IRQ_I2C0 24
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#define IRQ_I2C1 25
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#define IRQ_SPI0 26
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#define IRQ_SPI1 27
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#define IRQ_I2S0_TX 28
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#define IRQ_I2S0_RX 29
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#define IRQ_RESERVED0 30
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#define IRQ_UART0_STATUS 31
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#define IRQ_UART0_ERROR 32
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#define IRQ_UART1_STATUS 33
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#define IRQ_UART1_ERROR 34
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#define IRQ_UART2_STATUS 35
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#define IRQ_UART2_ERROR 36
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#define IRQ_UART3_STATUS 37
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#define IRQ_UART3_ERROR 38
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#define IRQ_ADC0 39
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#define IRQ_CMP0 40
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#define IRQ_CMP1 41
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#define IRQ_FTM0 42
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#define IRQ_FTM1 43
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#define IRQ_FTM2 44
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#define IRQ_CMT 45
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#define IRQ_RTC_ALARM 46
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#define IRQ_RTC_SEC 47
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#define IRQ_TIMER0 48
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#define IRQ_TIMER1 49
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#define IRQ_TIMER2 50
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#define IRQ_TIMER3 51
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#define IRQ_PDB 52
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#define IRQ_USB_OTG 53
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#define IRQ_USB_CHARGE 54
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#define IRQ_RESERVED1 55
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#define IRQ_DAC0 56
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#define IRQ_MCG 57
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#define IRQ_LOW_PWR_TIMER 58
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#define IRQ_GPIO_PORTA 59
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#define IRQ_GPIO_PORTB 60
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#define IRQ_GPIO_PORTC 61
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#define IRQ_GPIO_PORTD 62
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#define IRQ_GPIO_PORTE 63
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#define IRQ_SOFTWARE 64
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#define IRQ_SPI2 65
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#define IRQ_UART4_STATUS 66
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#define IRQ_UART4_ERROR 67
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#define IRQ_RESERVED2 68 /* IRQ_UART5_STATUS - UART5 not implemented */
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#define IRQ_RESERVED3 69 /* IRQ_UART5_ERROR - UART5 not implemented */
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#define IRQ_CMP2 70
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#define IRQ_FTM3 71
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#define IRQ_DAC1 72
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#define IRQ_ADC1 73
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#define IRQ_I2C2 74
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#define IRQ_CAN0_MSG_BUF 75
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#define IRQ_CAN0_BUS_OFF 76
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#define IRQ_CAN0_ERROR 77
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#define IRQ_CAN0_TX_WARN 78
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#define IRQ_CAN0_RX_WARN 79
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#define IRQ_CAN0_WAKEUP 80
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#define IRQ_SDHC 81
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#define IRQ_ETH_IEEE1588_TMR 82
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#define IRQ_ETH_TX 83
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#define IRQ_ETH_RX 84
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#define IRQ_ETH_ERR_MISC 85
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#ifndef _ASMLANGUAGE
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#include <misc/util.h>
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#include <drivers/rand32.h>
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/*
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* UART configuration settings
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*/
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#include <drivers/k20Pcr.h>
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#define CONFIG_UART_NUM_SYSTEM_PORTS 1
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#define CONFIG_UART_NUM_EXTRA_PORTS 0
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#define CONFIG_UART_NUM_PORTS \
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(CONFIG_UART_NUM_SYSTEM_PORTS + CONFIG_UART_NUM_EXTRA_PORTS)
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#define CONFIG_UART_CONSOLE_INDEX 0
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#define CONFIG_UART_CONSOLE_PORT PCR_PORT_B
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#define CONFIG_UART_CONSOLE_PORT_RX_PIN 16
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#define CONFIG_UART_CONSOLE_PORT_TX_PIN 17
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#define CONFIG_UART_CONSOLE_PORT_MUX_FUNC PCR_MUX_ALT3
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#define CONFIG_UART_CONSOLE_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ
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#define CONFIG_UART_CONSOLE_BAUDRATE 115200
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#define CONFIG_UART_CONSOLE_REGS PERIPH_ADDR_BASE_UART0
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#define CONFIG_UART_CONSOLE_IRQ IRQ_UART0_STATUS
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#define CONFIG_UART_CONSOLE_INT_PRI 3
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#define EXC_FROM_IRQ(irq) ((irq) + 16)
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#define VECTOR_FROM_IRQ(irq) EXC_FROM_IRQ(irq)
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#define VECTOR_ADDR(vector) ((uint32_t *)((int)vector << 2))
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/*
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* Device drivers utilize the macros PLB_BYTE_REG_WRITE() and
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* PLB_BYTE_REG_READ() to access byte-wide registers on the processor
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* local bus (PLB), as opposed to a PCI bus, for example. Boards are
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* expected to provide implementations of these macros.
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*/
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static inline void __plbByteRegWrite(unsigned char data, unsigned char *pAddr)
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{
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*pAddr = data;
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}
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#define PLB_BYTE_REG_WRITE(data, address) \
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__plbByteRegWrite((unsigned char)data, (unsigned char *)address)
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static inline unsigned char __plbByteRegRead(unsigned char *pAddr)
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{
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return *pAddr;
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}
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#define PLB_BYTE_REG_READ(address) __plbByteRegRead((unsigned char *)address)
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#endif /* !_ASMLANGUAGE */
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#endif /* _BOARD__H_ */
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