224 lines
7.2 KiB
ArmAsm
224 lines
7.2 KiB
ArmAsm
/* swap.s - thread context switching for ARM Cortex-M */
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This module implements the routines necessary for thread context switching
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on ARM Cortex-M3/M4 CPUs.
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*/
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#define _ASMLANGUAGE
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#include <nanok.h>
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#include <offsets.h>
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#include <toolchain.h>
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#include <nanokernel/cpu.h>
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_ASM_FILE_PROLOGUE
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GTEXT(_Swap)
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GTEXT(__svc)
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GTEXT(__pendsv)
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GDATA(_NanoKernel)
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/*******************************************************************************
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*
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* __pendsv - PendSV exception handler, handling context switches
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*
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* The PendSV exception is the only context in the system that can perform
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* context switching. When an execution context finds out it has to switch
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* contexts, it pends the PendSV exception.
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*
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* When PendSV is pended, the decision that a context switch must happen has
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* already been taken. In other words, when __pendsv() runs, we *know* we have
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* to swap *something*.
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*
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* The scheduling algorithm is simple: schedule the head of the runnable FIBER
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* context list, which is represented by _NanoKernel.fiber. If there are no
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* runnable FIBER contexts, then schedule the TASK context represented by
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* _NanoKernel.task. The _NanoKernel.task field will never be NULL.
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*/
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SECTION_FUNC(TEXT, __pendsv)
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_GDB_STUB_EXC_ENTRY
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/* load _Nanokernel into r1 and current tCCS into r2 */
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ldr r1, =_NanoKernel
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ldr r2, [r1, #__tNANO_current_OFFSET]
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/* addr of callee-saved regs in CCS in r0 */
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add r0, r2, #__tCCS_preempReg_OFFSET
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/* save callee-saved + psp in CCS */
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mrs ip, PSP
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stmia r0, {v1-v8, ip}
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/*
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* Prepare to clear PendSV with interrupts unlocked, but
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* don't clear it yet. PendSV must not be cleared until
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* the new thread is context-switched in since all decisions
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* to pend PendSV have been taken with the current kernel
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* state and this is what we're handling currently.
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*/
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ldr ip, =_SCS_ICSR
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ldr r3, =_SCS_ICSR_UNPENDSV
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/* protect the kernel state while we play with the thread lists */
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movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
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msr BASEPRI, r0
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/* find out incoming context (fiber or task) */
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/* is there a fiber ready ? */
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ldr r2, [r1, #__tNANO_fiber_OFFSET]
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cmp r2, #0
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/*
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* if so, remove fiber from list
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* else, the task is the thread we're switching in
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*/
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itte ne
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ldrne.w r0, [r2, #__tCCS_link_OFFSET] /* then */
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strne.w r0, [r1, #__tNANO_fiber_OFFSET] /* then */
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ldreq.w r2, [r1, #__tNANO_task_OFFSET] /* else */
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/* r2 contains the new thread */
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ldr r0, [r2, #__tCCS_flags_OFFSET]
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str r0, [r1, #__tNANO_flags_OFFSET]
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str r2, [r1, #__tNANO_current_OFFSET]
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/*
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* Clear PendSV so that if another interrupt comes in and
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* decides, with the new kernel state baseed on the new thread
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* being context-switched in, that it needs to reschedules, it
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* will take, but that previously pended PendSVs do not take,
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* since they were based on the previous kernel state and this
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* has been handled.
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*/
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/* _SCS_ICSR is still in ip and _SCS_ICSR_UNPENDSV in r3 */
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str r3, [ip, #0]
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/* restore BASEPRI for the incoming thread */
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ldr r0, [r2, #__tCCS_basepri_OFFSET]
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mov ip, #0
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str ip, [r2, #__tCCS_basepri_OFFSET]
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msr BASEPRI, r0
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/* load callee-saved + psp from CCS */
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add r0, r2, #__tCCS_preempReg_OFFSET
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ldmia r0, {v1-v8, ip}
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msr PSP, ip
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_GDB_STUB_EXC_EXIT
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/* exc return */
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bx lr
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/*******************************************************************************
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*
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* __svc - service call handler
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*
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* The service call (svc) is only used in _Swap() to enter handler mode so we
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* can go through the PendSV exception to perform a context switch.
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*
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* RETURNS: N/A
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*/
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SECTION_FUNC(TEXT, __svc)
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_GDB_STUB_EXC_ENTRY
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/*
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* Unlock interrupts:
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* - in a SVC call, so protected against context switches
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* - allow PendSV, since it's running at prio 0xff
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*/
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eors.n r0, r0
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msr BASEPRI, r0
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/* set PENDSV bit, pending the PendSV exception */
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ldr r1, =_SCS_ICSR
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ldr r2, =_SCS_ICSR_PENDSV
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str r2, [r1, #0]
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_GDB_STUB_EXC_EXIT
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/* handler mode exit, to PendSV */
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bx lr
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/*******************************************************************************
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*
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* _Swap - initiate a cooperative context switch
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*
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* The _Swap() routine is invoked by various nanokernel services to effect
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* a cooperative context context switch. Prior to invoking _Swap(), the caller
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* disables interrupts via irq_lock() and the return 'key' is passed as a
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* parameter to _Swap(). The 'key' actually represents the BASEPRI register
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* prior to disabling interrupts via the BASEPRI mechanism.
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*
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* _Swap() itself does not do much.
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*
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* It simply stores the intlock key (the BASEPRI value) parameter into
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* current->basepri, and then triggers a service call exception (svc) to setup
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* the PendSV exception, which does the heavy lifting of context switching.
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* This is the only place we have to save BASEPRI since the other paths to
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* __pendsv all come from handling an interrupt, which means we know the
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* interrupts were not locked: in that case the BASEPRI value is 0.
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*
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* Given that _Swap() is called to effect a cooperative context context switch,
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* only the caller-saved integer registers need to be saved in the tCCS of the
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* outgoing context. This is all performed by the hardware, which stores it in
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* its exception stack frame, created when handling the svc exception.
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*
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* RETURNS: may contain a return value setup by a call to fiberRtnValueSet()
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*
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* C function prototype:
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*
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* unsigned int _Swap (unsigned int basepri);
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*
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*/
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SECTION_FUNC(TEXT, _Swap)
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ldr r1, =_NanoKernel
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ldr r2, [r1, #__tNANO_current_OFFSET]
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str r0, [r2, #__tCCS_basepri_OFFSET]
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svc #0
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/* r0 contains the return value if needed */
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bx lr
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