112 lines
3.9 KiB
ArmAsm
112 lines
3.9 KiB
ArmAsm
/* isr_wrapper.s - ARM CORTEX-M3 wrapper for ISRs with parameter */
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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Wrapper installed in vector table for handling dynamic interrupts that accept
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a parameter.
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*/
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#define _ASMLANGUAGE
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#include <offsets.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <sw_isr_table.h>
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#include <nanok.h>
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#include <nanokernel/cpu.h>
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_ASM_FILE_PROLOGUE
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GDATA(_IsrTable)
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GTEXT(_IsrWrapper)
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GTEXT(_IntExit)
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/*******************************************************************************
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*
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* _IsrWrapper - wrapper around ISRs when inserted in software ISR table
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*
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* When inserted in the vector table, _IsrWrapper() demuxes the ISR table using
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* the running interrupt number as the index, and invokes the registered ISR
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* with its correspoding argument. When returning from the ISR, it determines
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* if a context switch needs to happen (see documentation for __pendsv()) and
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* pends the PendSV exception if so: the latter will perform the context switch
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* itself.
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*
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* RETURNS: N/A
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*/
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SECTION_FUNC(TEXT, _IsrWrapper)
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_GDB_STUB_EXC_ENTRY
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push {lr} /* lr is now the first item on the stack */
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#ifdef CONFIG_ADVANCED_POWER_MANAGEMENT
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/*
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* All interrupts are disabled when handling idle wakeup.
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* For tickless idle, this ensures that the calculation and programming of
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* the device for the next timer deadline is not interrupted.
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* For non-tickless idle, this ensures that the clearing of the kernel idle
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* state is not interrupted.
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* In each case, _SysPowerSaveIdleExit is called with interrupts disabled.
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*/
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cpsid i /* PRIMASK = 1 */
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/* is this a wakeup from idle ? */
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ldr r2, =_NanoKernel
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ldr r0, [r2, #__tNANO_idle_OFFSET] /* requested idle duration, in ticks */
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cmp r0, #0
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ittt ne
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movne r1, #0
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strne r1, [r2, #__tNANO_idle_OFFSET] /* clear kernel idle state */
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blxne _SysPowerSaveIdleExit
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cpsie i /* re-enable interrupts (PRIMASK = 0) */
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#endif /* CONFIG_ADVANCED_POWER_MANAGEMENT */
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mrs r0, IPSR /* get exception number */
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sub r0, r0, #16 /* get IRQ number */
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lsl r0, r0, #3 /* table is 8-byte wide */
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ldr r1, =_IsrTable
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add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
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* in thumb mode */
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ldmia r1,{r0,r3} /* arg in r0, ISR in r3 */
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blx r3 /* call ISR */
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pop {lr}
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/* exception return is done in _IntExit(), including _GDB_STUB_EXC_EXIT */
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b _IntExit
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