67 lines
2.3 KiB
C
67 lines
2.3 KiB
C
/* cache.h - cache helper functions (ARC) */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* DESCRIPTION
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* This file contains private nanokernel structures definitions and various
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* other definitions for the ARCv2 processor architecture.
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*/
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#ifndef _ARCV2_CACHE__H_
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#define _ARCV2_CACHE__H_
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#include <nanokernel/cpu.h>
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#ifndef _ASMLANGUAGE
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#define CACHE_ENABLE 0x00
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#define CACHE_DISABLE 0x01
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#define CACHE_DIRECT 0x00
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#define CACHE_CACHE_CONTROLLED 0x20
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/*
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* _icache_enable - sets the I-cache
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*
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* Enables cache and sets the direct access.
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*/
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static ALWAYS_INLINE void _icache_setup(void)
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{
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uint32_t icache_config = (
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CACHE_DIRECT | /* direct mapping (one-way assoc.) */
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CACHE_ENABLE /* i-cache enabled */
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);
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_arc_v2_aux_reg_write(_ARC_V2_IC_CTRL, icache_config);
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}
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#endif /* _ASMLANGUAGE */
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#endif /* _ARCV2_CACHE__H_ */
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