203 lines
6.0 KiB
ArmAsm
203 lines
6.0 KiB
ArmAsm
/* swap.s - thread context switching */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This module implements the routines necessary for thread context switching
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on ARCv2 CPUs.
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See isr_wrapper.s for details.
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*/
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#define _ASMLANGUAGE
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#include <nanok.h>
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#include <offsets.h>
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#include <toolchain.h>
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#include <nanokernel/cpu.h>
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#include <v2/irq.h>
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#include "swap_macros.h"
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GTEXT(_Swap)
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GDATA(_NanoKernel)
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/*******************************************************************************
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*
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* _Swap - initiate a cooperative context switch
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*
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* The _Swap() routine is invoked by various nanokernel services to effect
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* a cooperative context context switch. Prior to invoking _Swap(), the caller
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* disables interrupts via nanoCpuIntLock() and the return 'key' is passed as a
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* parameter to _Swap(). The key is in fact the value stored in the register
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* operand of a CLRI instruction.
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*
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* It stores the intlock key parameter into current->intlock_key.
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* Given that _Swap() is called to effect a cooperative context context switch,
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* the caller-saved integer registers are saved on the stack by the function
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* call preamble to _Swap(). This creates a custom stack frame that will be
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* popped when returning from _Swap(), but is not suitable for handling a return
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* from an exception. Thus, the fact that the thread is pending because of a
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* cooperative call to _Swap() has to be recorded via the _CAUSE_COOP code in
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* the relinquish_cause of the context's tCCS. The _IrqExit()/_FirqExit() code
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* will take care of doing the right thing to restore the thread status.
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*
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* When _Swap() is invoked, we know the decision to perform a context switch or
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* not has already been taken and a context switch must happen.
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*
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* RETURNS: may contain a return value setup by a call to fiberRtnValueSet()
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*
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* C function prototype:
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*
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* unsigned int _Swap (unsigned int key);
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*
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*/
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SECTION_FUNC(TEXT, _Swap)
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/* interrupts are locked, interrupt key is in r0 */
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mov r1, _NanoKernel
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ld r2, [r1, __tNANO_current_OFFSET]
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/* save intlock key */
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st r0, [r2, __tCCS_intlock_key_OFFSET]
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st _CAUSE_COOP, [r2, __tCCS_relinquish_cause_OFFSET]
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/*
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* Save status32 and blink on the stack before the callee-saved registers.
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* This is the same layout as the start of an IRQ stack frame.
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*/
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lr r3, [_ARC_V2_STATUS32]
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push_s r3
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push_s blink
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_save_callee_saved_regs
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ld r2, [r1, __tNANO_fiber_OFFSET]
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breq.nd r2, 0, _swap_to_the_task
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.balign 4
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_swap_to_a_fiber:
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ld r3, [r2, __tCCS_link_OFFSET]
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b.d _finish_swapping_to_context /* always execute delay slot */
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st r3, [r1, __tNANO_fiber_OFFSET] /* delay slot */
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.balign 4
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_swap_to_the_task:
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ld r2, [r1, __tNANO_task_OFFSET]
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/* fall through */
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.balign 4
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_finish_swapping_to_context:
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/* entering here, r2 contains the new current context */
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#if 0
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/* don't save flags in tNANO: slower, error-prone, and might not even give
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* a speed boost where it's supposed to */
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ld r3, [r2, __tCCS_flags_OFFSET]
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st r3, [r1, __tNANO_flags_OFFSET]
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#endif
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/* XXX - can be moved to delay slot of _CAUSE_RIRQ ? */
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st r2, [r1, __tNANO_current_OFFSET]
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_load_callee_saved_regs
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ld r3, [r2, __tCCS_relinquish_cause_OFFSET]
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breq.nd r3, _CAUSE_RIRQ, _swap_return_from_rirq
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nop
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breq.nd r3, _CAUSE_FIRQ, _swap_return_from_firq
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nop
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/* fall through to _swap_return_from_coop */
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.balign 4
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_swap_return_from_coop:
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ld r1, [r2, __tCCS_intlock_key_OFFSET]
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st 0, [r2, __tCCS_intlock_key_OFFSET]
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ld r0, [r2, __tCCS_return_value_OFFSET]
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/*
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* Adjust the stack here in case we go to _return_from_exc: this allows
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* keeping handling both coop and irq cases in _return_from_exc without
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* adding extra logic.
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*/
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add_s sp, sp, 8
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lr ilink, [_ARC_V2_STATUS32]
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bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
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sub_s sp, sp, 8
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pop_s blink /* pc into blink */
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pop_s r3 /* status32 into r3 */
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kflag r3 /* write status32 */
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j_s.d [blink] /* always execute delay slot */
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seti r1 /* delay slot */
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.balign 4
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_swap_return_from_rirq:
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_swap_return_from_firq:
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_pop_irq_stack_frame
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lr ilink, [_ARC_V2_STATUS32]
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bbit1 ilink, _ARC_V2_STATUS32_AE_BIT, _return_from_exc
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ld ilink, [sp, -4] /* status32 into ilink */
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and ilink, ilink, 0x7ffffffe // keep interrupts disabled until seti
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kflag ilink
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ld ilink, [sp, -8] /* pc into ilink */
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j.d [ilink]
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seti (_ARC_V2_DEF_IRQ_LEVEL | (1 << 4))
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.balign 4
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_return_from_exc:
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/* put the return address to eret */
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ld ilink, [sp, -8] /* pc into ilink */
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sr ilink, [_ARC_V2_ERET]
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/* put status32 into estatus */
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ld ilink, [sp, -4] /* status32 into ilink */
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sr ilink, [_ARC_V2_ERSTATUS]
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rtie
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