241 lines
8.5 KiB
ArmAsm
241 lines
8.5 KiB
ArmAsm
/* isr_wrapper.s - wrapper around ISRs with logic for context switching */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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Wrapper installed in vector table for handling dynamic interrupts that accept
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a parameter.
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*/
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#define _ASMLANGUAGE
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#include <offsets.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <sw_isr_table.h>
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#include <nanok.h>
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#include <nanokernel/cpu.h>
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GTEXT(_isr_enter)
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GTEXT(_isr_demux)
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/*
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The symbols in this file are not real functions, and neither are
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_rirq_enter/_firq_enter: they are jump points.
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The flow is the following:
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ISR -> _isr_enter -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
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+ -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
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Context switch explanation:
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The context switch code is spread in these files:
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isr_wrapper.s, swap.s, swap_macros.s, fast_irq.s, regular_irq.s
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IRQ stack frame layout:
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high address
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status32
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pc
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[jli_base]
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[ldi_base]
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[ei_base]
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lp_count
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lp_start
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lp_end
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blink
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r13
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...
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sp -> r0
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low address
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[registers not taken into account in the current implementation]
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The context switch code adopts this standard so that it is easier to follow:
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- r1 contains _NanoKernel ASAP and is not overwritten over the lifespan of
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the functions.
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- r2 contains _NanoKernel.current ASAP, and the incoming thread when we
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transition from outgoing context to incoming context
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Not loading _NanoKernel into r0 allows loading _NanoKernel without stomping on
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the parameter in r0 in _Swap().
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ARCv2 processor have two kinds of interrupts: fast (FIRQ) and regular. The
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official documentation calls them regular interrupts IRQ, but the internals of
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the kernel calls them RIRQ to differentiate with the 'irq' subsystem, which is
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the interrupt API/layer of abstraction.
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FIRQs can be used to allow ISRs to run without having to save any context,
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since they work with a second register bank. However, they can be somewhat more
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limited than RIRQs since the register bank does not copy every possible
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register that is needed to implement all available instructions: an example is
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that the 'loop' registers (lp_count, lp_end, lp_start) are not present in the
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second bank. The kernel thus takes upon itself to save these extra registers,
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if the FIRQ is made known to the kernel. It is possible for a FIRQ to operate
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outside of the kernel, but care must be taken to only use instructions that
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only use the banked registers. RIRQs must always use the kernel's interrupt
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entry and exit mechanisms.
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The kernel is able to handle transitions to and from FIRQ, RIRQ and threads
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(fibers/task). The contexts are saved 'lazily': the minimum amount of work is
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done upfront, and the rest is done when needed:
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o RIRQ
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All needed regisers to run C code in the ISR are saved automatically
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on the outgoing context's stack: loop, status32, pc, and the caller-
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saved GPRs. That stack frame layout is pre-determined. If returning
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to a fiber, the stack is popped and no registers have to be saved by
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the kernel. If a context switch is required, the callee-saved GPRs
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are then saved in the context control structure (CCS).
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o FIRQ
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First, a FIRQ can be interrupting a lower-priority RIRQ: if this is the case,
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the first does not take a scheduling decision and leaves it the RIRQ to
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handle. The limits the amount of code that has to run at interrupt-level.
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GPRs are banked, loop registers are saved in a global structure upon
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interrupt entry. If returning to a fiber, loop are poppped and the
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CPU switches back to bank 0 for the GPRs. If a context switch is
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needed, at this point only are all the registers saved. First, a
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stack frame with the same layout as the automatic RIRQ one is created
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and then the callee-saved GPRs are saved in the CCS. status32_p0 and
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ilink are saved in this case, not status32 and pc.
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To create the stack frame, the FIRQ handling code must first go back to using
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bank0 of registers, since that is where the register containing the exiting
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thread are saved. Care must be taken not to touch any register before saving
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them: the only one usable at that point is the stack pointer.
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o coop
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When a coop context switch is done, the callee-saved registers are
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saved in the CCS. The other GPRs do not have to be saved, since the
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compiler has already placed them on the stack.
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For restoring the contexts, there are six cases. In all cases, the
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callee-saved registers of the incoming thread have to be restored. Then, there
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are specifics for each case:
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From coop:
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o to coop
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Restore interrupt lock level and normal function call return.
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o to any irq
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The incoming interrupted thread has an IRQ stack frame containing the
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caller-saved registers that has to be popped. status32 has to be restored,
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then we jump to the interrupted instruction.
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From FIRQ:
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The processor is back to using bank0, not bank1 anymore, because it had to
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save the outgoing context from bank0, and not has to load the incoming one
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into bank0.
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o to coop
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The address of the returning instruction from _Swap() is loaded in ilink and
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the saved status32 in status32_p0, taking care to adjust the interrupt lock
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state desired in status32_p0. The return value is put in r0.
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o to any irq
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The IRQ has saved the caller-saved registers in a stack frame, which must be
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popped, and statu32 and pc loaded in status32_p0 and ilink.
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From RIRQ:
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o to coop
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The interrupt return mechanism in the processor expects a stack frame, but
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the outgoing context did not create one. A fake one is created here, with
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only the relevant values filled in: pc, status32 and the return value in r0.
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There is a discrepancy between the ABI from the ARCv2 docs, including the
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way the processor pushes GPRs in pairs in the IRQ stack frame, and the ABI
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GCC uses. r13 should be a callee-saved register, but GCC treats it as
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caller-saved. This means that the processor pushes it in the stack frame
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along with r12, but the compiler does not save it before entering a
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function. So, it is saved as part of the callee-saved registers, and
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restored there, but the processor restores it *a second time* when popping
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the IRQ stack frame. Thus, the correct value must also be put in the fake
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stack frame when returning to a thread that context switched out
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cooperatively.
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o to any irq
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Both types of IRQs already have an IRQ stack frame: simply return from
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interrupt.
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*/
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SECTION_FUNC(TEXT, _isr_enter)
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lr r0, [_ARC_V2_AUX_IRQ_ACT]
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ffs r0, r0
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cmp r0, 0
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mov.z r3, _firq_exit
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mov.z r2, _firq_enter
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mov.nz r3, _rirq_exit
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mov.nz r2, _rirq_enter
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j_s.nd [r2]
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/* when getting here, r3 contains the interrupt exit stub to call */
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SECTION_FUNC(TEXT, _isr_demux)
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push_s r3
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lr r0, [_ARC_V2_ICAUSE]
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sub r0, r0, 16
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mov r1, _IsrTable
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add3 r0, r1, r0 /* table entries are 8-bytes wide */
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ld r1, [r0, 4] /* ISR into r1 */
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jl_s.d [r1]
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ld_s r0, [r0] /* delay slot: ISR parameter into r0 */
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/* back from ISR, jump to exit stub */
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pop_s r3
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j_s.nd [r3]
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nop
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