108 lines
3.5 KiB
ArmAsm
108 lines
3.5 KiB
ArmAsm
/* fault_s.s - fault handlers for ARCv2 */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* DESCRIPTION
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* Fault handlers for ARCv2 processors.
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*/
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#define _ASMLANGUAGE
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#include <toolchain.h>
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#include <sections.h>
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#include <nanokernel/cpu.h>
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#include "swap_macros.h"
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GTEXT(_Fault)
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GTEXT(__reset)
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GTEXT(__memory_error)
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GTEXT(__instruction_error)
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GTEXT(__ev_machine_check)
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GTEXT(__ev_tlb_miss_i)
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GTEXT(__ev_tlb_miss_d)
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GTEXT(__ev_prot_v)
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GTEXT(__ev_privilege_v)
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GTEXT(__ev_swi)
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GTEXT(__ev_trap)
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GTEXT(__ev_extension)
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GTEXT(__ev_div_zero)
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GTEXT(__ev_dc_error)
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GTEXT(__ev_maligned)
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GDATA(_firq_stack)
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SECTION_VAR(BSS, saved_stack_pointer)
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.word 0
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/*
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* __fault - fault handler installed in the fault and reserved vectors
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*/
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SECTION_SUBSEC_FUNC(TEXT,__fault,__memory_error)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__instruction_error)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_machine_check)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_tlb_miss_i)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_tlb_miss_d)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_prot_v)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_privilege_v)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_swi)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_trap)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_extension)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_div_zero)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_dc_error)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__ev_maligned)
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/*
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* Before invoking exception handler, the kernel switches to an exception
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* stack, which is really the FIRQ stack, to save the faulting thread's
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* registers. It can use the FIRQ stack because it knows it is unused
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* since it is save to assume that if an exception has happened in FIRQ
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* handler, the problem is fatal and all the kernel can do is just print
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* a diagnostic message and halt.
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*/
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st sp, [saved_stack_pointer]
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mov_s sp, _firq_stack
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add sp, sp, CONFIG_FIRQ_STACK_SIZE
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/* save caller saved registers */
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_create_irq_stack_frame
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jl _Fault
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/* if _Fault returns, restore the registers */
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_pop_irq_stack_frame
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/* now restore the stack */
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ld sp,[saved_stack_pointer]
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rtie
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