285 lines
7.8 KiB
ArmAsm
285 lines
7.8 KiB
ArmAsm
/* fast_irq.s - handling of transitions to-and-from fast IRQs (FIRQ) */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This module implements the code for handling entry to and exit from Fast IRQs.
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See isr_wrapper.s for details.
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*/
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#define _ASMLANGUAGE
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#include <nanok.h>
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#include <offsets.h>
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#include <toolchain.h>
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#include <nanokernel/cpu.h>
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#include "swap_macros.h"
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GTEXT(_firq_enter)
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GTEXT(_firq_exit)
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GTEXT(_firq_stack_setup)
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GDATA(_firq_stack)
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SECTION_VAR(NOINIT, _firq_stack)
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.space CONFIG_FIRQ_STACK_SIZE
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/*******************************************************************************
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*
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* _firq_enter - work to be done before handing control to a FIRQ ISR
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*
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* The processor switches to a second register bank so registers from the
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* current bank do not have to be preserved yet. The only issue is the LP_START/
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* LP_COUNT/LP_END registers, which are not banked.
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*
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* If all FIRQ ISRs are programmed such that there are no use of the LP
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* registers (ie. no LPcc instruction), then the kernel can be configured to
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* remove the use of _firq_enter().
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*
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* When entering a FIRQ, interrupts might as well be locked: the processor is
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* running at its highest priority, and cannot be preempted by anything.
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*
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* Assumption by _isr_demux: r3 is untouched by _firq_enter.
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*
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* RETURNS: N/A
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*/
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SECTION_FUNC(TEXT, _firq_enter)
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#ifndef CONFIG_FIRQ_NO_LPCC
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/*
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* Unlike the rest of context switching code, r2 is loaded with something
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* else than 'current' in this routine: this is to preserve r3 so that it
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* does not have to be fetched again in _isr_demux.
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*/
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/* save LP_START/LP_COUNT/LP_END variables */
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mov_s r1, _NanoKernel
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/* cannot store lp_count directly to memory */
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mov r2, lp_count
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st lp_count, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
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lr r2, [_ARC_V2_LP_START]
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st r2, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_start_OFFSET]
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lr r2, [_ARC_V2_LP_END]
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st r2, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_end_OFFSET]
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#endif
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j @_isr_demux
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/*******************************************************************************
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*
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* _firq_exit - work to be done exiting a FIRQ
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*
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* RETURNS: N/A
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*/
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SECTION_FUNC(TEXT, _firq_exit)
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mov_s r1, _NanoKernel
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ld_s r2, [r1, __tNANO_current_OFFSET]
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#ifndef CONFIG_FIRQ_NO_LPCC
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/* assumption: r1 contains _NanoKernel, r2 contains the current thread */
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/* restore LP_START/LP_COUNT/LP_END variables */
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/* cannot load lp_count from memory */
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ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_count_OFFSET]
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mov lp_count, r3
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ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_start_OFFSET]
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sr r3, [_ARC_V2_LP_START]
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ld r3, [r1, __tNANO_firq_regs_OFFSET + __tFirqRegs_lp_end_OFFSET]
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sr r3, [_ARC_V2_LP_END]
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/* exiting here: r1/r2 unchanged, r0/r3 destroyed */
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#endif
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#if CONFIG_NUM_IRQ_PRIO_LEVELS > 1
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/* check if we're a nested interrupt: if so, let the interrupted interrupt
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* handle the reschedule */
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lr r3, [_ARC_V2_AUX_IRQ_ACT]
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/* Viper on ARCv2 always runs in kernel mode, so assume bit31 [U] in
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* AUX_IRQ_ACT is always 0: if the contents of AUX_IRQ_ACT is not 1, it
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* means that another bit is set so an interrupt was interrupted.
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*/
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breq.nd r3, 1, _check_if_current_is_the_task
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rtie
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#endif
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.balign 4
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_check_if_current_is_the_task:
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ld r0, [r2, __tCCS_flags_OFFSET]
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and.f r0, r0, PREEMPTIBLE
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bnz.nd _check_if_a_fiber_is_ready
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rtie
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.balign 4
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_check_if_a_fiber_is_ready:
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ld r0, [r1, __tNANO_fiber_OFFSET] /* incoming fiber in r0 */
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brne.nd r0, 0, _firq_reschedule
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rtie
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.balign 4
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_firq_reschedule:
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/*
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* We know there is no interrupted interrupt of lower priority at this
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* point, so when switching back to register bank 0, it will contain the
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* registers from the interrupted thread.
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*/
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/* chose register bank #0 */
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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kflag r0
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/* we're back on the outgoing thread's stack */
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_create_irq_stack_frame
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/*
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* In a FIRQ, STATUS32 of the outgoing thread is in STATUS32_P0 and the
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* PC in ILINK: save them in status32/pc respectively.
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*/
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lr r0, [_ARC_V2_STATUS32_P0]
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st_s r0, [sp, __tISF_status32_OFFSET]
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st ilink, [sp, __tISF_pc_OFFSET] /* ilink into pc */
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mov_s r1, _NanoKernel
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ld r2, [r1, __tNANO_current_OFFSET]
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_save_callee_saved_regs
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st _CAUSE_FIRQ, [r2, __tCCS_relinquish_cause_OFFSET]
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ld r2, [r1, __tNANO_fiber_OFFSET]
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st r2, [r1, __tNANO_current_OFFSET]
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ld r3, [r2, __tCCS_link_OFFSET]
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st r3, [r1, __tNANO_fiber_OFFSET]
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/*
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* _load_callee_saved_regs expects incoming thread in r2.
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* _load_callee_saved_regs restores the stack pointer.
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*/
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_load_callee_saved_regs
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ld r3, [r2, __tCCS_relinquish_cause_OFFSET]
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breq.nd r3, _CAUSE_RIRQ, _firq_return_from_rirq
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nop
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breq.nd r3, _CAUSE_FIRQ, _firq_return_from_firq
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nop
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/* fall through */
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.balign 4
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_firq_return_from_coop:
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ld r3, [r2, __tCCS_intlock_key_OFFSET]
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st 0, [r2, __tCCS_intlock_key_OFFSET]
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/* pc into ilink */
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pop_s r0
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mov ilink, r0
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pop_s r0 /* status32 into r0 */
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/*
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* There are only two interrupt lock states: locked and unlocked. When
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* entering _Swap(), they are always locked, so the IE bit is unset in
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* status32. If the incoming thread had them locked recursively, it means
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* that the IE bit should stay unset. The only time the bit has to change
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* is if they were not locked recursively.
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*/
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and.f r3, r3, (1 << 4)
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or.nz r0, r0, _ARC_V2_STATUS32_IE
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sr r0, [_ARC_V2_STATUS32_P0]
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ld r0, [r2, __tCCS_return_value_OFFSET]
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rtie
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.balign 4
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_firq_return_from_rirq:
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_firq_return_from_firq:
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_pop_irq_stack_frame
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ld ilink, [sp, -4] /* status32 into ilink */
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sr ilink, [_ARC_V2_STATUS32_P0]
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ld ilink, [sp, -8] /* pc into ilink */
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/* fall through to rtie instruction */
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.balign 4
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_firq_no_reschedule:
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/* LP registers are already restored, just switch back to bank 0 */
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rtie
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/*******************************************************************************
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*
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* _firq_stack_setup - install the FIRQ stack in register bank 1
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*
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* RETURNS: N/A
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*/
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SECTION_FUNC(TEXT, _firq_stack_setup)
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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or r0, r0, _ARC_V2_STATUS32_RB(1)
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kflag r0
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mov sp, _firq_stack
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add sp, sp, CONFIG_FIRQ_STACK_SIZE
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/*
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* We have to reload r0 here, because it is bank1 r0 which contains
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* garbage, not bank0 r0 containing the previous value of status32.
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*/
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lr r0, [_ARC_V2_STATUS32]
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and r0, r0, ~_ARC_V2_STATUS32_RB(7)
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kflag r0
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j_s.nd [blink]
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