69 lines
2.8 KiB
C
69 lines
2.8 KiB
C
/* Customized table mapping between kernel xtregset and GDB register cache.
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Copyright (c) 2007-2010 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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typedef struct {
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int gdb_regnum;
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int gdb_offset;
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int ptrace_cp_offset;
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int ptrace_offset;
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int size;
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int coproc;
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int dbnum;
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char* name
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;} xtensa_regtable_t;
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#define XTENSA_ELF_XTREG_SIZE 152
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const xtensa_regtable_t xtensa_regmap_table[] = {
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/* gnum,gofs,cpofs,ofs,siz,cp, dbnum, name */
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{ 46, 184, 24, 24, 4, -1, 0x0204, "br" },
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{ 47, 188, 28, 28, 4, -1, 0x020c, "scompare1" },
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{ 48, 192, 0, 0, 4, -1, 0x0210, "acclo" },
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{ 49, 196, 4, 4, 4, -1, 0x0211, "acchi" },
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{ 50, 200, 8, 8, 4, -1, 0x0220, "m0" },
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{ 51, 204, 12, 12, 4, -1, 0x0221, "m1" },
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{ 52, 208, 16, 16, 4, -1, 0x0222, "m2" },
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{ 53, 212, 20, 20, 4, -1, 0x0223, "m3" },
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{ 54, 216, 24, 56, 8, 1, 0x0060, "aep0" },
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{ 55, 224, 32, 64, 8, 1, 0x0061, "aep1" },
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{ 56, 232, 40, 72, 8, 1, 0x0062, "aep2" },
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{ 57, 240, 48, 80, 8, 1, 0x0063, "aep3" },
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{ 58, 248, 56, 88, 8, 1, 0x0064, "aep4" },
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{ 59, 256, 64, 96, 8, 1, 0x0065, "aep5" },
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{ 60, 264, 72, 104, 8, 1, 0x0066, "aep6" },
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{ 61, 272, 80, 112, 8, 1, 0x0067, "aep7" },
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{ 62, 280, 88, 120, 8, 1, 0x0068, "aeq0" },
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{ 63, 288, 96, 128, 8, 1, 0x0069, "aeq1" },
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{ 64, 296, 104, 136, 8, 1, 0x006a, "aeq2" },
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{ 65, 304, 112, 144, 8, 1, 0x006b, "aeq3" },
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{ 66, 312, 0, 32, 4, 1, 0x03f0, "ae_ovf_sar" },
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{ 67, 316, 4, 36, 4, 1, 0x03f1, "ae_bithead" },
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{ 68, 320, 8, 40, 4, 1, 0x03f2, "ae_ts_fts_bu_bp" },
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{ 69, 324, 12, 44, 4, 1, 0x03f3, "ae_sd_no" },
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{ 70, 328, 16, 48, 4, 1, 0x03f6, "ae_cbegin0" },
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{ 71, 332, 20, 52, 4, 1, 0x03f7, "ae_cend0" },
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{ 0 }
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};
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