315 lines
19 KiB
C
315 lines
19 KiB
C
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
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Copyright (c) 2003-2017 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#define XTENSA_CONFIG_VERSION 0x60
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#include "defs.h"
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#include "xtensa-config.h"
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#include "xtensa-tdep.h"
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/* Masked registers. */
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xtensa_reg_mask_t xtensa_submask0[] = { { 46, 0, 1 } };
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const xtensa_mask_t xtensa_mask0 = { 1, xtensa_submask0 };
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xtensa_reg_mask_t xtensa_submask1[] = { { 46, 1, 1 } };
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const xtensa_mask_t xtensa_mask1 = { 1, xtensa_submask1 };
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xtensa_reg_mask_t xtensa_submask2[] = { { 46, 2, 1 } };
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const xtensa_mask_t xtensa_mask2 = { 1, xtensa_submask2 };
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xtensa_reg_mask_t xtensa_submask3[] = { { 46, 3, 1 } };
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const xtensa_mask_t xtensa_mask3 = { 1, xtensa_submask3 };
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xtensa_reg_mask_t xtensa_submask4[] = { { 46, 4, 1 } };
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const xtensa_mask_t xtensa_mask4 = { 1, xtensa_submask4 };
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xtensa_reg_mask_t xtensa_submask5[] = { { 46, 5, 1 } };
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const xtensa_mask_t xtensa_mask5 = { 1, xtensa_submask5 };
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xtensa_reg_mask_t xtensa_submask6[] = { { 46, 6, 1 } };
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const xtensa_mask_t xtensa_mask6 = { 1, xtensa_submask6 };
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xtensa_reg_mask_t xtensa_submask7[] = { { 46, 7, 1 } };
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const xtensa_mask_t xtensa_mask7 = { 1, xtensa_submask7 };
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xtensa_reg_mask_t xtensa_submask8[] = { { 46, 8, 1 } };
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const xtensa_mask_t xtensa_mask8 = { 1, xtensa_submask8 };
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xtensa_reg_mask_t xtensa_submask9[] = { { 46, 9, 1 } };
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const xtensa_mask_t xtensa_mask9 = { 1, xtensa_submask9 };
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xtensa_reg_mask_t xtensa_submask10[] = { { 46, 10, 1 } };
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const xtensa_mask_t xtensa_mask10 = { 1, xtensa_submask10 };
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xtensa_reg_mask_t xtensa_submask11[] = { { 46, 11, 1 } };
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const xtensa_mask_t xtensa_mask11 = { 1, xtensa_submask11 };
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xtensa_reg_mask_t xtensa_submask12[] = { { 46, 12, 1 } };
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const xtensa_mask_t xtensa_mask12 = { 1, xtensa_submask12 };
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xtensa_reg_mask_t xtensa_submask13[] = { { 46, 13, 1 } };
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const xtensa_mask_t xtensa_mask13 = { 1, xtensa_submask13 };
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xtensa_reg_mask_t xtensa_submask14[] = { { 46, 14, 1 } };
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const xtensa_mask_t xtensa_mask14 = { 1, xtensa_submask14 };
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xtensa_reg_mask_t xtensa_submask15[] = { { 46, 15, 1 } };
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const xtensa_mask_t xtensa_mask15 = { 1, xtensa_submask15 };
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xtensa_reg_mask_t xtensa_submask16[] = { { 44, 0, 4 } };
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const xtensa_mask_t xtensa_mask16 = { 1, xtensa_submask16 };
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xtensa_reg_mask_t xtensa_submask17[] = { { 44, 5, 1 } };
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const xtensa_mask_t xtensa_mask17 = { 1, xtensa_submask17 };
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xtensa_reg_mask_t xtensa_submask18[] = { { 44, 18, 1 } };
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const xtensa_mask_t xtensa_mask18 = { 1, xtensa_submask18 };
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xtensa_reg_mask_t xtensa_submask19[] = { { 44, 4, 1 } };
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const xtensa_mask_t xtensa_mask19 = { 1, xtensa_submask19 };
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xtensa_reg_mask_t xtensa_submask20[] = { { 44, 16, 2 } };
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const xtensa_mask_t xtensa_mask20 = { 1, xtensa_submask20 };
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xtensa_reg_mask_t xtensa_submask21[] = { { 44, 8, 4 } };
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const xtensa_mask_t xtensa_mask21 = { 1, xtensa_submask21 };
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xtensa_reg_mask_t xtensa_submask22[] = { { 48, 0, 32 }, { 49, 0, 8 } };
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const xtensa_mask_t xtensa_mask22 = { 2, xtensa_submask22 };
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xtensa_reg_mask_t xtensa_submask23[] = { { 109, 8, 4 } };
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const xtensa_mask_t xtensa_mask23 = { 1, xtensa_submask23 };
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xtensa_reg_mask_t xtensa_submask24[] = { { 66, 6, 1 } };
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const xtensa_mask_t xtensa_mask24 = { 1, xtensa_submask24 };
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xtensa_reg_mask_t xtensa_submask25[] = { { 66, 0, 6 } };
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const xtensa_mask_t xtensa_mask25 = { 1, xtensa_submask25 };
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xtensa_reg_mask_t xtensa_submask26[] = { { 68, 0, 4 } };
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const xtensa_mask_t xtensa_mask26 = { 1, xtensa_submask26 };
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xtensa_reg_mask_t xtensa_submask27[] = { { 68, 4, 4 } };
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const xtensa_mask_t xtensa_mask27 = { 1, xtensa_submask27 };
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xtensa_reg_mask_t xtensa_submask28[] = { { 68, 12, 4 } };
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const xtensa_mask_t xtensa_mask28 = { 1, xtensa_submask28 };
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xtensa_reg_mask_t xtensa_submask29[] = { { 68, 8, 4 } };
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const xtensa_mask_t xtensa_mask29 = { 1, xtensa_submask29 };
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xtensa_reg_mask_t xtensa_submask30[] = { { 69, 0, 27 } };
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const xtensa_mask_t xtensa_mask30 = { 1, xtensa_submask30 };
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xtensa_reg_mask_t xtensa_submask31[] = { { 69, 27, 1 } };
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const xtensa_mask_t xtensa_mask31 = { 1, xtensa_submask31 };
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/* Register map. */
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static xtensa_register_t rmap[] =
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{
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/* idx ofs bi sz al targno flags cp typ group name */
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XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
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XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
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XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
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XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
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XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
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XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
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XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
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XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
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XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
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XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
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XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
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XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
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XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
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XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
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XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
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XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
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XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
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XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
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XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
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XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
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XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
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XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
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XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
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XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
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XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
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XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
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XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
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XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
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XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
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XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
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XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
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XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
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XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
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XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
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XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
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XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
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XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
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XTREG( 37,148, 8, 4, 4,0x0228,0x0006,-2, 2,0x1100,prefctl, 0,0,0,0,0,0)
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XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
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XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
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XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
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XTREG( 41,164,32, 4, 4,0x02b0,0x0002,-2, 2,0x0000,sr176, 0,0,0,0,0,0)
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XTREG( 42,168,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
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XTREG( 43,172,32, 4, 4,0x02d0,0x0002,-2, 2,0x0000,sr208, 0,0,0,0,0,0)
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XTREG( 44,176,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
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XTREG( 45,180,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
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XTREG( 46,184,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
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XTREG( 47,188,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
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XTREG( 48,192,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
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XTREG( 49,196, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
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XTREG( 50,200,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
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XTREG( 51,204,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
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XTREG( 52,208,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
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XTREG( 53,212,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
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XTREG( 54,216,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
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"03:04:84:b2","03:04:84:a7",0,0,0,0)
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XTREG( 55,224,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
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"03:04:94:b2","03:04:94:a7",0,0,0,0)
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XTREG( 56,232,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
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"03:04:a4:b2","03:04:a4:a7",0,0,0,0)
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XTREG( 57,240,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
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"03:04:b4:b2","03:04:b4:a7",0,0,0,0)
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XTREG( 58,248,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
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"03:04:c4:b2","03:04:c4:a7",0,0,0,0)
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XTREG( 59,256,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
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"03:04:d4:b2","03:04:d4:a7",0,0,0,0)
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XTREG( 60,264,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
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"03:04:e4:b2","03:04:e4:a7",0,0,0,0)
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XTREG( 61,272,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
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"03:04:f4:b2","03:04:f4:a7",0,0,0,0)
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XTREG( 62,280,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
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"03:04:04:c3","03:04:04:c1",0,0,0,0)
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XTREG( 63,288,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
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"03:04:14:c3","03:04:44:c1",0,0,0,0)
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XTREG( 64,296,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
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"03:04:24:c3","03:04:84:c1",0,0,0,0)
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XTREG( 65,304,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
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"03:04:34:c3","03:04:c4:c1",0,0,0,0)
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XTREG( 66,312, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
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XTREG( 67,316,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
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XTREG( 68,320,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
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XTREG( 69,324,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
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XTREG( 70,328,32, 4, 4,0x03f6,0x0006, 1, 3,0x0110,ae_cbegin0, 0,0,0,0,0,0)
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XTREG( 71,332,32, 4, 4,0x03f7,0x0006, 1, 3,0x0110,ae_cend0, 0,0,0,0,0,0)
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XTREG( 72,336, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
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XTREG( 73,340, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
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XTREG( 74,344,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
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XTREG( 75,348,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
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XTREG( 76,352,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
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XTREG( 77,356,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
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XTREG( 78,360,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
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XTREG( 79,364,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
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XTREG( 80,368,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
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XTREG( 81,372,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
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XTREG( 82,376,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
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XTREG( 83,380,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
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XTREG( 84,384,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
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XTREG( 85,388,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
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XTREG( 86,392,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
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XTREG( 87,396,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
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XTREG( 88,400,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
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XTREG( 89,404,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
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XTREG( 90,408,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
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XTREG( 91,412,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
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XTREG( 92,416,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
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XTREG( 93,420,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
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XTREG( 94,424,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
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|
XTREG( 95,428,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
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|
XTREG( 96,432,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
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|
XTREG( 97,436,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
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|
XTREG( 98,440,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
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|
XTREG( 99,444,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
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|
XTREG(100,448,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
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|
XTREG(101,452,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
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|
XTREG(102,456, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
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|
XTREG(103,460,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
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|
XTREG(104,464,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
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|
XTREG(105,468,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
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|
XTREG(106,472,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
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|
XTREG(107,476,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
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|
XTREG(108,480, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
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|
XTREG(109,484,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
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|
XTREG(110,488,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
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|
XTREG(111,492,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
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|
XTREG(112,496,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
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|
XTREG(113,500, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
|
XTREG(114,504,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
|
XTREG(115,508,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
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|
XTREG(116,512,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
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|
XTREG(117,516,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
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|
XTREG(118,520,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
|
|
XTREG(119,524,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
|
|
XTREG(120,528,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
|
|
XTREG(121,532,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
|
|
XTREG(122,536,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
|
|
XTREG(123,540,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
|
|
XTREG(124,544,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
|
|
XTREG(125,548,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
|
|
XTREG(126,552,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
|
|
XTREG(127,556,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
|
|
XTREG(128,560,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
|
|
XTREG(129,564,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
|
|
XTREG(130,568,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
|
|
XTREG(131,572,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
|
|
XTREG(132,576,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
|
|
XTREG(133,580,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
|
|
XTREG(134,584, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
|
|
0,0,&xtensa_mask0,0,0,0)
|
|
XTREG(135,585, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
|
|
0,0,&xtensa_mask1,0,0,0)
|
|
XTREG(136,586, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
|
|
0,0,&xtensa_mask2,0,0,0)
|
|
XTREG(137,587, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
|
|
0,0,&xtensa_mask3,0,0,0)
|
|
XTREG(138,588, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
|
|
0,0,&xtensa_mask4,0,0,0)
|
|
XTREG(139,589, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
|
|
0,0,&xtensa_mask5,0,0,0)
|
|
XTREG(140,590, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
|
|
0,0,&xtensa_mask6,0,0,0)
|
|
XTREG(141,591, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
|
|
0,0,&xtensa_mask7,0,0,0)
|
|
XTREG(142,592, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
|
|
0,0,&xtensa_mask8,0,0,0)
|
|
XTREG(143,593, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
|
|
0,0,&xtensa_mask9,0,0,0)
|
|
XTREG(144,594, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
|
|
0,0,&xtensa_mask10,0,0,0)
|
|
XTREG(145,595, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
|
|
0,0,&xtensa_mask11,0,0,0)
|
|
XTREG(146,596, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
|
|
0,0,&xtensa_mask12,0,0,0)
|
|
XTREG(147,597, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
|
|
0,0,&xtensa_mask13,0,0,0)
|
|
XTREG(148,598, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
|
|
0,0,&xtensa_mask14,0,0,0)
|
|
XTREG(149,599, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
|
|
0,0,&xtensa_mask15,0,0,0)
|
|
XTREG(150,600, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
|
|
0,0,&xtensa_mask16,0,0,0)
|
|
XTREG(151,604, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
|
|
0,0,&xtensa_mask17,0,0,0)
|
|
XTREG(152,608, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
|
|
0,0,&xtensa_mask18,0,0,0)
|
|
XTREG(153,612, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,psexcm,
|
|
0,0,&xtensa_mask19,0,0,0)
|
|
XTREG(154,616, 2, 4, 4,0x200c,0x0006,-2, 6,0x1010,pscallinc,
|
|
0,0,&xtensa_mask20,0,0,0)
|
|
XTREG(155,620, 4, 4, 4,0x200d,0x0006,-2, 6,0x1010,psowb,
|
|
0,0,&xtensa_mask21,0,0,0)
|
|
XTREG(156,624,40, 8, 4,0x200e,0x0006,-2, 6,0x1010,acc,
|
|
0,0,&xtensa_mask22,0,0,0)
|
|
XTREG(157,632, 4, 4, 4,0x2013,0x0006,-2, 6,0x1010,dbnum,
|
|
0,0,&xtensa_mask23,0,0,0)
|
|
XTREG(158,636, 1, 4, 4,0x2014,0x0006, 1, 5,0x1010,ae_overflow,
|
|
0,0,&xtensa_mask24,0,0,0)
|
|
XTREG(159,640, 6, 4, 4,0x2015,0x0006, 1, 5,0x1010,ae_sar,
|
|
0,0,&xtensa_mask25,0,0,0)
|
|
XTREG(160,644, 4, 4, 4,0x2016,0x0006, 1, 5,0x1010,ae_bitptr,
|
|
0,0,&xtensa_mask26,0,0,0)
|
|
XTREG(161,648, 4, 4, 4,0x2017,0x0006, 1, 5,0x1010,ae_bitsused,
|
|
0,0,&xtensa_mask27,0,0,0)
|
|
XTREG(162,652, 4, 4, 4,0x2018,0x0006, 1, 5,0x1010,ae_tablesize,
|
|
0,0,&xtensa_mask28,0,0,0)
|
|
XTREG(163,656, 4, 4, 4,0x2019,0x0006, 1, 5,0x1010,ae_first_ts,
|
|
0,0,&xtensa_mask29,0,0,0)
|
|
XTREG(164,660,27, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_nextoffset,
|
|
0,0,&xtensa_mask30,0,0,0)
|
|
XTREG_END
|
|
};
|
|
|
|
xtensa_gdbarch_tdep xtensa_tdep (rmap);
|