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sdk-ng/patches-arc64/binutils/0001-Add-ARC64-support.patch

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From 9fb4053152aa67c25eb37488a95847474e46bfd1 Mon Sep 17 00:00:00 2001
From: Alexey Brodkin <abrodkin@synopsys.com>
Date: Tue, 27 Apr 2021 19:38:21 +0300
Subject: [PATCH] Add ARC64 support
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
---
bfd/Makefile.am | 17 +-
bfd/Makefile.in | 18 +-
bfd/arc-got.h | 92 +-
bfd/arc-plt.c | 121 +
bfd/arc-plt.def | 43 +-
bfd/arc-plt.h | 93 +-
bfd/archures.c | 2 +
bfd/bfd-in2.h | 23 +
bfd/config.bfd | 18 +-
bfd/configure | 5 +-
bfd/configure.ac | 5 +-
bfd/cpu-arc.c | 58 +-
bfd/elf32-arc.c | 3158 ---
bfd/elflink.c | 2 +-
bfd/elfnn-arc.c | 3556 +++
bfd/libbfd.h | 20 +
bfd/reloc.c | 40 +
bfd/targets.c | 8 +-
binutils/readelf.c | 44 +-
config.sub | 2 +-
gas/config/tc-arc.c | 471 +-
gas/config/tc-arc.h | 56 +-
gas/configure | 2 +-
gas/configure.ac | 2 +-
gas/configure.tgt | 4 +-
gas/testsuite/gas/arc/arc.exp | 4 +
gas/testsuite/gas/arc64/arc64.exp | 24 +
gas/testsuite/gas/arc64/lddl.d | 46 +
gas/testsuite/gas/arc64/lddl.s | 54 +
gas/testsuite/gas/arc64/stdl.d | 32 +
gas/testsuite/gas/arc64/stdl.s | 35 +
gas/write.c | 12 +-
include/elf/arc-cpu.def | 2 +
include/elf/arc-reloc.def | 147 +-
include/elf/arc.h | 1 +
include/elf/common.h | 3 +
include/opcode/arc-attrs.h | 4 +-
include/opcode/arc-func.h | 87 +-
include/opcode/arc.h | 124 +-
ld/Makefile.am | 4 +
ld/Makefile.in | 6 +
ld/configure.tgt | 14 +-
ld/emulparams/arc64linux.sh | 22 +
ld/emulparams/arcelf.sh | 1 +
ld/emulparams/arcv2elf.sh | 2 +-
ld/emulparams/arcv2elfx.sh | 2 +-
ld/emulparams/elf64arc.sh | 15 +
ld/emultempl/arcelf.em | 40 +
ld/testsuite/ld-arc/arc.exp | 3 +-
ld/testsuite/ld-arc/hiddso.d | 6 +
ld/testsuite/ld-arc/hiddsoA.s | 3 +
ld/testsuite/ld-arc/hiddsoB.s | 6 +
ld/testsuite/ld-arc/nps-1a.d | 2 +-
ld/testsuite/ld-arc/nps-1b.d | 2 +-
ld/testsuite/ld-arc/relax-call-1.d | 20 +
ld/testsuite/ld-arc/relax-call-1.s | 14 +
ld/testsuite/ld-arc/relax-call-2.d | 27 +
ld/testsuite/ld-arc/relax-call-2.s | 23 +
ld/testsuite/ld-arc/relax-call-3.d | 36 +
ld/testsuite/ld-arc/relax-call-3.s | 27 +
ld/testsuite/ld-arc/relax-local-pic.d | 4 +-
ld/testsuite/ld-arc/weakhid.s | 13 +
ld/testsuite/ld-arc/weakhiddso.d | 29 +
.../ld-arc64/arcv3_64-reloc-near-exe.dd | 29 +
.../ld-arc64/arcv3_64-reloc-near-so.dd | 23 +
ld/testsuite/ld-arc64/arcv3_64-reloc-near.s | 11 +
ld/testsuite/ld-arc64/arcv3_64.exp | 36 +
opcodes/arc-dis.c | 107 +-
opcodes/arc-ext-tbl.h | 15 +
opcodes/arc-fxi.h | 60 +
opcodes/arc-opc.c | 424 +-
opcodes/arc64-fp-tbl.h | 479 +
opcodes/arc64-tbl.h | 18828 ++++++++++++++++
73 files changed, 25172 insertions(+), 3596 deletions(-)
create mode 100644 bfd/arc-plt.c
delete mode 100644 bfd/elf32-arc.c
create mode 100644 bfd/elfnn-arc.c
create mode 100644 gas/testsuite/gas/arc64/arc64.exp
create mode 100644 gas/testsuite/gas/arc64/lddl.d
create mode 100644 gas/testsuite/gas/arc64/lddl.s
create mode 100644 gas/testsuite/gas/arc64/stdl.d
create mode 100644 gas/testsuite/gas/arc64/stdl.s
create mode 100644 ld/emulparams/arc64linux.sh
create mode 100644 ld/emulparams/elf64arc.sh
create mode 100644 ld/emultempl/arcelf.em
create mode 100644 ld/testsuite/ld-arc/hiddso.d
create mode 100644 ld/testsuite/ld-arc/hiddsoA.s
create mode 100644 ld/testsuite/ld-arc/hiddsoB.s
create mode 100644 ld/testsuite/ld-arc/relax-call-1.d
create mode 100644 ld/testsuite/ld-arc/relax-call-1.s
create mode 100644 ld/testsuite/ld-arc/relax-call-2.d
create mode 100644 ld/testsuite/ld-arc/relax-call-2.s
create mode 100644 ld/testsuite/ld-arc/relax-call-3.d
create mode 100644 ld/testsuite/ld-arc/relax-call-3.s
create mode 100644 ld/testsuite/ld-arc/weakhid.s
create mode 100644 ld/testsuite/ld-arc/weakhiddso.d
create mode 100644 ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd
create mode 100644 ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd
create mode 100644 ld/testsuite/ld-arc64/arcv3_64-reloc-near.s
create mode 100644 ld/testsuite/ld-arc64/arcv3_64.exp
create mode 100644 opcodes/arc64-fp-tbl.h
create mode 100644 opcodes/arc64-tbl.h
diff --git a/bfd/Makefile.am b/bfd/Makefile.am
index c88c4480001..ae292e0442e 100644
--- a/bfd/Makefile.am
+++ b/bfd/Makefile.am
@@ -291,7 +291,6 @@ BFD32_BACKENDS = \
elf-vxworks.lo \
elf.lo \
elf32-am33lin.lo \
- elf32-arc.lo \
elf32-arm.lo \
elf32-avr.lo \
elf32-bfin.lo \
@@ -426,7 +425,6 @@ BFD32_BACKENDS_CFILES = \
elf-vxworks.c \
elf.c \
elf32-am33lin.c \
- elf32-arc.c \
elf32-arm.c \
elf32-avr.c \
elf32-bfin.c \
@@ -537,6 +535,8 @@ BFD64_BACKENDS = \
elf32-aarch64.lo \
elf64-aarch64.lo \
elfxx-aarch64.lo \
+ elf32-arc.lo \
+ elf64-arc.lo \
aix5ppc-core.lo \
aout64.lo \
coff-alpha.lo \
@@ -668,6 +668,7 @@ SOURCE_CFILES = \
BUILD_CFILES = \
elf32-aarch64.c elf64-aarch64.c \
+ elf32-arc.c elf64-arc.c \
elf32-ia64.c elf64-ia64.c \
elf32-riscv.c elf64-riscv.c \
peigen.c pepigen.c pex64igen.c
@@ -838,6 +839,18 @@ elf64-aarch64.c : elfnn-aarch64.c
echo "#line 1 \"elfnn-aarch64.c\"" > $@
$(SED) -e s/NN/64/g < $< >> $@
+elf32-arc.c : elfnn-arc.c
+ rm -f elf32-arc.c
+ echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > elf32-arc.new
+ sed -e s/NN/32/g < $(srcdir)/elfnn-arc.c >> elf32-arc.new
+ mv -f elf32-arc.new elf32-arc.c
+
+elf64-arc.c : elfnn-arc.c
+ rm -f elf64-arc.c
+ echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > elf64-arc.new
+ sed -e s/NN/64/g < $(srcdir)/elfnn-arc.c >> elf64-arc.new
+ mv -f elf64-arc.new elf64-arc.c
+
elf32-ia64.c : elfnn-ia64.c
echo "#line 1 \"elfnn-ia64.c\"" > $@
$(SED) -e s/NN/32/g < $< >> $@
diff --git a/bfd/Makefile.in b/bfd/Makefile.in
index d0d14c6ab32..f8a7f610199 100644
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -716,7 +716,6 @@ BFD32_BACKENDS = \
elf-vxworks.lo \
elf.lo \
elf32-am33lin.lo \
- elf32-arc.lo \
elf32-arm.lo \
elf32-avr.lo \
elf32-bfin.lo \
@@ -851,7 +850,6 @@ BFD32_BACKENDS_CFILES = \
elf-vxworks.c \
elf.c \
elf32-am33lin.c \
- elf32-arc.c \
elf32-arm.c \
elf32-avr.c \
elf32-bfin.c \
@@ -963,6 +961,8 @@ BFD64_BACKENDS = \
elf32-aarch64.lo \
elf64-aarch64.lo \
elfxx-aarch64.lo \
+ elf32-arc.lo \
+ elf64-arc.lo \
aix5ppc-core.lo \
aout64.lo \
coff-alpha.lo \
@@ -1093,6 +1093,7 @@ SOURCE_CFILES = \
BUILD_CFILES = \
elf32-aarch64.c elf64-aarch64.c \
+ elf32-arc.c elf64-arc.c \
elf32-ia64.c elf64-ia64.c \
elf32-riscv.c elf64-riscv.c \
peigen.c pepigen.c pex64igen.c
@@ -1491,6 +1492,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-aarch64.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-alpha.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-bpf.Plo@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-arc.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-gen.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ia64-vms.Plo@am__quote@
@@ -1969,6 +1971,18 @@ elf64-aarch64.c : elfnn-aarch64.c
echo "#line 1 \"elfnn-aarch64.c\"" > $@
$(SED) -e s/NN/64/g < $< >> $@
+elf32-arc.c : elfnn-arc.c
+ rm -f elf32-arc.c
+ echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > elf32-arc.new
+ sed -e s/NN/32/g < $(srcdir)/elfnn-arc.c >> elf32-arc.new
+ mv -f elf32-arc.new elf32-arc.c
+
+elf64-arc.c : elfnn-arc.c
+ rm -f elf64-arc.c
+ echo "#line 1 \"$(srcdir)/elfnn-arc.c\"" > elf64-arc.new
+ sed -e s/NN/64/g < $(srcdir)/elfnn-arc.c >> elf64-arc.new
+ mv -f elf64-arc.new elf64-arc.c
+
elf32-ia64.c : elfnn-ia64.c
echo "#line 1 \"elfnn-ia64.c\"" > $@
$(SED) -e s/NN/32/g < $< >> $@
diff --git a/bfd/arc-got.h b/bfd/arc-got.h
index 8053a2d9077..f45de1e5265 100644
--- a/bfd/arc-got.h
+++ b/bfd/arc-got.h
@@ -22,7 +22,21 @@
#ifndef ARC_GOT_H
#define ARC_GOT_H
+#if ARCH_SIZE == 32
#define TCB_SIZE (8)
+#else
+#define TCB_SIZE (16)
+#endif
+
+#if ARCH_SIZE == 32
+#define GOT_ENTRY_SIZE 4
+#define write_in_got(A, B, C) bfd_put_32 (A, B, C)
+#define read_from_got(A, B) bfd_get_32 (A, B)
+#else
+#define GOT_ENTRY_SIZE 8
+#define write_in_got(A, B, C) bfd_put_64 (A, B, C)
+#define read_from_got(A, B) bfd_get_64 (A, B)
+#endif
#define align_power(addr, align) \
(((addr) + ((bfd_vma) 1 << (align)) - 1) & (-((bfd_vma) 1 << (align))))
@@ -201,7 +215,7 @@ arc_got_entry_type_for_reloc (reloc_howto_type *howto)
{ \
if (COND_FOR_RELOC) \
{ \
- htab->srel##SECNAME->size += sizeof (Elf32_External_Rela); \
+ htab->srel##SECNAME->size += RELA_SIZE; \
ARC_DEBUG ("arc_info: Added reloc space in " \
#SECNAME " section at " __FILE__ \
":%d for symbol %s\n", \
@@ -211,7 +225,7 @@ arc_got_entry_type_for_reloc (reloc_howto_type *howto)
if (H->dynindx == -1 && !H->forced_local) \
if (! bfd_elf_link_record_dynamic_symbol (info, H)) \
return FALSE; \
- htab->s##SECNAME->size += 4; \
+ htab->s##SECNAME->size += GOT_ENTRY_SIZE; \
} \
static bfd_boolean
@@ -335,27 +349,27 @@ relocate_fix_got_relocs_for_got_info (struct got_entry ** list_p,
if (h == NULL || h->forced_local
|| !elf_hash_table (info)->dynamic_sections_created)
{
- bfd_put_32 (output_bfd,
- sym_value - sec_vma
- + (elf_hash_table (info)->dynamic_sections_created
- ? 0
- : (align_power (0,
- tls_sec->alignment_power))),
- htab->sgot->contents + entry->offset
- + (entry->existing_entries == TLS_GOT_MOD_AND_OFF
- ? 4 : 0));
+ write_in_got (output_bfd,
+ sym_value - sec_vma
+ + (elf_hash_table (info)->dynamic_sections_created
+ ? 0
+ : (align_power (0,
+ tls_sec->alignment_power))),
+ htab->sgot->contents + entry->offset
+ + (entry->existing_entries == TLS_GOT_MOD_AND_OFF
+ ? GOT_ENTRY_SIZE : 0));
ARC_DEBUG ("arc_info: FIXED -> %s value = %#lx "
- "@ %lx, for symbol %s\n",
- (entry->type == GOT_TLS_GD ? "GOT_TLS_GD" :
- "GOT_TLS_IE"),
- (long) (sym_value - sec_vma),
- (long) (htab->sgot->output_section->vma
- + htab->sgot->output_offset
- + entry->offset
- + (entry->existing_entries == TLS_GOT_MOD_AND_OFF
- ? 4 : 0)),
- symbol_name);
+ "@ %lx, for symbol %s\n",
+ (entry->type == GOT_TLS_GD ? "GOT_TLS_GD" :
+ "GOT_TLS_IE"),
+ (long) (sym_value - sec_vma),
+ (long) (htab->sgot->output_section->vma
+ + htab->sgot->output_offset
+ + entry->offset
+ + (entry->existing_entries == TLS_GOT_MOD_AND_OFF
+ ? GOT_ENTRY_SIZE : 0)),
+ symbol_name);
}
}
break;
@@ -366,26 +380,26 @@ relocate_fix_got_relocs_for_got_info (struct got_entry ** list_p,
bfd_vma ATTRIBUTE_UNUSED sec_vma
= tls_sec->output_section->vma;
- bfd_put_32 (output_bfd,
- sym_value - sec_vma
- + (elf_hash_table (info)->dynamic_sections_created
- ? 0
- : (align_power (TCB_SIZE,
- tls_sec->alignment_power))),
- htab->sgot->contents + entry->offset
- + (entry->existing_entries == TLS_GOT_MOD_AND_OFF
- ? 4 : 0));
+ write_in_got (output_bfd,
+ sym_value - sec_vma
+ + (elf_hash_table (info)->dynamic_sections_created
+ ? 0
+ : (align_power (TCB_SIZE,
+ tls_sec->alignment_power))),
+ htab->sgot->contents + entry->offset
+ + (entry->existing_entries == TLS_GOT_MOD_AND_OFF
+ ? GOT_ENTRY_SIZE : 0));
ARC_DEBUG ("arc_info: FIXED -> %s value = %#lx "
"@ %p, for symbol %s\n",
(entry->type == GOT_TLS_GD ? "GOT_TLS_GD" :
"GOT_TLS_IE"),
(long) (sym_value - sec_vma),
- (long) (htab->sgot->output_section->vma
+ (void *) (htab->sgot->output_section->vma
+ htab->sgot->output_offset
+ entry->offset
+ (entry->existing_entries == TLS_GOT_MOD_AND_OFF
- ? 4 : 0)),
+ ? GOT_ENTRY_SIZE : 0)),
symbol_name);
}
break;
@@ -408,9 +422,9 @@ relocate_fix_got_relocs_for_got_info (struct got_entry ** list_p,
(long) entry->offset);
else
{
- bfd_put_32 (output_bfd,
- reloc_data->sym_value + sec_vma,
- htab->sgot->contents + entry->offset);
+ write_in_got (output_bfd,
+ reloc_data->sym_value + sec_vma,
+ htab->sgot->contents + entry->offset);
ARC_DEBUG ("arc_info: PATCHED: %#08lx "
"@ %#08lx for sym %s in got offset %#lx\n",
(long) (reloc_data->sym_value + sec_vma),
@@ -496,12 +510,14 @@ GOT_OFFSET = %#lx, GOT_VMA = %#lx, INDEX = %ld, ADDEND = 0x0\n",
bfd_vma addend = 0;
if (list->type == GOT_TLS_IE)
{
- addend = bfd_get_32 (output_bfd,
- htab->sgot->contents + got_offset);
+ /* CZI: I don't understand why we need this. Adding an
+ assert to catch the usecase. */
+ addend = read_from_got (output_bfd,
+ htab->sgot->contents + got_offset);
}
ADD_RELA (output_bfd, got,
- got_offset + (e == TLS_GOT_MOD_AND_OFF ? 4 : 0),
+ got_offset + (e == TLS_GOT_MOD_AND_OFF ? GOT_ENTRY_SIZE : 0),
dynindx,
(list->type == GOT_TLS_IE ? R_ARC_TLS_TPOFF
: R_ARC_TLS_DTPOFF),
diff --git a/bfd/arc-plt.c b/bfd/arc-plt.c
new file mode 100644
index 00000000000..7ba98fdc570
--- /dev/null
+++ b/bfd/arc-plt.c
@@ -0,0 +1,121 @@
+/* ARC-specific support for PLT relocations.
+ Copyright (C) 2016-2019 Free Software Foundation, Inc.
+ Contributed by Cupertino Miranda (cmiranda@synopsys.com).
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "arc-plt.h"
+
+#define PLT_TYPE_START(NAME) \
+ const insn_hword NAME##_plt_entry[] = {
+#define PLT_TYPE_END(NAME) };
+#define PLT_ENTRY(...) __VA_ARGS__,
+#define PLT_ELEM(...)
+#define ENTRY_RELOC(...)
+#define ELEM_RELOC(...)
+
+#include "arc-plt.def"
+
+#undef PLT_TYPE_START
+#undef PLT_TYPE_END
+#undef PLT_ENTRY
+#undef PLT_ELEM
+#undef ENTRY_RELOC
+#undef ELEM_RELOC
+
+#define PLT_TYPE_START(NAME) \
+ const struct plt_reloc NAME##_plt_entry_relocs[] = {
+#define PLT_TYPE_END(NAME) \
+ {0, 0, 0, LAST_RELOC, 0} \
+ };
+#define PLT_ENTRY(...)
+#define PLT_ELEM(...)
+#define ENTRY_RELOC(...) { __VA_ARGS__ },
+#define ELEM_RELOC(...)
+
+#include "arc-plt.def"
+
+#undef PLT_TYPE_START
+#undef PLT_TYPE_END
+#undef PLT_ENTRY
+#undef PLT_ELEM
+#undef ENTRY_RELOC
+#undef ELEM_RELOC
+
+
+#define PLT_TYPE_START(NAME) \
+ const insn_hword NAME##_plt_elem[] = {
+#define PLT_TYPE_END(NAME) };
+#define PLT_ENTRY(...)
+#define PLT_ELEM(...) __VA_ARGS__,
+#define ENTRY_RELOC(...)
+#define ELEM_RELOC(...)
+
+#include "arc-plt.def"
+
+#undef PLT_TYPE_START
+#undef PLT_TYPE_END
+#undef PLT_ENTRY
+#undef PLT_ELEM
+#undef ENTRY_RELOC
+#undef ELEM_RELOC
+
+#define PLT_TYPE_START(NAME) \
+ const struct plt_reloc NAME##_plt_elem_relocs[] = {
+#define PLT_TYPE_END(NAME) \
+ {0, 0, 0, LAST_RELOC, 0} \
+ };
+#define PLT_ENTRY(...)
+#define PLT_ELEM(...)
+#define ENTRY_RELOC(...)
+#define ELEM_RELOC(...) { __VA_ARGS__ },
+
+#include "arc-plt.def"
+
+#undef PLT_TYPE_START
+#undef PLT_TYPE_END
+#undef PLT_ENTRY
+#undef PLT_ELEM
+#undef ENTRY_RELOC
+#undef ELEM_RELOC
+
+
+#define PLT_TYPE_START(NAME) \
+ { \
+ .entry = &NAME##_plt_entry, \
+ .entry_size = sizeof (NAME##_plt_entry), \
+ .elem = &NAME##_plt_elem, \
+ .elem_size = sizeof (NAME##_plt_elem), \
+ .entry_relocs = NAME##_plt_entry_relocs, \
+ .elem_relocs = NAME##_plt_elem_relocs
+#define PLT_TYPE_END(NAME) },
+#define PLT_ENTRY(...)
+#define PLT_ELEM(...)
+#define ENTRY_RELOC(...)
+#define ELEM_RELOC(...)
+struct plt_version_t plt_versions[PLT_MAX] = {
+
+#include "arc-plt.def"
+
+};
+#undef PLT_TYPE_START
+#undef PLT_TYPE_END
+#undef PLT_ENTRY
+#undef PLT_ELEM
+#undef ENTRY_RELOC
+#undef ELEM_RELOC
diff --git a/bfd/arc-plt.def b/bfd/arc-plt.def
index 254f1e5b85e..87bac4f69be 100644
--- a/bfd/arc-plt.def
+++ b/bfd/arc-plt.def
@@ -1,4 +1,4 @@
-/* Arc V2 Related PLT entries.
+/* Arc V2/V3 Related PLT entries.
Copyright (C) 2016-2020 Free Software Foundation, Inc.
Contributed by Cupertino Miranda (cmiranda@synopsys.com).
@@ -19,6 +19,47 @@
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
+
+PLT_TYPE_START (ELF_ARCV3_PIC)
+// ldl r11, [pcl, 0] .got.plt + 8 -- at .got.plt + 0 should be the address of .dynamic
+// ldl r10, [pcl, 0] .got.plt + 16
+// j [r10]
+// padding
+
+
+// 2e: 2731 ff0b 0000 0000 ldl r11,[pcl,0@s32] ;2c <main+0x2c>
+// 32: R_ARC_GOTPC32 f_var
+// 36: 2731 ff0a 0000 0000 ldl r10,[pcl,0@s32] ;34 <main+0x34>
+// 3a: R_ARC_GOTPC32 f_var
+// 3e: 2020 0280 j [r10]
+
+
+ PLT_ENTRY (0x2731, 0xff0b, 0x0000, 0x0000) /* ldl %r11, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+4 */
+ PLT_ENTRY (0x2731, 0xff0a, 0x0000, 0x0000) /* ldl %r10, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+8 */
+ PLT_ENTRY (0x2020, 0x0280) /* j [%r10] */
+ PLT_ENTRY (0x0, 0x0, 0x0, 0x0, 0x0,0x0) /* padding */
+
+// ldl r12, [pcl, 0] -- at .got.plt + 0 should be the address of .dynamic
+
+// 46: 2731 ff0c 0000 0000 ldl r12,[pcl,0@s32] ;44 <main+0x44>
+// 4a: R_ARC_GOTPC32 f_var
+// 4e: 2021 0300 j.d [r12]
+// 52: 240a 1fc0 mov r12,pcl
+
+
+ PLT_ELEM (0x2731, 0xff0c, 0x0000, 0x0000) /* ld %r12, [%pc,func@got] */
+ PLT_ELEM (0x2021, 0x0300) /* j.d [%r12] */
+ PLT_ELEM (0x240a, 0x1fc0) /* mov %r12, %pcl */
+
+ ENTRY_RELOC (4, 32, 0xFFFFFFFF, SGOT | RELATIVE_INSN_32 | MIDDLE_ENDIAN, 8)
+ ENTRY_RELOC (12, 32, 0xFFFFFFFF, SGOT | RELATIVE_INSN_32 | MIDDLE_ENDIAN, 16)
+ ENTRY_RELOC (20, 32, 0xFFFFFFFF, SGOT, 0)
+
+ ELEM_RELOC (4, 32, 0xFFFFFFFF, SGOT | RELATIVE_INSN_32 | MIDDLE_ENDIAN, 0)
+
+PLT_TYPE_END (ELF_ARCV3_PIC)
+
+
PLT_TYPE_START (ELF_ARCV2_PIC)
PLT_ENTRY (0x2730, 0x7f8b, 0x0000, 0x0000) /* ld %r11, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+4 */
PLT_ENTRY (0x2730, 0x7f8a, 0x0000, 0x0000) /* ld %r10, [pcl,0] : 0 to be replaced by _DYNAMIC@GOTPC+8 */
diff --git a/bfd/arc-plt.h b/bfd/arc-plt.h
index f668fee8ca6..3c98b2ff141 100644
--- a/bfd/arc-plt.h
+++ b/bfd/arc-plt.h
@@ -22,6 +22,9 @@
#ifndef ARC_PLT_H
#define ARC_PLT_H
+#include "sysdep.h"
+#include "bfd.h"
+
/* Instructions appear in memory as a sequence of half-words (16 bit);
individual half-words are represented on the target in target byte order.
We use 'unsigned short' on the host to represent the PLT templates,
@@ -92,97 +95,20 @@ struct plt_version_t
};
#define PLT_TYPE_START(NAME) \
- const insn_hword NAME##_plt_entry[] = {
-#define PLT_TYPE_END(NAME) };
-#define PLT_ENTRY(...) __VA_ARGS__,
-#define PLT_ELEM(...)
-#define ENTRY_RELOC(...)
-#define ELEM_RELOC(...)
-
-#include "arc-plt.def"
-
-#undef PLT_TYPE_START
-#undef PLT_TYPE_END
-#undef PLT_ENTRY
-#undef PLT_ELEM
-#undef ENTRY_RELOC
-#undef ELEM_RELOC
-
-#define PLT_TYPE_START(NAME) \
- const struct plt_reloc NAME##_plt_entry_relocs[] = {
-#define PLT_TYPE_END(NAME) \
- {0, 0, 0, LAST_RELOC, 0} \
- };
-#define PLT_ENTRY(...)
-#define PLT_ELEM(...)
-#define ENTRY_RELOC(...) { __VA_ARGS__ },
-#define ELEM_RELOC(...)
+ extern const insn_hword NAME##_plt_entry[]; \
+ extern const struct plt_reloc NAME##_plt_entry_relocs[]; \
+ extern const insn_hword NAME##_plt_elem[]; \
+ extern const struct plt_reloc NAME##_plt_elem_relocs[];
-#include "arc-plt.def"
-#undef PLT_TYPE_START
-#undef PLT_TYPE_END
-#undef PLT_ENTRY
-#undef PLT_ELEM
-#undef ENTRY_RELOC
-#undef ELEM_RELOC
-
-
-#define PLT_TYPE_START(NAME) \
- const insn_hword NAME##_plt_elem[] = {
-#define PLT_TYPE_END(NAME) };
-#define PLT_ENTRY(...)
-#define PLT_ELEM(...) __VA_ARGS__,
-#define ENTRY_RELOC(...)
-#define ELEM_RELOC(...)
-
-#include "arc-plt.def"
-
-#undef PLT_TYPE_START
-#undef PLT_TYPE_END
-#undef PLT_ENTRY
-#undef PLT_ELEM
-#undef ENTRY_RELOC
-#undef ELEM_RELOC
-
-#define PLT_TYPE_START(NAME) \
- const struct plt_reloc NAME##_plt_elem_relocs[] = {
-#define PLT_TYPE_END(NAME) \
- {0, 0, 0, LAST_RELOC, 0} \
- };
-#define PLT_ENTRY(...)
-#define PLT_ELEM(...)
-#define ENTRY_RELOC(...)
-#define ELEM_RELOC(...) { __VA_ARGS__ },
-
-#include "arc-plt.def"
-
-#undef PLT_TYPE_START
-#undef PLT_TYPE_END
-#undef PLT_ENTRY
-#undef PLT_ELEM
-#undef ENTRY_RELOC
-#undef ELEM_RELOC
-
-
-#define PLT_TYPE_START(NAME) \
- { \
- .entry = &NAME##_plt_entry, \
- .entry_size = sizeof (NAME##_plt_entry), \
- .elem = &NAME##_plt_elem, \
- .elem_size = sizeof (NAME##_plt_elem), \
- .entry_relocs = NAME##_plt_entry_relocs, \
- .elem_relocs = NAME##_plt_elem_relocs
-#define PLT_TYPE_END(NAME) },
+#define PLT_TYPE_END(NAME)
#define PLT_ENTRY(...)
#define PLT_ELEM(...)
#define ENTRY_RELOC(...)
#define ELEM_RELOC(...)
-struct plt_version_t plt_versions[PLT_MAX] = {
#include "arc-plt.def"
-};
#undef PLT_TYPE_START
#undef PLT_TYPE_END
#undef PLT_ENTRY
@@ -190,5 +116,6 @@ struct plt_version_t plt_versions[PLT_MAX] = {
#undef ENTRY_RELOC
#undef ELEM_RELOC
+extern struct plt_version_t plt_versions[PLT_MAX];
-#endif /* ARC_PLT_H */
+#endif
diff --git a/bfd/archures.c b/bfd/archures.c
index bcc2601e0c8..890d0796757 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -365,6 +365,8 @@ DESCRIPTION
.#define bfd_mach_arc_arc601 4
.#define bfd_mach_arc_arc700 3
.#define bfd_mach_arc_arcv2 5
+.#define bfd_mach_arcv3_64 0x10
+.#define bfd_mach_arcv3_32 0x20
. bfd_arch_m32c, {* Renesas M16C/M32C. *}
.#define bfd_mach_m16c 0x75
.#define bfd_mach_m32c 0x78
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index df6f9f45673..e833861bfd5 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1765,6 +1765,8 @@ enum bfd_architecture
#define bfd_mach_arc_arc601 4
#define bfd_mach_arc_arc700 3
#define bfd_mach_arc_arcv2 5
+#define bfd_mach_arcv3_64 0x10
+#define bfd_mach_arcv3_32 0x20
bfd_arch_m32c, /* Renesas M16C/M32C. */
#define bfd_mach_m16c 0x75
#define bfd_mach_m32c 0x78
@@ -3352,6 +3354,7 @@ pc-relative or some form of GOT-indirect relocation. */
BFD_RELOC_ARC_16,
BFD_RELOC_ARC_24,
BFD_RELOC_ARC_32,
+ BFD_RELOC_ARC_64,
BFD_RELOC_ARC_N8,
BFD_RELOC_ARC_N16,
BFD_RELOC_ARC_N24,
@@ -3416,6 +3419,26 @@ pc-relative or some form of GOT-indirect relocation. */
BFD_RELOC_ARC_S21H_PCREL_PLT,
BFD_RELOC_ARC_NPS_CMEM16,
BFD_RELOC_ARC_JLI_SECTOFF,
+ BFD_RELOC_ARC_S7H_PCREL,
+ BFD_RELOC_ARC_S8H_PCREL,
+ BFD_RELOC_ARC_S9H_PCREL,
+ BFD_RELOC_ARC_S10H_PCREL,
+ BFD_RELOC_ARC_S13H_PCREL,
+ BFD_RELOC_ARC_ALIGN,
+ BFD_RELOC_ARC_ADD8,
+ BFD_RELOC_ARC_ADD16,
+ BFD_RELOC_ARC_SUB8,
+ BFD_RELOC_ARC_SUB16,
+ BFD_RELOC_ARC_SUB32,
+ BFD_RELOC_ARC_LO32,
+ BFD_RELOC_ARC_HI32,
+ BFD_RELOC_ARC_LO32_ME,
+ BFD_RELOC_ARC_HI32_ME,
+ BFD_RELOC_ARC_N64,
+ BFD_RELOC_ARC_SDA_LDST3,
+ BFD_RELOC_ARC_NLO32,
+ BFD_RELOC_ARC_NLO32_ME,
+
/* ADI Blackfin 16 bit immediate absolute reloc. */
BFD_RELOC_BFIN_16_IMM,
diff --git a/bfd/config.bfd b/bfd/config.bfd
index 14523caf0c5..5bc2635b159 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -319,16 +319,26 @@ case "${targ}" in
targ_defvec=am33_elf32_linux_vec
;;
- arc*eb-*-elf* | arc*eb-*-linux*)
+#ifdef BFD64
+ arceb-*-elf* | arceb-*-linux*)
targ_defvec=arc_elf32_be_vec
- targ_selvecs=arc_elf32_le_vec
+ targ_selvecs="arc_elf32_le_vec arc_elf64_le_vec"
+ want64=true
;;
- arc*-*-elf* | arc*-*-linux*)
+ arc-*-elf* | arc-*-linux*)
targ_defvec=arc_elf32_le_vec
- targ_selvecs=arc_elf32_be_vec
+ targ_selvecs="arc_elf32_be_vec arc_elf64_le_vec"
+ want64=true
;;
+ arc64-*-*)
+ targ_defvec=arc_elf64_le_vec
+ targ_selvecs="arc_elf32_be_vec arc_elf32_le_vec"
+ want64=true
+ ;;
+#endif
+
arm-*-darwin*)
targ_defvec=arm_mach_o_vec
targ_selvecs="mach_o_le_vec mach_o_be_vec mach_o_fat_vec"
diff --git a/bfd/configure b/bfd/configure
index c6905180819..eee59a34a9a 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -14721,8 +14721,9 @@ do
aout0_be_vec) tb="$tb aout0.lo aout32.lo" ;;
aout64_vec) tb="$tb demo64.lo aout64.lo"; target_size=64 ;;
aout_vec) tb="$tb host-aout.lo aout32.lo" ;;
- arc_elf32_be_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
- arc_elf32_le_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
+ arc_elf32_be_vec) tb="$tb arc-plt.lo elf32-arc.lo elf32.lo $elf" ;;
+ arc_elf32_le_vec) tb="$tb arc-plt.lo elf32-arc.lo elf32.lo $elf" ;;
+ arc_elf64_le_vec) tb="$tb arc-plt.lo elf64-arc.lo elf64.lo elf32.lo $elf"; target_size=64 ;;
arm_elf32_be_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
arm_elf32_le_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
arm_elf32_fdpic_be_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
diff --git a/bfd/configure.ac b/bfd/configure.ac
index 8e86f8399ce..b23cda48157 100644
--- a/bfd/configure.ac
+++ b/bfd/configure.ac
@@ -457,8 +457,9 @@ do
aout0_be_vec) tb="$tb aout0.lo aout32.lo" ;;
aout64_vec) tb="$tb demo64.lo aout64.lo"; target_size=64 ;;
aout_vec) tb="$tb host-aout.lo aout32.lo" ;;
- arc_elf32_be_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
- arc_elf32_le_vec) tb="$tb elf32-arc.lo elf32.lo $elf" ;;
+ arc_elf32_be_vec) tb="$tb arc-plt.lo elf32-arc.lo elf32.lo $elf" ;;
+ arc_elf32_le_vec) tb="$tb arc-plt.lo elf32-arc.lo elf32.lo $elf" ;;
+ arc_elf64_le_vec) tb="$tb arc-plt.lo elf64-arc.lo elf64.lo elf32.lo $elf"; target_size=64 ;;
arm_elf32_be_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
arm_elf32_le_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
arm_elf32_fdpic_be_vec) tb="$tb elf32-arm.lo elf32.lo elf-nacl.lo elf-vxworks.lo $elf" ;;
diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c
index 56a9f7bb454..71eed8432c2 100644
--- a/bfd/cpu-arc.c
+++ b/bfd/cpu-arc.c
@@ -26,37 +26,39 @@
static const bfd_arch_info_type *
arc_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b);
-#define ARC(mach, print_name, default_p, next) \
- { \
- 32, /* Bits in a word. */ \
- 32, /* Bits in an address. */ \
- 8, /* Bits in a byte. */ \
- bfd_arch_arc, \
- mach, \
- "arc", \
- print_name, \
- 4, /* Section alignment power. */ \
- default_p, \
- arc_compatible, \
- bfd_default_scan, \
- bfd_arch_default_fill, \
- next, \
- 0 /* Maximum offset of a reloc from the start of an insn. */ \
- }
+#define ARC(BITS_WORD, BITS_ADDR, MACH, PRINT_NAME, DEFAULT_P, NEXT) \
+{ \
+ BITS_WORD, /* 32 bits in a word */ \
+ BITS_ADDR, /* 32 bits in an address */ \
+ 8, /* 8 bits in a byte */ \
+ bfd_arch_arc, \
+ MACH, \
+ "arc", \
+ PRINT_NAME, \
+ 4, /* section alignment power */ \
+ DEFAULT_P, \
+ arc_compatible, \
+ bfd_default_scan, \
+ bfd_arch_default_fill, \
+ NEXT, \
+ 0 /* Maximum offset of a reloc from the start of an insn. */ \
+}
static const bfd_arch_info_type arch_info_struct[] =
{
- ARC (bfd_mach_arc_arc600, "A6" , FALSE, &arch_info_struct[1]),
- ARC (bfd_mach_arc_arc601, "ARC601", FALSE, &arch_info_struct[2]),
- ARC (bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[3]),
- ARC (bfd_mach_arc_arc700, "A7", FALSE, &arch_info_struct[4]),
- ARC (bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[5]),
- ARC (bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[6]),
- ARC (bfd_mach_arc_arcv2, "HS", FALSE, NULL),
+ ARC (32, 32, bfd_mach_arc_arc600, "A6" , FALSE, &arch_info_struct[1]),
+ ARC (32, 32, bfd_mach_arc_arc601, "ARC601", FALSE, &arch_info_struct[2]),
+ ARC (32, 32, bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[3]),
+ ARC (32, 32, bfd_mach_arc_arc700, "A7", FALSE, &arch_info_struct[4]),
+ ARC (32, 32, bfd_mach_arc_arcv2, "ARCv2", FALSE, &arch_info_struct[5]),
+ ARC (32, 32, bfd_mach_arc_arcv2, "EM", FALSE, &arch_info_struct[6]),
+ ARC (32, 32, bfd_mach_arc_arcv2, "HS", FALSE, &arch_info_struct[7]),
+ ARC (32, 32, bfd_mach_arcv3_32, "ARCv3_32", FALSE, &arch_info_struct[8]),
+ ARC (64, 64, bfd_mach_arcv3_64, "ARCv3_64", FALSE, NULL),
};
const bfd_arch_info_type bfd_arc_arch =
- ARC (bfd_mach_arc_arc600, "ARC600", TRUE, &arch_info_struct[0]);
+ ARC (32, 32, bfd_mach_arc_arc600, "ARC600", TRUE, &arch_info_struct[0]);
/* ARC-specific "compatible" function. The general rule is that if A and B are
compatible, then this function should return architecture that is more
@@ -84,9 +86,6 @@ arc_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
if (a->arch != b->arch)
return NULL;
- if (a->bits_per_word != b->bits_per_word)
- return NULL;
-
/* ARCv2|EM and EM. */
if ((a->mach == bfd_mach_arc_arcv2 && b == em)
|| (b->mach == bfd_mach_arc_arcv2 && a == em))
@@ -97,5 +96,6 @@ arc_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
|| (b->mach == bfd_mach_arc_arcv2 && a == hs))
return hs;
- return bfd_default_compatible (a, b);
+ /* Machine compatibilitu is checked in merge_private_bfd_data. */
+ return a;
}
diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
deleted file mode 100644
index 4d9d6b99928..00000000000
--- a/bfd/elf32-arc.c
+++ /dev/null
@@ -1,3158 +0,0 @@
-/* ARC-specific support for 32-bit ELF
- Copyright (C) 1994-2020 Free Software Foundation, Inc.
- Contributed by Cupertino Miranda (cmiranda@synopsys.com).
-
- This file is part of BFD, the Binary File Descriptor library.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
- MA 02110-1301, USA. */
-
-#include "sysdep.h"
-#include "bfd.h"
-#include "libbfd.h"
-#include "elf-bfd.h"
-#include "elf/arc.h"
-#include "libiberty.h"
-#include "opcode/arc-func.h"
-#include "opcode/arc.h"
-#include "arc-plt.h"
-
-#define FEATURE_LIST_NAME bfd_feature_list
-#define CONFLICT_LIST bfd_conflict_list
-#include "opcode/arc-attrs.h"
-
-/* #define ARC_ENABLE_DEBUG 1 */
-#ifdef ARC_ENABLE_DEBUG
-static const char *
-name_for_global_symbol (struct elf_link_hash_entry *h)
-{
- static char *local_str = "(local)";
- if (h == NULL)
- return local_str;
- return h->root.root.string;
-}
-#define ARC_DEBUG(fmt, args...) fprintf (stderr, fmt, ##args)
-#else
-#define ARC_DEBUG(...)
-#endif
-
-
-#define ADD_RELA(BFD, SECTION, OFFSET, SYM_IDX, TYPE, ADDEND) \
- { \
- struct elf_link_hash_table *_htab = elf_hash_table (info); \
- Elf_Internal_Rela _rel; \
- bfd_byte * _loc; \
- \
- if (_htab->dynamic_sections_created == TRUE) \
- { \
- BFD_ASSERT (_htab->srel##SECTION &&_htab->srel##SECTION->contents); \
- _loc = _htab->srel##SECTION->contents \
- + ((_htab->srel##SECTION->reloc_count) \
- * sizeof (Elf32_External_Rela)); \
- _htab->srel##SECTION->reloc_count++; \
- _rel.r_addend = ADDEND; \
- _rel.r_offset = (_htab->s##SECTION)->output_section->vma \
- + (_htab->s##SECTION)->output_offset + OFFSET; \
- BFD_ASSERT ((long) SYM_IDX != -1); \
- _rel.r_info = ELF32_R_INFO (SYM_IDX, TYPE); \
- bfd_elf32_swap_reloca_out (BFD, &_rel, _loc); \
- } \
- }
-
-#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
- case VALUE: \
- return "R_" #TYPE; \
- break;
-
-static ATTRIBUTE_UNUSED const char *
-reloc_type_to_name (unsigned int type)
-{
- switch (type)
- {
-#include "elf/arc-reloc.def"
-
- default:
- return "UNKNOWN";
- break;
- }
-}
-
-#undef ARC_RELOC_HOWTO
-
-/* Try to minimize the amount of space occupied by relocation tables
- on the ROM (not that the ROM won't be swamped by other ELF overhead). */
-
-#define USE_REL 1
-
-/* Similar with bfd_get_32 but taking into account the
- middle-endianess of the ARC CPUs. Only to be used in code
- sections. */
-
-static bfd_vma
-bfd_get_32_me (bfd * abfd,const unsigned char * data)
-{
- bfd_vma value = 0;
-
- if (bfd_big_endian (abfd))
- value = bfd_get_32 (abfd, data);
- else
- {
- value = ((bfd_get_8 (abfd, data) & 255) << 16);
- value |= ((bfd_get_8 (abfd, data + 1) & 255) << 24);
- value |= (bfd_get_8 (abfd, data + 2) & 255);
- value |= ((bfd_get_8 (abfd, data + 3) & 255) << 8);
- }
-
- return value;
-}
-
-static void
-bfd_put_32_me (bfd *abfd, bfd_vma value,unsigned char *data)
-{
- bfd_put_16 (abfd, (value & 0xffff0000) >> 16, data);
- bfd_put_16 (abfd, value & 0xffff, data + 2);
-}
-
-static ATTRIBUTE_UNUSED bfd_boolean
-is_reloc_PC_relative (reloc_howto_type *howto)
-{
- return (strstr (howto->name, "PC") != NULL) ? TRUE : FALSE;
-}
-
-static bfd_boolean
-is_reloc_SDA_relative (reloc_howto_type *howto)
-{
- return (strstr (howto->name, "SDA") != NULL) ? TRUE : FALSE;
-}
-
-static bfd_boolean
-is_reloc_for_GOT (reloc_howto_type * howto)
-{
- if (strstr (howto->name, "TLS") != NULL)
- return FALSE;
- return (strstr (howto->name, "GOT") != NULL) ? TRUE : FALSE;
-}
-
-static bfd_boolean
-is_reloc_for_PLT (reloc_howto_type * howto)
-{
- return (strstr (howto->name, "PLT") != NULL) ? TRUE : FALSE;
-}
-
-static bfd_boolean
-is_reloc_for_TLS (reloc_howto_type *howto)
-{
- return (strstr (howto->name, "TLS") != NULL) ? TRUE : FALSE;
-}
-
-struct arc_relocation_data
-{
- bfd_signed_vma reloc_offset;
- bfd_signed_vma reloc_addend;
- bfd_signed_vma got_offset_value;
-
- bfd_signed_vma sym_value;
- asection * sym_section;
-
- reloc_howto_type *howto;
-
- asection * input_section;
-
- bfd_signed_vma sdata_begin_symbol_vma;
- bfd_boolean sdata_begin_symbol_vma_set;
- bfd_signed_vma got_symbol_vma;
-
- bfd_boolean should_relocate;
-
- const char * symbol_name;
-};
-
-/* ARC ELF linker hash entry. */
-struct elf_arc_link_hash_entry
-{
- struct elf_link_hash_entry root;
-
- struct got_entry *got_ents;
-};
-
-
-/* Should be included at this location due to static declarations
- defined before this point. */
-#include "arc-got.h"
-
-#define arc_bfd_get_8(A,B,C) bfd_get_8(A,B)
-#define arc_bfd_get_16(A,B,C) bfd_get_16(A,B)
-#define arc_bfd_get_32(A,B,C) bfd_get_32(A,B)
-#define arc_bfd_put_8(A,B,C,D) bfd_put_8(A,B,C)
-#define arc_bfd_put_16(A,B,C,D) bfd_put_16(A,B,C)
-#define arc_bfd_put_32(A,B,C,D) bfd_put_32(A,B,C)
-
-
-static bfd_reloc_status_type
-arc_elf_reloc (bfd *abfd ATTRIBUTE_UNUSED,
- arelent *reloc_entry,
- asymbol *symbol_in,
- void *data ATTRIBUTE_UNUSED,
- asection *input_section,
- bfd *output_bfd,
- char ** error_message ATTRIBUTE_UNUSED)
-{
- if (output_bfd != NULL)
- {
- reloc_entry->address += input_section->output_offset;
-
- /* In case of relocateable link and if the reloc is against a
- section symbol, the addend needs to be adjusted according to
- where the section symbol winds up in the output section. */
- if ((symbol_in->flags & BSF_SECTION_SYM) && symbol_in->section)
- reloc_entry->addend += symbol_in->section->output_offset;
-
- return bfd_reloc_ok;
- }
-
- return bfd_reloc_continue;
-}
-
-
-#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
- TYPE = VALUE,
-
-enum howto_list
-{
-#include "elf/arc-reloc.def"
- HOWTO_LIST_LAST
-};
-
-#undef ARC_RELOC_HOWTO
-
-#define ARC_RELOC_HOWTO(TYPE, VALUE, RSIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
- [TYPE] = HOWTO (R_##TYPE, 0, RSIZE, BITSIZE, FALSE, 0, \
- complain_overflow_##OVERFLOW, arc_elf_reloc, \
- "R_" #TYPE, FALSE, 0, 0, FALSE),
-
-static struct reloc_howto_struct elf_arc_howto_table[] =
-{
-#include "elf/arc-reloc.def"
-/* Example of what is generated by the preprocessor. Currently kept as an
- example.
- HOWTO (R_ARC_NONE, // Type.
- 0, // Rightshift.
- 2, // Size (0 = byte, 1 = short, 2 = long).
- 32, // Bitsize.
- FALSE, // PC_relative.
- 0, // Bitpos.
- complain_overflow_bitfield, // Complain_on_overflow.
- bfd_elf_generic_reloc, // Special_function.
- "R_ARC_NONE", // Name.
- TRUE, // Partial_inplace.
- 0, // Src_mask.
- 0, // Dst_mask.
- FALSE), // PCrel_offset.
-*/
-};
-#undef ARC_RELOC_HOWTO
-
-static void
-arc_elf_howto_init (void)
-{
-#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
- elf_arc_howto_table[TYPE].pc_relative = \
- (strstr (#FORMULA, " P ") != NULL || strstr (#FORMULA, " PDATA ") != NULL); \
- elf_arc_howto_table[TYPE].dst_mask = RELOC_FUNCTION(0, ~0); \
- /* Only 32 bit data relocations should be marked as ME. */ \
- if (strstr (#FORMULA, " ME ") != NULL) \
- { \
- BFD_ASSERT (SIZE == 2); \
- }
-
-#include "elf/arc-reloc.def"
-
-}
-#undef ARC_RELOC_HOWTO
-
-
-#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
- [TYPE] = VALUE,
-
-const int howto_table_lookup[] =
-{
-#include "elf/arc-reloc.def"
-};
-
-#undef ARC_RELOC_HOWTO
-
-static reloc_howto_type *
-arc_elf_howto (unsigned int r_type)
-{
- if (elf_arc_howto_table[R_ARC_32].dst_mask == 0)
- arc_elf_howto_init ();
- return &elf_arc_howto_table[r_type];
-}
-
-/* Map BFD reloc types to ARC ELF reloc types. */
-
-struct arc_reloc_map
-{
- bfd_reloc_code_real_type bfd_reloc_val;
- unsigned char elf_reloc_val;
-};
-
-/* ARC ELF linker hash table. */
-struct elf_arc_link_hash_table
-{
- struct elf_link_hash_table elf;
-};
-
-static struct bfd_hash_entry *
-elf_arc_link_hash_newfunc (struct bfd_hash_entry *entry,
- struct bfd_hash_table *table,
- const char *string)
-{
- struct elf_arc_link_hash_entry * ret =
- (struct elf_arc_link_hash_entry *) entry;
-
- /* Allocate the structure if it has not already been allocated by a
- subclass. */
- if (ret == NULL)
- ret = (struct elf_arc_link_hash_entry *)
- bfd_hash_allocate (table, sizeof (struct elf_arc_link_hash_entry));
- if (ret == NULL)
- return (struct bfd_hash_entry *) ret;
-
- /* Call the allocation method of the superclass. */
- ret = ((struct elf_arc_link_hash_entry *)
- _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
- table, string));
- if (ret != NULL)
- {
- ret->got_ents = NULL;
- }
-
- return (struct bfd_hash_entry *) ret;
-}
-
-/* Destroy an ARC ELF linker hash table. */
-static void
-elf_arc_link_hash_table_free (bfd *obfd)
-{
- _bfd_elf_link_hash_table_free (obfd);
-}
-
-/* Create an ARC ELF linker hash table. */
-
-static struct bfd_link_hash_table *
-arc_elf_link_hash_table_create (bfd *abfd)
-{
- struct elf_arc_link_hash_table *ret;
-
- ret = (struct elf_arc_link_hash_table *) bfd_zmalloc (sizeof (*ret));
- if (ret == NULL)
- return NULL;
-
- if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd,
- elf_arc_link_hash_newfunc,
- sizeof (struct elf_arc_link_hash_entry),
- ARC_ELF_DATA))
- {
- free (ret);
- return NULL;
- }
-
- ret->elf.root.hash_table_free = elf_arc_link_hash_table_free;
-
- return &ret->elf.root;
-}
-
-#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
- { BFD_RELOC_##TYPE, R_##TYPE },
-
-static const struct arc_reloc_map arc_reloc_map[] =
-{
-#include "elf/arc-reloc.def"
-
- {BFD_RELOC_NONE, R_ARC_NONE},
- {BFD_RELOC_8, R_ARC_8},
- {BFD_RELOC_16, R_ARC_16},
- {BFD_RELOC_24, R_ARC_24},
- {BFD_RELOC_32, R_ARC_32},
-};
-
-#undef ARC_RELOC_HOWTO
-
-typedef ATTRIBUTE_UNUSED bfd_vma (*replace_func) (unsigned, int ATTRIBUTE_UNUSED);
-
-#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
- case TYPE: \
- func = (void *) RELOC_FUNCTION; \
- break;
-
-static replace_func
-get_replace_function (bfd *abfd, unsigned int r_type)
-{
- void *func = NULL;
-
- switch (r_type)
- {
- #include "elf/arc-reloc.def"
- }
-
- if (func == replace_bits24 && bfd_big_endian (abfd))
- func = replace_bits24_be;
-
- return (replace_func) func;
-}
-#undef ARC_RELOC_HOWTO
-
-static reloc_howto_type *
-arc_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
- bfd_reloc_code_real_type code)
-{
- unsigned int i;
-
- for (i = ARRAY_SIZE (arc_reloc_map); i--;)
- {
- if (arc_reloc_map[i].bfd_reloc_val == code)
- return arc_elf_howto (arc_reloc_map[i].elf_reloc_val);
- }
-
- return NULL;
-}
-
-/* Function to set the ELF flag bits. */
-static bfd_boolean
-arc_elf_set_private_flags (bfd *abfd, flagword flags)
-{
- elf_elfheader (abfd)->e_flags = flags;
- elf_flags_init (abfd) = TRUE;
- return TRUE;
-}
-
-/* Print private flags. */
-static bfd_boolean
-arc_elf_print_private_bfd_data (bfd *abfd, void * ptr)
-{
- FILE *file = (FILE *) ptr;
- flagword flags;
-
- BFD_ASSERT (abfd != NULL && ptr != NULL);
-
- /* Print normal ELF private data. */
- _bfd_elf_print_private_bfd_data (abfd, ptr);
-
- flags = elf_elfheader (abfd)->e_flags;
- fprintf (file, _("private flags = 0x%lx:"), (unsigned long) flags);
-
- switch (flags & EF_ARC_MACH_MSK)
- {
- case EF_ARC_CPU_ARCV2HS : fprintf (file, " -mcpu=ARCv2HS"); break;
- case EF_ARC_CPU_ARCV2EM : fprintf (file, " -mcpu=ARCv2EM"); break;
- case E_ARC_MACH_ARC600 : fprintf (file, " -mcpu=ARC600"); break;
- case E_ARC_MACH_ARC601 : fprintf (file, " -mcpu=ARC601"); break;
- case E_ARC_MACH_ARC700 : fprintf (file, " -mcpu=ARC700"); break;
- default:
- fprintf (file, "-mcpu=unknown");
- break;
- }
-
- switch (flags & EF_ARC_OSABI_MSK)
- {
- case E_ARC_OSABI_ORIG : fprintf (file, " (ABI:legacy)"); break;
- case E_ARC_OSABI_V2 : fprintf (file, " (ABI:v2)"); break;
- case E_ARC_OSABI_V3 : fprintf (file, " (ABI:v3)"); break;
- case E_ARC_OSABI_V4 : fprintf (file, " (ABI:v4)"); break;
- default:
- fprintf (file, " (ABI:unknown)");
- break;
- }
-
- fputc ('\n', file);
- return TRUE;
-}
-
-/* Copy backend specific data from one object module to another. */
-
-static bfd_boolean
-arc_elf_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
-{
- if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour
- || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
- return TRUE;
-
- BFD_ASSERT (!elf_flags_init (obfd)
- || elf_elfheader (obfd)->e_flags == elf_elfheader (ibfd)->e_flags);
-
- elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags;
- elf_flags_init (obfd) = TRUE;
-
- /* Copy object attributes. */
- _bfd_elf_copy_obj_attributes (ibfd, obfd);
-
- return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
-}
-
-static reloc_howto_type *
-bfd_elf32_bfd_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED,
- const char *r_name)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE (elf_arc_howto_table); i++)
- if (elf_arc_howto_table[i].name != NULL
- && strcasecmp (elf_arc_howto_table[i].name, r_name) == 0)
- return arc_elf_howto (i);
-
- return NULL;
-}
-
-/* Set the howto pointer for an ARC ELF reloc. */
-
-static bfd_boolean
-arc_info_to_howto_rel (bfd * abfd,
- arelent * cache_ptr,
- Elf_Internal_Rela * dst)
-{
- unsigned int r_type;
-
- r_type = ELF32_R_TYPE (dst->r_info);
- if (r_type >= (unsigned int) R_ARC_max)
- {
- /* xgettext:c-format */
- _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
- abfd, r_type);
- bfd_set_error (bfd_error_bad_value);
- return FALSE;
- }
-
- cache_ptr->howto = arc_elf_howto (r_type);
- return TRUE;
-}
-
-/* Extract CPU features from an NTBS. */
-
-static unsigned
-arc_extract_features (const char *p)
-{
- unsigned i, r = 0;
-
- if (!p)
- return 0;
-
- for (i = 0; i < ARRAY_SIZE (bfd_feature_list); i++)
- {
- char *t = strstr (p, bfd_feature_list[i].attr);
- unsigned l = strlen (bfd_feature_list[i].attr);
- if ((t != NULL)
- && (t[l] == ','
- || t[l] == '\0'))
- r |= bfd_feature_list[i].feature;
- }
-
- return r;
-}
-
-/* Concatenate two strings. s1 can be NULL but not
- s2. */
-
-static char *
-arc_stralloc (char * s1, const char * s2)
-{
- char *p;
-
- /* Only s1 can be null. */
- BFD_ASSERT (s2);
-
- p = s1 ? concat (s1, ",", s2, NULL) : (char *)s2;
-
- return p;
-}
-
-/* Merge ARC object attributes from IBFD into OBFD. Raise an error if
- there are conflicting attributes. */
-
-static bfd_boolean
-arc_elf_merge_attributes (bfd *ibfd, struct bfd_link_info *info)
-{
- bfd *obfd = info->output_bfd;
- obj_attribute *in_attr;
- obj_attribute *out_attr;
- int i;
- bfd_boolean result = TRUE;
- const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
- char *tagname = NULL;
-
- /* Skip the linker stubs file. This preserves previous behavior
- of accepting unknown attributes in the first input file - but
- is that a bug? */
- if (ibfd->flags & BFD_LINKER_CREATED)
- return TRUE;
-
- /* Skip any input that hasn't attribute section.
- This enables to link object files without attribute section with
- any others. */
- if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
- return TRUE;
-
- if (!elf_known_obj_attributes_proc (obfd)[0].i)
- {
- /* This is the first object. Copy the attributes. */
- _bfd_elf_copy_obj_attributes (ibfd, obfd);
-
- out_attr = elf_known_obj_attributes_proc (obfd);
-
- /* Use the Tag_null value to indicate the attributes have been
- initialized. */
- out_attr[0].i = 1;
-
- return TRUE;
- }
-
- in_attr = elf_known_obj_attributes_proc (ibfd);
- out_attr = elf_known_obj_attributes_proc (obfd);
-
- for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
- {
- /* Merge this attribute with existing attributes. */
- switch (i)
- {
- case Tag_ARC_PCS_config:
- if (out_attr[i].i == 0)
- out_attr[i].i = in_attr[i].i;
- else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
- {
- const char *tagval[] = { "Absent", "Bare-metal/mwdt",
- "Bare-metal/newlib", "Linux/uclibc",
- "Linux/glibc" };
- BFD_ASSERT (in_attr[i].i < 5);
- BFD_ASSERT (out_attr[i].i < 5);
- /* It's sometimes ok to mix different configs, so this is only
- a warning. */
- _bfd_error_handler
- (_("warning: %pB: conflicting platform configuration "
- "%s with %s"), ibfd,
- tagval[in_attr[i].i],
- tagval[out_attr[i].i]);
- }
- break;
-
- case Tag_ARC_CPU_base:
- if (out_attr[i].i == 0)
- out_attr[i].i = in_attr[i].i;
- else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i
- && ((out_attr[i].i + in_attr[i].i) < 6))
- {
- const char *tagval[] = { "Absent", "ARC6xx", "ARC7xx",
- "ARCEM", "ARCHS" };
- BFD_ASSERT (in_attr[i].i < 5);
- BFD_ASSERT (out_attr[i].i < 5);
- /* We cannot mix code for different CPUs. */
- _bfd_error_handler
- (_("error: %pB: unable to merge CPU base attributes "
- "%s with %s"),
- obfd,
- tagval[in_attr[i].i],
- tagval[out_attr[i].i]);
- result = FALSE;
- break;
- }
- else
- {
- /* The CPUs may be different, check if we can still mix
- the objects against the output choosen CPU. */
- unsigned in_feature = 0;
- unsigned out_feature = 0;
- char *p1 = in_attr[Tag_ARC_ISA_config].s;
- char *p2 = out_attr[Tag_ARC_ISA_config].s;
- unsigned j;
- unsigned cpu_out;
- unsigned opcode_map[] = {0, ARC_OPCODE_ARC600, ARC_OPCODE_ARC700,
- ARC_OPCODE_ARCv2EM, ARC_OPCODE_ARCv2HS};
-
- BFD_ASSERT (in_attr[i].i < (sizeof (opcode_map)
- / sizeof (unsigned)));
- BFD_ASSERT (out_attr[i].i < (sizeof (opcode_map)
- / sizeof (unsigned)));
- cpu_out = opcode_map[out_attr[i].i];
-
- in_feature = arc_extract_features (p1);
- out_feature = arc_extract_features (p2);
-
- /* First, check if a feature is compatible with the
- output object chosen CPU. */
- for (j = 0; j < ARRAY_SIZE (bfd_feature_list); j++)
- if (((in_feature | out_feature) & bfd_feature_list[j].feature)
- && (!(cpu_out & bfd_feature_list[j].cpus)))
- {
- _bfd_error_handler
- (_("error: %pB: unable to merge ISA extension attributes "
- "%s"),
- obfd, bfd_feature_list[j].name);
- result = FALSE;
- break;
- }
- /* Second, if we have compatible features with the
- chosen CPU, check if they are compatible among
- them. */
- for (j = 0; j < ARRAY_SIZE (bfd_conflict_list); j++)
- if (((in_feature | out_feature) & bfd_conflict_list[j])
- == bfd_conflict_list[j])
- {
- unsigned k;
- for (k = 0; k < ARRAY_SIZE (bfd_feature_list); k++)
- {
- if (in_feature & bfd_feature_list[k].feature
- & bfd_conflict_list[j])
- p1 = (char *) bfd_feature_list[k].name;
- if (out_feature & bfd_feature_list[k].feature
- & bfd_conflict_list[j])
- p2 = (char *) bfd_feature_list[k].name;
- }
- _bfd_error_handler
- (_("error: %pB: conflicting ISA extension attributes "
- "%s with %s"),
- obfd, p1, p2);
- result = FALSE;
- break;
- }
- /* Everithing is alright. */
- out_feature |= in_feature;
- p1 = NULL;
- for (j = 0; j < ARRAY_SIZE (bfd_feature_list); j++)
- if (out_feature & bfd_feature_list[j].feature)
- p1 = arc_stralloc (p1, bfd_feature_list[j].attr);
- if (p1)
- out_attr[Tag_ARC_ISA_config].s =
- _bfd_elf_attr_strdup (obfd, p1);
- }
- /* Fall through. */
- case Tag_ARC_CPU_variation:
- case Tag_ARC_ISA_mpy_option:
- case Tag_ARC_ABI_osver:
- /* Use the largest value specified. */
- if (in_attr[i].i > out_attr[i].i)
- out_attr[i].i = in_attr[i].i;
- break;
-
- /* The CPU name is given by the vendor, just choose an
- existing one if missing or different. There are no fail
- criteria if they different or both missing. */
- case Tag_ARC_CPU_name:
- if (!out_attr[i].s && in_attr[i].s)
- out_attr[i].s = _bfd_elf_attr_strdup (obfd, in_attr[i].s);
- break;
-
- case Tag_ARC_ABI_rf16:
- if (out_attr[i].i == 0)
- out_attr[i].i = in_attr[i].i;
- else if (out_attr[i].i != in_attr[i].i)
- {
- /* We cannot mix code with rf16 and without. */
- _bfd_error_handler
- (_("error: %pB: cannot mix rf16 with full register set %pB"),
- obfd, ibfd);
- result = FALSE;
- }
- break;
-
- case Tag_ARC_ABI_pic:
- tagname = "PIC";
- /* fall through */
- case Tag_ARC_ABI_sda:
- if (!tagname)
- tagname = "SDA";
- /* fall through */
- case Tag_ARC_ABI_tls:
- {
- const char *tagval[] = { "Absent", "MWDT", "GNU" };
-
- if (!tagname)
- tagname = "TLS";
-
- BFD_ASSERT (in_attr[i].i < 3);
- BFD_ASSERT (out_attr[i].i < 3);
- if (out_attr[i].i == 0)
- out_attr[i].i = in_attr[i].i;
- else if (out_attr[i].i != 0 && in_attr[i].i != 0
- && out_attr[i].i != in_attr[i].i)
- {
- _bfd_error_handler
- (_("error: %pB: conflicting attributes %s: %s with %s"),
- obfd, tagname,
- tagval[in_attr[i].i],
- tagval[out_attr[i].i]);
- result = FALSE;
- }
- tagname = NULL;
- break;
- }
-
- case Tag_ARC_ABI_double_size:
- tagname = "Double size";
- /* fall through */
- case Tag_ARC_ABI_enumsize:
- if (!tagname)
- tagname = "Enum size";
- /* fall through */
- case Tag_ARC_ABI_exceptions:
- if (!tagname)
- tagname = "ABI exceptions";
-
- if (out_attr[i].i == 0)
- out_attr[i].i = in_attr[i].i;
- else if (out_attr[i].i != 0 && in_attr[i].i != 0
- && out_attr[i].i != in_attr[i].i)
- {
- _bfd_error_handler
- (_("error: %pB: conflicting attributes %s"),
- obfd, tagname);
- result = FALSE;
- }
- break;
-
- case Tag_ARC_ISA_apex:
- break; /* Do nothing for APEX attributes. */
-
- case Tag_ARC_ISA_config:
- /* It is handled in Tag_ARC_CPU_base. */
- break;
-
- case Tag_ARC_ATR_version:
- if (out_attr[i].i == 0)
- out_attr[i].i = in_attr[i].i;
- break;
-
- default:
- result
- = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
- }
-
- /* If out_attr was copied from in_attr then it won't have a type yet. */
- if (in_attr[i].type && !out_attr[i].type)
- out_attr[i].type = in_attr[i].type;
- }
-
- /* Merge Tag_compatibility attributes and any common GNU ones. */
- if (!_bfd_elf_merge_object_attributes (ibfd, info))
- return FALSE;
-
- /* Check for any attributes not known on ARC. */
- result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
-
- return result;
-}
-
-/* Merge backend specific data from an object file to the output
- object file when linking. */
-
-static bfd_boolean
-arc_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
-{
- bfd *obfd = info->output_bfd;
- unsigned short mach_ibfd;
- static unsigned short mach_obfd = EM_NONE;
- flagword out_flags;
- flagword in_flags;
- asection *sec;
-
- /* Check if we have the same endianess. */
- if (! _bfd_generic_verify_endian_match (ibfd, info))
- return FALSE;
-
- if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour
- || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
- return TRUE;
-
- /* Collect ELF flags. */
- in_flags = elf_elfheader (ibfd)->e_flags & EF_ARC_MACH_MSK;
- out_flags = elf_elfheader (obfd)->e_flags & EF_ARC_MACH_MSK;
-
- if (!elf_flags_init (obfd)) /* First call, no flags set. */
- {
- elf_flags_init (obfd) = TRUE;
- out_flags = in_flags;
- }
-
- if (!arc_elf_merge_attributes (ibfd, info))
- return FALSE;
-
- /* Check to see if the input BFD actually contains any sections. Do
- not short-circuit dynamic objects; their section list may be
- emptied by elf_link_add_object_symbols. */
- if (!(ibfd->flags & DYNAMIC))
- {
- bfd_boolean null_input_bfd = TRUE;
- bfd_boolean only_data_sections = TRUE;
-
- for (sec = ibfd->sections; sec != NULL; sec = sec->next)
- {
- if ((bfd_section_flags (sec)
- & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
- == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
- only_data_sections = FALSE;
-
- null_input_bfd = FALSE;
- }
-
- if (null_input_bfd || only_data_sections)
- return TRUE;
- }
-
- /* Complain about various flag/architecture mismatches. */
- mach_ibfd = elf_elfheader (ibfd)->e_machine;
- if (mach_obfd == EM_NONE)
- {
- mach_obfd = mach_ibfd;
- }
- else
- {
- if (mach_ibfd != mach_obfd)
- {
- /* xgettext:c-format */
- _bfd_error_handler (_("error: attempting to link %pB "
- "with a binary %pB of different architecture"),
- ibfd, obfd);
- return FALSE;
- }
- else if ((in_flags != out_flags)
- /* If we have object attributes, then we already
- checked the objects compatibility, skip it. */
- && !bfd_elf_get_obj_attr_int (ibfd, OBJ_ATTR_PROC,
- Tag_ARC_CPU_base))
- {
- if (in_flags && out_flags)
- {
- /* Warn if different flags. */
- _bfd_error_handler
- /* xgettext:c-format */
- (_("%pB: uses different e_flags (%#x) fields than "
- "previous modules (%#x)"),
- ibfd, in_flags, out_flags);
- return FALSE;
- }
- /* MWDT doesnt set the eflags hence make sure we choose the
- eflags set by gcc. */
- in_flags = in_flags > out_flags ? in_flags : out_flags;
- }
- else
- {
- /* Everything is correct; don't change the output flags. */
- in_flags = out_flags;
- }
- }
-
- /* Update the flags. */
- elf_elfheader (obfd)->e_flags = in_flags;
-
- if (bfd_get_mach (obfd) < bfd_get_mach (ibfd))
- {
- return bfd_set_arch_mach (obfd, bfd_arch_arc, bfd_get_mach (ibfd));
- }
-
- return TRUE;
-}
-
-/* Return a best guess for the machine number based on the attributes. */
-
-static unsigned int
-bfd_arc_get_mach_from_attributes (bfd * abfd)
-{
- int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ARC_CPU_base);
- unsigned e_machine = elf_elfheader (abfd)->e_machine;
-
- switch (arch)
- {
- case TAG_CPU_ARC6xx:
- return bfd_mach_arc_arc600;
- case TAG_CPU_ARC7xx:
- return bfd_mach_arc_arc700;
- case TAG_CPU_ARCEM:
- case TAG_CPU_ARCHS:
- return bfd_mach_arc_arcv2;
- default:
- break;
- }
- return (e_machine == EM_ARC_COMPACT)
- ? bfd_mach_arc_arc700 : bfd_mach_arc_arcv2;
-}
-
-/* Set the right machine number for an ARC ELF file. */
-static bfd_boolean
-arc_elf_object_p (bfd * abfd)
-{
- /* Make sure this is initialised, or you'll have the potential of passing
- garbage---or misleading values---into the call to
- bfd_default_set_arch_mach (). */
- unsigned int mach = bfd_mach_arc_arc700;
- unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH_MSK;
- unsigned e_machine = elf_elfheader (abfd)->e_machine;
-
- if (e_machine == EM_ARC_COMPACT || e_machine == EM_ARC_COMPACT2)
- {
- switch (arch)
- {
- case E_ARC_MACH_ARC600:
- mach = bfd_mach_arc_arc600;
- break;
- case E_ARC_MACH_ARC601:
- mach = bfd_mach_arc_arc601;
- break;
- case E_ARC_MACH_ARC700:
- mach = bfd_mach_arc_arc700;
- break;
- case EF_ARC_CPU_ARCV2HS:
- case EF_ARC_CPU_ARCV2EM:
- mach = bfd_mach_arc_arcv2;
- break;
- default:
- mach = bfd_arc_get_mach_from_attributes (abfd);
- break;
- }
- }
- else
- {
- if (e_machine == EM_ARC)
- {
- _bfd_error_handler
- (_("error: the ARC4 architecture is no longer supported"));
- return FALSE;
- }
- else
- {
- _bfd_error_handler
- (_("warning: unset or old architecture flags; "
- "use default machine"));
- }
- }
-
- return bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach);
-}
-
-/* The final processing done just before writing out an ARC ELF object file.
- This gets the ARC architecture right based on the machine number. */
-
-static bfd_boolean
-arc_elf_final_write_processing (bfd *abfd)
-{
- unsigned long emf;
- int osver = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC,
- Tag_ARC_ABI_osver);
- flagword e_flags = elf_elfheader (abfd)->e_flags & ~EF_ARC_OSABI_MSK;
-
- switch (bfd_get_mach (abfd))
- {
- case bfd_mach_arc_arcv2:
- emf = EM_ARC_COMPACT2;
- break;
- default:
- emf = EM_ARC_COMPACT;
- break;
- }
-
- elf_elfheader (abfd)->e_machine = emf;
-
- /* Record whatever is the current syscall ABI version. */
- if (osver)
- e_flags |= ((osver & 0x0f) << 8);
- else
- e_flags |= E_ARC_OSABI_V3;
-
- elf_elfheader (abfd)->e_flags |= e_flags;
- return _bfd_elf_final_write_processing (abfd);
-}
-
-#ifdef ARC_ENABLE_DEBUG
-#define DEBUG_ARC_RELOC(A) debug_arc_reloc (A)
-
-static void
-debug_arc_reloc (struct arc_relocation_data reloc_data)
-{
- ARC_DEBUG ("Reloc type=%s, should_relocate = %s\n",
- reloc_data.howto->name,
- reloc_data.should_relocate ? "true" : "false");
- ARC_DEBUG (" offset = 0x%x, addend = 0x%x\n",
- (unsigned int) reloc_data.reloc_offset,
- (unsigned int) reloc_data.reloc_addend);
- ARC_DEBUG (" Symbol:\n");
- ARC_DEBUG (" value = 0x%08x\n",
- (unsigned int) reloc_data.sym_value);
- if (reloc_data.sym_section != NULL)
- {
- ARC_DEBUG (" Symbol Section:\n");
- ARC_DEBUG (" section name = %s, output_offset 0x%08x",
- reloc_data.sym_section->name,
- (unsigned int) reloc_data.sym_section->output_offset);
- if (reloc_data.sym_section->output_section != NULL)
- ARC_DEBUG (", output_section->vma = 0x%08x",
- ((unsigned int) reloc_data.sym_section->output_section->vma));
- ARC_DEBUG ("\n");
- if (reloc_data.sym_section->owner
- && reloc_data.sym_section->owner->filename)
- ARC_DEBUG (" file: %s\n", reloc_data.sym_section->owner->filename);
- }
- else
- {
- ARC_DEBUG (" symbol section is NULL\n");
- }
-
- ARC_DEBUG (" Input_section:\n");
- if (reloc_data.input_section != NULL)
- {
- ARC_DEBUG (" section name = %s, output_offset 0x%08x, output_section->vma = 0x%08x\n",
- reloc_data.input_section->name,
- (unsigned int) reloc_data.input_section->output_offset,
- (unsigned int) reloc_data.input_section->output_section->vma);
- ARC_DEBUG (" changed_address = 0x%08x\n",
- (unsigned int) (reloc_data.input_section->output_section->vma
- + reloc_data.input_section->output_offset
- + reloc_data.reloc_offset));
- ARC_DEBUG (" file: %s\n", reloc_data.input_section->owner->filename);
- }
- else
- {
- ARC_DEBUG (" input section is NULL\n");
- }
-}
-#else
-#define DEBUG_ARC_RELOC(A)
-#endif /* ARC_ENABLE_DEBUG */
-
-static bfd_vma
-middle_endian_convert (bfd_vma insn, bfd_boolean do_it)
-{
- if (do_it)
- {
- insn
- = ((insn & 0xffff0000) >> 16)
- | ((insn & 0xffff) << 16);
- }
- return insn;
-}
-
-/* This function is called for relocations that are otherwise marked as NOT
- requiring overflow checks. In here we perform non-standard checks of
- the relocation value. */
-
-static inline bfd_reloc_status_type
-arc_special_overflow_checks (const struct arc_relocation_data reloc_data,
- bfd_signed_vma relocation,
- struct bfd_link_info *info ATTRIBUTE_UNUSED)
-{
- switch (reloc_data.howto->type)
- {
- case R_ARC_NPS_CMEM16:
- if (((relocation >> 16) & 0xffff) != NPS_CMEM_HIGH_VALUE)
- {
- if (reloc_data.reloc_addend == 0)
- _bfd_error_handler
- /* xgettext:c-format */
- (_("%pB(%pA+%#" PRIx64 "): CMEM relocation to `%s' is invalid, "
- "16 MSB should be %#x (value is %#" PRIx64 ")"),
- reloc_data.input_section->owner,
- reloc_data.input_section,
- (uint64_t) reloc_data.reloc_offset,
- reloc_data.symbol_name,
- NPS_CMEM_HIGH_VALUE,
- (uint64_t) relocation);
- else
- _bfd_error_handler
- /* xgettext:c-format */
- (_("%pB(%pA+%#" PRIx64 "): CMEM relocation to `%s+%#" PRIx64
- "' is invalid, 16 MSB should be %#x (value is %#" PRIx64 ")"),
- reloc_data.input_section->owner,
- reloc_data.input_section,
- (uint64_t) reloc_data.reloc_offset,
- reloc_data.symbol_name,
- (uint64_t) reloc_data.reloc_addend,
- NPS_CMEM_HIGH_VALUE,
- (uint64_t) relocation);
- return bfd_reloc_overflow;
- }
- break;
-
- default:
- break;
- }
-
- return bfd_reloc_ok;
-}
-
-#define ME(reloc) (reloc)
-
-#define IS_ME(FORMULA,BFD) ((strstr (FORMULA, "ME") != NULL) \
- && (!bfd_big_endian (BFD)))
-
-#define S ((bfd_signed_vma) (reloc_data.sym_value \
- + (reloc_data.sym_section->output_section != NULL ? \
- (reloc_data.sym_section->output_offset \
- + reloc_data.sym_section->output_section->vma) : 0)))
-#define L ((bfd_signed_vma) (reloc_data.sym_value \
- + (reloc_data.sym_section->output_section != NULL ? \
- (reloc_data.sym_section->output_offset \
- + reloc_data.sym_section->output_section->vma) : 0)))
-#define A (reloc_data.reloc_addend)
-#define B (0)
-#define G (reloc_data.got_offset_value)
-#define GOT (reloc_data.got_symbol_vma)
-#define GOT_BEGIN (htab->sgot->output_section->vma)
-
-#define MES (0)
- /* P: relative offset to PCL The offset should be to the
- current location aligned to 32 bits. */
-#define P ((bfd_signed_vma) ( \
- ( \
- (reloc_data.input_section->output_section != NULL ? \
- reloc_data.input_section->output_section->vma : 0) \
- + reloc_data.input_section->output_offset \
- + (reloc_data.reloc_offset - (bitsize >= 32 ? 4 : 0))) \
- & ~0x3))
-#define PDATA ((bfd_signed_vma) ( \
- (reloc_data.input_section->output_section->vma \
- + reloc_data.input_section->output_offset \
- + (reloc_data.reloc_offset))))
-#define SECTSTART (bfd_signed_vma) (reloc_data.sym_section->output_section->vma \
- + reloc_data.sym_section->output_offset)
-#define FINAL_SECTSTART \
- (bfd_signed_vma) (reloc_data.sym_section->output_section->vma)
-#define JLI (bfd_signed_vma) (reloc_data.sym_section->output_section->vma)
-#define _SDA_BASE_ (bfd_signed_vma) (reloc_data.sdata_begin_symbol_vma)
-#define TLS_REL (bfd_signed_vma) \
- ((elf_hash_table (info))->tls_sec->output_section->vma)
-#define TLS_TBSS (align_power(TCB_SIZE, \
- reloc_data.sym_section->alignment_power))
-
-#define none (0)
-
-#ifdef ARC_ENABLE_DEBUG
-#define PRINT_DEBUG_RELOC_INFO_BEFORE(FORMULA, TYPE) \
- do \
- { \
- asection *sym_section = reloc_data.sym_section; \
- asection *input_section = reloc_data.input_section; \
- ARC_DEBUG ("RELOC_TYPE = " TYPE "\n"); \
- ARC_DEBUG ("FORMULA = " FORMULA "\n"); \
- ARC_DEBUG ("S = %#lx\n", S); \
- ARC_DEBUG ("A = %#lx\n", A); \
- ARC_DEBUG ("L = %lx\n", L); \
- if (sym_section->output_section != NULL) \
- ARC_DEBUG ("symbol_section->vma = %#lx\n", \
- sym_section->output_section->vma \
- + sym_section->output_offset); \
- else \
- ARC_DEBUG ("symbol_section->vma = NULL\n"); \
- if (input_section->output_section != NULL) \
- ARC_DEBUG ("input_section->vma = %#lx\n", \
- input_section->output_section->vma \
- + input_section->output_offset); \
- else \
- ARC_DEBUG ("input_section->vma = NULL\n"); \
- ARC_DEBUG ("PCL = %#lx\n", P); \
- ARC_DEBUG ("P = %#lx\n", P); \
- ARC_DEBUG ("G = %#lx\n", G); \
- ARC_DEBUG ("SDA_OFFSET = %#lx\n", _SDA_BASE_); \
- ARC_DEBUG ("SDA_SET = %d\n", reloc_data.sdata_begin_symbol_vma_set); \
- ARC_DEBUG ("GOT_OFFSET = %#lx\n", GOT); \
- ARC_DEBUG ("relocation = %#08lx\n", relocation); \
- ARC_DEBUG ("before = %#08x\n", (unsigned) insn); \
- ARC_DEBUG ("data = %08x (%u) (%d)\n", (unsigned) relocation, \
- (unsigned) relocation, (int) relocation); \
- } \
- while (0)
-
-#define PRINT_DEBUG_RELOC_INFO_AFTER \
- do \
- { \
- ARC_DEBUG ("after = 0x%08x\n", (unsigned int) insn); \
- } \
- while (0)
-
-#else
-
-#define PRINT_DEBUG_RELOC_INFO_BEFORE(...)
-#define PRINT_DEBUG_RELOC_INFO_AFTER
-
-#endif /* ARC_ENABLE_DEBUG */
-
-#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
- case R_##TYPE: \
- { \
- bfd_signed_vma bitsize ATTRIBUTE_UNUSED = BITSIZE; \
- relocation = FORMULA ; \
- PRINT_DEBUG_RELOC_INFO_BEFORE (#FORMULA, #TYPE); \
- insn = middle_endian_convert (insn, IS_ME (#FORMULA, abfd)); \
- insn = (* get_replace_function (abfd, TYPE)) (insn, relocation); \
- insn = middle_endian_convert (insn, IS_ME (#FORMULA, abfd)); \
- PRINT_DEBUG_RELOC_INFO_AFTER; \
- } \
- break;
-
-static bfd_reloc_status_type
-arc_do_relocation (bfd_byte * contents,
- struct arc_relocation_data reloc_data,
- struct bfd_link_info *info)
-{
- bfd_signed_vma relocation = 0;
- bfd_vma insn;
- bfd_vma orig_insn ATTRIBUTE_UNUSED;
- bfd * abfd = reloc_data.input_section->owner;
- struct elf_link_hash_table *htab ATTRIBUTE_UNUSED = elf_hash_table (info);
- bfd_reloc_status_type flag;
-
- if (!reloc_data.should_relocate)
- return bfd_reloc_ok;
-
- switch (reloc_data.howto->size)
- {
- case 2:
- insn = arc_bfd_get_32 (abfd,
- contents + reloc_data.reloc_offset,
- reloc_data.input_section);
- break;
- case 1:
- insn = arc_bfd_get_16 (abfd,
- contents + reloc_data.reloc_offset,
- reloc_data.input_section);
- break;
- case 0:
- insn = arc_bfd_get_8 (abfd,
- contents + reloc_data.reloc_offset,
- reloc_data.input_section);
- break;
- default:
- insn = 0;
- BFD_ASSERT (0);
- break;
- }
-
- orig_insn = insn;
-
- switch (reloc_data.howto->type)
- {
-#include "elf/arc-reloc.def"
-
- default:
- BFD_ASSERT (0);
- break;
- }
-
- /* Check for relocation overflow. */
- if (reloc_data.howto->complain_on_overflow != complain_overflow_dont)
- flag = bfd_check_overflow (reloc_data.howto->complain_on_overflow,
- reloc_data.howto->bitsize,
- reloc_data.howto->rightshift,
- bfd_arch_bits_per_address (abfd),
- relocation);
- else
- flag = arc_special_overflow_checks (reloc_data, relocation, info);
-
- if (flag != bfd_reloc_ok)
- {
- ARC_DEBUG ("Relocation overflows !\n");
- DEBUG_ARC_RELOC (reloc_data);
- ARC_DEBUG ("Relocation value = signed -> %d, unsigned -> %u"
- ", hex -> (0x%08x)\n",
- (int) relocation, (unsigned) relocation, (int) relocation);
-
- return flag;
- }
-
- /* Write updated instruction back to memory. */
- switch (reloc_data.howto->size)
- {
- case 2:
- arc_bfd_put_32 (abfd, insn,
- contents + reloc_data.reloc_offset,
- reloc_data.input_section);
- break;
- case 1:
- arc_bfd_put_16 (abfd, insn,
- contents + reloc_data.reloc_offset,
- reloc_data.input_section);
- break;
- case 0:
- arc_bfd_put_8 (abfd, insn,
- contents + reloc_data.reloc_offset,
- reloc_data.input_section);
- break;
- default:
- ARC_DEBUG ("size = %d\n", reloc_data.howto->size);
- BFD_ASSERT (0);
- break;
- }
-
- return bfd_reloc_ok;
-}
-#undef S
-#undef A
-#undef B
-#undef G
-#undef GOT
-#undef L
-#undef MES
-#undef P
-#undef SECTSTAR
-#undef SECTSTART
-#undef JLI
-#undef _SDA_BASE_
-#undef none
-
-#undef ARC_RELOC_HOWTO
-
-
-/* Relocate an arc ELF section.
- Function : elf_arc_relocate_section
- Brief : Relocate an arc section, by handling all the relocations
- appearing in that section.
- Args : output_bfd : The bfd being written to.
- info : Link information.
- input_bfd : The input bfd.
- input_section : The section being relocated.
- contents : contents of the section being relocated.
- relocs : List of relocations in the section.
- local_syms : is a pointer to the swapped in local symbols.
- local_section : is an array giving the section in the input file
- corresponding to the st_shndx field of each
- local symbol. */
-static bfd_boolean
-elf_arc_relocate_section (bfd * output_bfd,
- struct bfd_link_info * info,
- bfd * input_bfd,
- asection * input_section,
- bfd_byte * contents,
- Elf_Internal_Rela * relocs,
- Elf_Internal_Sym * local_syms,
- asection ** local_sections)
-{
- Elf_Internal_Shdr * symtab_hdr;
- struct elf_link_hash_entry ** sym_hashes;
- Elf_Internal_Rela * rel;
- Elf_Internal_Rela * wrel;
- Elf_Internal_Rela * relend;
- struct elf_link_hash_table * htab = elf_hash_table (info);
-
- symtab_hdr = &((elf_tdata (input_bfd))->symtab_hdr);
- sym_hashes = elf_sym_hashes (input_bfd);
-
- rel = wrel = relocs;
- relend = relocs + input_section->reloc_count;
- for (; rel < relend; wrel++, rel++)
- {
- enum elf_arc_reloc_type r_type;
- reloc_howto_type * howto;
- unsigned long r_symndx;
- struct elf_link_hash_entry * h;
- Elf_Internal_Sym * sym;
- asection * sec;
- struct elf_link_hash_entry * h2;
- const char * msg;
- bfd_boolean unresolved_reloc = FALSE;
-
- struct arc_relocation_data reloc_data =
- {
- .reloc_offset = 0,
- .reloc_addend = 0,
- .got_offset_value = 0,
- .sym_value = 0,
- .sym_section = NULL,
- .howto = NULL,
- .input_section = NULL,
- .sdata_begin_symbol_vma = 0,
- .sdata_begin_symbol_vma_set = FALSE,
- .got_symbol_vma = 0,
- .should_relocate = FALSE
- };
-
- r_type = ELF32_R_TYPE (rel->r_info);
-
- if (r_type >= (int) R_ARC_max)
- {
- bfd_set_error (bfd_error_bad_value);
- return FALSE;
- }
- howto = arc_elf_howto (r_type);
-
- r_symndx = ELF32_R_SYM (rel->r_info);
-
- /* If we are generating another .o file and the symbol in not
- local, skip this relocation. */
- if (bfd_link_relocatable (info))
- {
- /* This is a relocateable link. We don't have to change
- anything, unless the reloc is against a section symbol,
- in which case we have to adjust according to where the
- section symbol winds up in the output section. */
-
- /* Checks if this is a local symbol and thus the reloc
- might (will??) be against a section symbol. */
- if (r_symndx < symtab_hdr->sh_info)
- {
- sym = local_syms + r_symndx;
- if (ELF_ST_TYPE (sym->st_info) == STT_SECTION)
- {
- sec = local_sections[r_symndx];
-
- /* For RELA relocs. Just adjust the addend
- value in the relocation entry. */
- rel->r_addend += sec->output_offset + sym->st_value;
-
- ARC_DEBUG ("local symbols reloc (section=%d %s) seen in %s\n",
- (int) r_symndx, local_sections[r_symndx]->name,
- __PRETTY_FUNCTION__);
- }
- }
- }
-
- h2 = elf_link_hash_lookup (elf_hash_table (info), "__SDATA_BEGIN__",
- FALSE, FALSE, TRUE);
-
- if (!reloc_data.sdata_begin_symbol_vma_set
- && h2 != NULL && h2->root.type != bfd_link_hash_undefined
- && h2->root.u.def.section->output_section != NULL)
- /* TODO: Verify this condition. */
- {
- reloc_data.sdata_begin_symbol_vma =
- (h2->root.u.def.value
- + h2->root.u.def.section->output_section->vma);
- reloc_data.sdata_begin_symbol_vma_set = TRUE;
- }
-
- reloc_data.input_section = input_section;
- reloc_data.howto = howto;
- reloc_data.reloc_offset = rel->r_offset;
- reloc_data.reloc_addend = rel->r_addend;
-
- /* This is a final link. */
- h = NULL;
- sym = NULL;
- sec = NULL;
-
- if (r_symndx < symtab_hdr->sh_info) /* A local symbol. */
- {
- sym = local_syms + r_symndx;
- sec = local_sections[r_symndx];
- }
- else
- {
- bfd_boolean warned, ignored;
- bfd_vma relocation ATTRIBUTE_UNUSED;
-
- RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
- r_symndx, symtab_hdr, sym_hashes,
- h, sec, relocation,
- unresolved_reloc, warned, ignored);
-
- /* TODO: This code is repeated from below. We should
- clean it and remove duplications.
- Sec is used check for discarded sections.
- Need to redesign code below. */
-
- /* Get the symbol's entry in the symtab. */
- h = sym_hashes[r_symndx - symtab_hdr->sh_info];
-
- while (h->root.type == bfd_link_hash_indirect
- || h->root.type == bfd_link_hash_warning)
- h = (struct elf_link_hash_entry *) h->root.u.i.link;
-
- /* If we have encountered a definition for this symbol. */
- if (h->root.type == bfd_link_hash_defined
- || h->root.type == bfd_link_hash_defweak)
- {
- reloc_data.sym_value = h->root.u.def.value;
- sec = h->root.u.def.section;
- }
- }
-
- /* Clean relocs for symbols in discarded sections. */
- if (sec != NULL && discarded_section (sec))
- {
- _bfd_clear_contents (howto, input_bfd, input_section,
- contents, rel->r_offset);
- rel->r_info = 0;
- rel->r_addend = 0;
-
- /* For ld -r, remove relocations in debug sections against
- sections defined in discarded sections. Not done for
- eh_frame editing code expects to be present. */
- if (bfd_link_relocatable (info)
- && (input_section->flags & SEC_DEBUGGING))
- wrel--;
-
- continue;
- }
-
- if (bfd_link_relocatable (info))
- {
- if (wrel != rel)
- *wrel = *rel;
- continue;
- }
-
- if (r_symndx < symtab_hdr->sh_info) /* A local symbol. */
- {
- reloc_data.sym_value = sym->st_value;
- reloc_data.sym_section = sec;
- reloc_data.symbol_name =
- bfd_elf_string_from_elf_section (input_bfd,
- symtab_hdr->sh_link,
- sym->st_name);
-
- /* Mergeable section handling. */
- if ((sec->flags & SEC_MERGE)
- && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
- {
- asection *msec;
- msec = sec;
- rel->r_addend = _bfd_elf_rel_local_sym (output_bfd, sym,
- &msec, rel->r_addend);
- rel->r_addend -= (sec->output_section->vma
- + sec->output_offset
- + sym->st_value);
- rel->r_addend += msec->output_section->vma + msec->output_offset;
-
- reloc_data.reloc_addend = rel->r_addend;
- }
-
- BFD_ASSERT (htab->sgot != NULL || !is_reloc_for_GOT (howto));
- if (htab->sgot != NULL)
- reloc_data.got_symbol_vma = htab->sgot->output_section->vma
- + htab->sgot->output_offset;
-
- reloc_data.should_relocate = TRUE;
- }
- else /* Global symbol. */
- {
- /* FIXME: We should use the RELOC_FOR_GLOBAL_SYMBOL macro
- (defined in elf-bfd.h) here. */
-
- /* Get the symbol's entry in the symtab. */
- h = sym_hashes[r_symndx - symtab_hdr->sh_info];
-
- while (h->root.type == bfd_link_hash_indirect
- || h->root.type == bfd_link_hash_warning)
- {
- struct elf_arc_link_hash_entry *ah_old =
- (struct elf_arc_link_hash_entry *) h;
- h = (struct elf_link_hash_entry *) h->root.u.i.link;
- struct elf_arc_link_hash_entry *ah =
- (struct elf_arc_link_hash_entry *) h;
-
- if (ah->got_ents == 0 && ah_old->got_ents != ah->got_ents)
- ah->got_ents = ah_old->got_ents;
- }
-
- /* TODO: Need to validate what was the intention. */
- /* BFD_ASSERT ((h->dynindx == -1) || (h->forced_local != 0)); */
- reloc_data.symbol_name = h->root.root.string;
-
- /* If we have encountered a definition for this symbol. */
- if (h->root.type == bfd_link_hash_defined
- || h->root.type == bfd_link_hash_defweak)
- {
- reloc_data.sym_value = h->root.u.def.value;
- reloc_data.sym_section = h->root.u.def.section;
-
- reloc_data.should_relocate = TRUE;
-
- if (is_reloc_for_GOT (howto) && !bfd_link_pic (info))
- {
- struct elf_arc_link_hash_entry *ah =
- (struct elf_arc_link_hash_entry *) h;
- /* TODO: Change it to use arc_do_relocation with
- ARC_32 reloc. Try to use ADD_RELA macro. */
- bfd_vma relocation =
- reloc_data.sym_value + reloc_data.reloc_addend
- + (reloc_data.sym_section->output_section != NULL ?
- (reloc_data.sym_section->output_offset
- + reloc_data.sym_section->output_section->vma)
- : 0);
-
- BFD_ASSERT (ah->got_ents);
- bfd_vma got_offset = ah->got_ents->offset;
- bfd_put_32 (output_bfd, relocation,
- htab->sgot->contents + got_offset);
- }
- if (is_reloc_for_PLT (howto) && h->plt.offset != (bfd_vma) -1)
- {
- /* TODO: This is repeated up here. */
- reloc_data.sym_value = h->plt.offset;
- reloc_data.sym_section = htab->splt;
- }
- }
- else if (h->root.type == bfd_link_hash_undefweak)
- {
- /* Is weak symbol and has no definition. */
- if (is_reloc_for_GOT (howto))
- {
- reloc_data.sym_value = h->root.u.def.value;
- reloc_data.sym_section = htab->sgot;
- reloc_data.should_relocate = TRUE;
- }
- else if (is_reloc_for_PLT (howto)
- && h->plt.offset != (bfd_vma) -1)
- {
- /* TODO: This is repeated up here. */
- reloc_data.sym_value = h->plt.offset;
- reloc_data.sym_section = htab->splt;
- reloc_data.should_relocate = TRUE;
- }
- else
- continue;
- }
- else
- {
- if (is_reloc_for_GOT (howto))
- {
- reloc_data.sym_value = h->root.u.def.value;
- reloc_data.sym_section = htab->sgot;
-
- reloc_data.should_relocate = TRUE;
- }
- else if (is_reloc_for_PLT (howto))
- {
- /* Fail if it is linking for PIE and the symbol is
- undefined. */
- if (bfd_link_executable (info))
- (*info->callbacks->undefined_symbol)
- (info, h->root.root.string, input_bfd, input_section,
- rel->r_offset, TRUE);
- reloc_data.sym_value = h->plt.offset;
- reloc_data.sym_section = htab->splt;
-
- reloc_data.should_relocate = TRUE;
- }
- else if (!bfd_link_pic (info) || bfd_link_executable (info))
- (*info->callbacks->undefined_symbol)
- (info, h->root.root.string, input_bfd, input_section,
- rel->r_offset, TRUE);
- }
-
- BFD_ASSERT (htab->sgot != NULL || !is_reloc_for_GOT (howto));
- if (htab->sgot != NULL)
- reloc_data.got_symbol_vma = htab->sgot->output_section->vma
- + htab->sgot->output_offset;
- }
-
- if ((is_reloc_for_GOT (howto)
- || is_reloc_for_TLS (howto)))
- {
- reloc_data.should_relocate = TRUE;
-
- struct got_entry **list
- = get_got_entry_list_for_symbol (input_bfd, r_symndx, h);
-
- reloc_data.got_offset_value
- = relocate_fix_got_relocs_for_got_info (list,
- tls_type_for_reloc (howto),
- info,
- output_bfd,
- r_symndx,
- local_syms,
- local_sections,
- h,
- &reloc_data);
-
- if (h == NULL)
- {
- create_got_dynrelocs_for_single_entry (
- got_entry_for_type (list,
- arc_got_entry_type_for_reloc (howto)),
- output_bfd, info, NULL);
- }
- }
-
-
-#define IS_ARC_PCREL_TYPE(TYPE) \
- ( (TYPE == R_ARC_PC32) \
- || (TYPE == R_ARC_32_PCREL))
-
- switch (r_type)
- {
- case R_ARC_32:
- case R_ARC_32_ME:
- case R_ARC_PC32:
- case R_ARC_32_PCREL:
- if (bfd_link_pic (info)
- && (input_section->flags & SEC_ALLOC) != 0
- && (!IS_ARC_PCREL_TYPE (r_type)
- || (h != NULL
- && h->dynindx != -1
- && !h->def_regular
- && (!info->symbolic || !h->def_regular))))
- {
- Elf_Internal_Rela outrel;
- bfd_byte *loc;
- bfd_boolean skip = FALSE;
- bfd_boolean relocate = FALSE;
- asection *sreloc = _bfd_elf_get_dynamic_reloc_section
- (input_bfd, input_section,
- /*RELA*/ TRUE);
-
- BFD_ASSERT (sreloc != NULL);
-
- outrel.r_offset = _bfd_elf_section_offset (output_bfd,
- info,
- input_section,
- rel->r_offset);
-
- if (outrel.r_offset == (bfd_vma) -1)
- skip = TRUE;
-
- outrel.r_addend = rel->r_addend;
- outrel.r_offset += (input_section->output_section->vma
- + input_section->output_offset);
-
- if (skip)
- {
- memset (&outrel, 0, sizeof outrel);
- relocate = FALSE;
- }
- else if (h != NULL
- && h->dynindx != -1
- && (IS_ARC_PCREL_TYPE (r_type)
- || !(bfd_link_executable (info)
- || SYMBOLIC_BIND (info, h))
- || ! h->def_regular))
- {
- BFD_ASSERT (h != NULL);
- if ((input_section->flags & SEC_ALLOC) != 0)
- relocate = FALSE;
- else
- relocate = TRUE;
-
- BFD_ASSERT (h->dynindx != -1);
- outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
- }
- else
- {
- /* Handle local symbols, they either do not have a
- global hash table entry (h == NULL), or are
- forced local due to a version script
- (h->forced_local), or the third condition is
- legacy, it appears to say something like, for
- links where we are pre-binding the symbols, or
- there's not an entry for this symbol in the
- dynamic symbol table, and it's a regular symbol
- not defined in a shared object, then treat the
- symbol as local, resolve it now. */
- relocate = TRUE;
- /* outrel.r_addend = 0; */
- outrel.r_info = ELF32_R_INFO (0, R_ARC_RELATIVE);
- }
-
- BFD_ASSERT (sreloc->contents != 0);
-
- loc = sreloc->contents;
- loc += sreloc->reloc_count * sizeof (Elf32_External_Rela);
- sreloc->reloc_count += 1;
-
- bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
-
- if (!relocate)
- continue;
- }
- break;
- default:
- break;
- }
-
- if (is_reloc_SDA_relative (howto)
- && !reloc_data.sdata_begin_symbol_vma_set)
- {
- _bfd_error_handler
- ("error: linker symbol __SDATA_BEGIN__ not found");
- bfd_set_error (bfd_error_bad_value);
- return FALSE;
- }
-
- DEBUG_ARC_RELOC (reloc_data);
-
- /* Make sure we have with a dynamic linker. In case of GOT and PLT
- the sym_section should point to .got or .plt respectively. */
- if ((is_reloc_for_GOT (howto) || is_reloc_for_PLT (howto))
- && reloc_data.sym_section == NULL)
- {
- _bfd_error_handler
- (_("GOT and PLT relocations cannot be fixed with a non dynamic linker"));
- bfd_set_error (bfd_error_bad_value);
- return FALSE;
- }
-
- msg = NULL;
- switch (arc_do_relocation (contents, reloc_data, info))
- {
- case bfd_reloc_ok:
- continue; /* The reloc processing loop. */
-
- case bfd_reloc_overflow:
- (*info->callbacks->reloc_overflow)
- (info, (h ? &h->root : NULL), reloc_data.symbol_name, howto->name, (bfd_vma) 0,
- input_bfd, input_section, rel->r_offset);
- break;
-
- case bfd_reloc_undefined:
- (*info->callbacks->undefined_symbol)
- (info, reloc_data.symbol_name, input_bfd, input_section, rel->r_offset, TRUE);
- break;
-
- case bfd_reloc_other:
- /* xgettext:c-format */
- msg = _("%pB(%pA): warning: unaligned access to symbol '%s' in the small data area");
- break;
-
- case bfd_reloc_outofrange:
- /* xgettext:c-format */
- msg = _("%pB(%pA): internal error: out of range error");
- break;
-
- case bfd_reloc_notsupported:
- /* xgettext:c-format */
- msg = _("%pB(%pA): internal error: unsupported relocation error");
- break;
-
- case bfd_reloc_dangerous:
- /* xgettext:c-format */
- msg = _("%pB(%pA): internal error: dangerous relocation");
- break;
-
- default:
- /* xgettext:c-format */
- msg = _("%pB(%pA): internal error: unknown error");
- break;
- }
-
- if (msg)
- _bfd_error_handler (msg, input_bfd, input_section, reloc_data.symbol_name);
- return FALSE;
- }
-
- return TRUE;
-}
-
-#define elf_arc_hash_table(p) \
- (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \
- == ARC_ELF_DATA ? ((struct elf_arc_link_hash_table *) ((p)->hash)) : NULL)
-
-static bfd_boolean
-elf_arc_check_relocs (bfd * abfd,
- struct bfd_link_info * info,
- asection * sec,
- const Elf_Internal_Rela * relocs)
-{
- Elf_Internal_Shdr * symtab_hdr;
- struct elf_link_hash_entry ** sym_hashes;
- const Elf_Internal_Rela * rel;
- const Elf_Internal_Rela * rel_end;
- bfd * dynobj;
- asection * sreloc = NULL;
- struct elf_link_hash_table * htab = elf_hash_table (info);
-
- if (bfd_link_relocatable (info))
- return TRUE;
-
- if (htab->dynobj == NULL)
- htab->dynobj = abfd;
-
- dynobj = (elf_hash_table (info))->dynobj;
- symtab_hdr = &((elf_tdata (abfd))->symtab_hdr);
- sym_hashes = elf_sym_hashes (abfd);
-
- rel_end = relocs + sec->reloc_count;
- for (rel = relocs; rel < rel_end; rel++)
- {
- enum elf_arc_reloc_type r_type;
- reloc_howto_type *howto;
- unsigned long r_symndx;
- struct elf_link_hash_entry *h;
-
- r_type = ELF32_R_TYPE (rel->r_info);
-
- if (r_type >= (int) R_ARC_max)
- {
- bfd_set_error (bfd_error_bad_value);
- return FALSE;
- }
- howto = arc_elf_howto (r_type);
-
- /* Load symbol information. */
- r_symndx = ELF32_R_SYM (rel->r_info);
- if (r_symndx < symtab_hdr->sh_info) /* Is a local symbol. */
- h = NULL;
- else /* Global one. */
- {
- h = sym_hashes[r_symndx - symtab_hdr->sh_info];
- while (h->root.type == bfd_link_hash_indirect
- || h->root.type == bfd_link_hash_warning)
- h = (struct elf_link_hash_entry *) h->root.u.i.link;
- }
-
-
- switch (r_type)
- {
- case R_ARC_32:
- case R_ARC_32_ME:
- /* During shared library creation, these relocs should not
- appear in a shared library (as memory will be read only
- and the dynamic linker can not resolve these. However
- the error should not occur for e.g. debugging or
- non-readonly sections. */
- if (h != NULL
- && (bfd_link_dll (info) && !bfd_link_pie (info))
- && (sec->flags & SEC_ALLOC) != 0
- && (sec->flags & SEC_READONLY) != 0
- && ((sec->flags & SEC_CODE) != 0
- || (sec->flags & SEC_DEBUGGING) != 0))
- {
- const char *name;
- if (h)
- name = h->root.root.string;
- else
- name = "UNKNOWN";
- _bfd_error_handler
- /* xgettext:c-format */
- (_("%pB: relocation %s against `%s' can not be used"
- " when making a shared object; recompile with -fPIC"),
- abfd,
- arc_elf_howto (r_type)->name,
- name);
- bfd_set_error (bfd_error_bad_value);
- return FALSE;
- }
-
- /* In some cases we are not setting the 'non_got_ref'
- flag, even though the relocations don't require a GOT
- access. We should extend the testing in this area to
- ensure that no significant cases are being missed. */
- if (h)
- h->non_got_ref = 1;
- /* FALLTHROUGH */
- case R_ARC_PC32:
- case R_ARC_32_PCREL:
- if ((bfd_link_pic (info))
- && ((r_type != R_ARC_PC32 && r_type != R_ARC_32_PCREL)
- || (h != NULL
- && (!info->symbolic || !h->def_regular))))
- {
- if (sreloc == NULL)
- {
- if (info->dynamic
- && ! htab->dynamic_sections_created
- && ! _bfd_elf_link_create_dynamic_sections (abfd, info))
- return FALSE;
- sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj,
- 2, abfd,
- /*rela*/
- TRUE);
-
- if (sreloc == NULL)
- return FALSE;
- }
- sreloc->size += sizeof (Elf32_External_Rela);
-
- }
- default:
- break;
- }
-
- if (is_reloc_for_PLT (howto))
- {
- if (h == NULL)
- continue;
- else
- if (h->forced_local == 0)
- h->needs_plt = 1;
- }
-
- /* Add info to the symbol got_entry_list. */
- if (is_reloc_for_GOT (howto)
- || is_reloc_for_TLS (howto))
- {
- if (bfd_link_dll (info) && !bfd_link_pie (info)
- && (r_type == R_ARC_TLS_LE_32 || r_type == R_ARC_TLS_LE_S9))
- {
- const char *name;
- if (h)
- name = h->root.root.string;
- else
- /* bfd_elf_sym_name (abfd, symtab_hdr, isym, NULL); */
- name = "UNKNOWN";
- _bfd_error_handler
- /* xgettext:c-format */
- (_("%pB: relocation %s against `%s' can not be used"
- " when making a shared object; recompile with -fPIC"),
- abfd,
- arc_elf_howto (r_type)->name,
- name);
- bfd_set_error (bfd_error_bad_value);
- return FALSE;
- }
- if (! _bfd_elf_create_got_section (dynobj, info))
- return FALSE;
-
- arc_fill_got_info_for_reloc (
- arc_got_entry_type_for_reloc (howto),
- get_got_entry_list_for_symbol (abfd, r_symndx, h),
- info,
- h);
- }
- }
-
- return TRUE;
-}
-
-#define ELF_DYNAMIC_INTERPRETER "/sbin/ld-uClibc.so"
-
-static struct plt_version_t *
-arc_get_plt_version (struct bfd_link_info *info)
-{
- int i;
-
- for (i = 0; i < 1; i++)
- {
- ARC_DEBUG ("%d: size1 = %d, size2 = %d\n", i,
- (int) plt_versions[i].entry_size,
- (int) plt_versions[i].elem_size);
- }
-
- if (bfd_get_mach (info->output_bfd) == bfd_mach_arc_arcv2)
- {
- if (bfd_link_pic (info))
- return &(plt_versions[ELF_ARCV2_PIC]);
- else
- return &(plt_versions[ELF_ARCV2_ABS]);
- }
- else
- {
- if (bfd_link_pic (info))
- return &(plt_versions[ELF_ARC_PIC]);
- else
- return &(plt_versions[ELF_ARC_ABS]);
- }
-}
-
-static bfd_vma
-add_symbol_to_plt (struct bfd_link_info *info)
-{
- struct elf_link_hash_table *htab = elf_hash_table (info);
- bfd_vma ret;
-
- struct plt_version_t *plt_data = arc_get_plt_version (info);
-
- /* If this is the first .plt entry, make room for the special first
- entry. */
- if (htab->splt->size == 0)
- htab->splt->size += plt_data->entry_size;
-
- ret = htab->splt->size;
-
- htab->splt->size += plt_data->elem_size;
- ARC_DEBUG ("PLT_SIZE = %d\n", (int) htab->splt->size);
-
- htab->sgotplt->size += 4;
- htab->srelplt->size += sizeof (Elf32_External_Rela);
-
- return ret;
-}
-
-#define PLT_DO_RELOCS_FOR_ENTRY(ABFD, DS, RELOCS) \
- plt_do_relocs_for_symbol (ABFD, DS, RELOCS, 0, 0)
-
-static void
-plt_do_relocs_for_symbol (bfd *abfd,
- struct elf_link_hash_table *htab,
- const struct plt_reloc *reloc,
- bfd_vma plt_offset,
- bfd_vma symbol_got_offset)
-{
- while (SYM_ONLY (reloc->symbol) != LAST_RELOC)
- {
- bfd_vma relocation = 0;
-
- switch (SYM_ONLY (reloc->symbol))
- {
- case SGOT:
- relocation
- = htab->sgotplt->output_section->vma
- + htab->sgotplt->output_offset + symbol_got_offset;
- break;
- }
- relocation += reloc->addend;
-
- if (IS_RELATIVE (reloc->symbol))
- {
- bfd_vma reloc_offset = reloc->offset;
- reloc_offset -= (IS_INSN_32 (reloc->symbol)) ? 4 : 0;
- reloc_offset -= (IS_INSN_24 (reloc->symbol)) ? 2 : 0;
-
- relocation -= htab->splt->output_section->vma
- + htab->splt->output_offset
- + plt_offset + reloc_offset;
- }
-
- /* TODO: being ME is not a property of the relocation but of the
- section of which is applying the relocation. */
- if (IS_MIDDLE_ENDIAN (reloc->symbol) && !bfd_big_endian (abfd))
- {
- relocation
- = ((relocation & 0xffff0000) >> 16)
- | ((relocation & 0xffff) << 16);
- }
-
- switch (reloc->size)
- {
- case 32:
- bfd_put_32 (htab->splt->output_section->owner,
- relocation,
- htab->splt->contents + plt_offset + reloc->offset);
- break;
- }
-
- reloc = &(reloc[1]); /* Jump to next relocation. */
- }
-}
-
-static void
-relocate_plt_for_symbol (bfd *output_bfd,
- struct bfd_link_info *info,
- struct elf_link_hash_entry *h)
-{
- struct plt_version_t *plt_data = arc_get_plt_version (info);
- struct elf_link_hash_table *htab = elf_hash_table (info);
-
- bfd_vma plt_index = (h->plt.offset - plt_data->entry_size)
- / plt_data->elem_size;
- bfd_vma got_offset = (plt_index + 3) * 4;
-
- ARC_DEBUG ("arc_info: PLT_OFFSET = %#lx, PLT_ENTRY_VMA = %#lx, \
-GOT_ENTRY_OFFSET = %#lx, GOT_ENTRY_VMA = %#lx, for symbol %s\n",
- (long) h->plt.offset,
- (long) (htab->splt->output_section->vma
- + htab->splt->output_offset
- + h->plt.offset),
- (long) got_offset,
- (long) (htab->sgotplt->output_section->vma
- + htab->sgotplt->output_offset
- + got_offset),
- h->root.root.string);
-
- {
- bfd_vma i = 0;
- uint16_t *ptr = (uint16_t *) plt_data->elem;
-
- for (i = 0; i < plt_data->elem_size/2; i++)
- {
- uint16_t data = ptr[i];
- bfd_put_16 (output_bfd,
- (bfd_vma) data,
- htab->splt->contents + h->plt.offset + (i*2));
- }
- }
-
- plt_do_relocs_for_symbol (output_bfd, htab,
- plt_data->elem_relocs,
- h->plt.offset,
- got_offset);
-
- /* Fill in the entry in the global offset table. */
- bfd_put_32 (output_bfd,
- (bfd_vma) (htab->splt->output_section->vma
- + htab->splt->output_offset),
- htab->sgotplt->contents + got_offset);
-
- /* TODO: Fill in the entry in the .rela.plt section. */
- {
- Elf_Internal_Rela rel;
- bfd_byte *loc;
-
- rel.r_offset = (htab->sgotplt->output_section->vma
- + htab->sgotplt->output_offset
- + got_offset);
- rel.r_addend = 0;
-
- BFD_ASSERT (h->dynindx != -1);
- rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_JMP_SLOT);
-
- loc = htab->srelplt->contents;
- loc += plt_index * sizeof (Elf32_External_Rela); /* relA */
- bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
- }
-}
-
-static void
-relocate_plt_for_entry (bfd *abfd,
- struct bfd_link_info *info)
-{
- struct plt_version_t *plt_data = arc_get_plt_version (info);
- struct elf_link_hash_table *htab = elf_hash_table (info);
-
- {
- bfd_vma i = 0;
- uint16_t *ptr = (uint16_t *) plt_data->entry;
- for (i = 0; i < plt_data->entry_size/2; i++)
- {
- uint16_t data = ptr[i];
- bfd_put_16 (abfd,
- (bfd_vma) data,
- htab->splt->contents + (i*2));
- }
- }
- PLT_DO_RELOCS_FOR_ENTRY (abfd, htab, plt_data->entry_relocs);
-}
-
-/* Desc : Adjust a symbol defined by a dynamic object and referenced
- by a regular object. The current definition is in some section of
- the dynamic object, but we're not including those sections. We
- have to change the definition to something the rest of the link can
- understand. */
-
-static bfd_boolean
-elf_arc_adjust_dynamic_symbol (struct bfd_link_info *info,
- struct elf_link_hash_entry *h)
-{
- asection *s;
- bfd *dynobj = (elf_hash_table (info))->dynobj;
- struct elf_link_hash_table *htab = elf_hash_table (info);
-
- if (h->type == STT_FUNC
- || h->type == STT_GNU_IFUNC
- || h->needs_plt == 1)
- {
- if (!bfd_link_pic (info) && !h->def_dynamic && !h->ref_dynamic)
- {
- /* This case can occur if we saw a PLT32 reloc in an input
- file, but the symbol was never referred to by a dynamic
- object. In such a case, we don't actually need to build
- a procedure linkage table, and we can just do a PC32
- reloc instead. */
- BFD_ASSERT (h->needs_plt);
- return TRUE;
- }
-
- /* Make sure this symbol is output as a dynamic symbol. */
- if (h->dynindx == -1 && !h->forced_local
- && !bfd_elf_link_record_dynamic_symbol (info, h))
- return FALSE;
-
- if (bfd_link_pic (info)
- || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
- {
- bfd_vma loc = add_symbol_to_plt (info);
-
- if (bfd_link_executable (info) && !h->def_regular)
- {
- h->root.u.def.section = htab->splt;
- h->root.u.def.value = loc;
- }
- h->plt.offset = loc;
- }
- else
- {
- h->plt.offset = (bfd_vma) -1;
- h->needs_plt = 0;
- }
- return TRUE;
- }
-
- /* If this is a weak symbol, and there is a real definition, the
- processor independent code will have arranged for us to see the
- real definition first, and we can just use the same value. */
- if (h->is_weakalias)
- {
- struct elf_link_hash_entry *def = weakdef (h);
- BFD_ASSERT (def->root.type == bfd_link_hash_defined);
- h->root.u.def.section = def->root.u.def.section;
- h->root.u.def.value = def->root.u.def.value;
- return TRUE;
- }
-
- /* This is a reference to a symbol defined by a dynamic object which
- is not a function. */
-
- /* If we are creating a shared library, we must presume that the
- only references to the symbol are via the global offset table.
- For such cases we need not do anything here; the relocations will
- be handled correctly by relocate_section. */
- if (!bfd_link_executable (info))
- return TRUE;
-
- /* If there are no non-GOT references, we do not need a copy
- relocation. */
- if (!h->non_got_ref)
- return TRUE;
-
- /* If -z nocopyreloc was given, we won't generate them either. */
- if (info->nocopyreloc)
- {
- h->non_got_ref = 0;
- return TRUE;
- }
-
- /* We must allocate the symbol in our .dynbss section, which will
- become part of the .bss section of the executable. There will be
- an entry for this symbol in the .dynsym section. The dynamic
- object will contain position independent code, so all references
- from the dynamic object to this symbol will go through the global
- offset table. The dynamic linker will use the .dynsym entry to
- determine the address it must put in the global offset table, so
- both the dynamic object and the regular object will refer to the
- same memory location for the variable. */
-
- if (htab == NULL)
- return FALSE;
-
- /* We must generate a R_ARC_COPY reloc to tell the dynamic linker to
- copy the initial value out of the dynamic object and into the
- runtime process image. We need to remember the offset into the
- .rela.bss section we are going to use. */
- if ((h->root.u.def.section->flags & SEC_ALLOC) != 0)
- {
- struct elf_arc_link_hash_table *arc_htab = elf_arc_hash_table (info);
-
- BFD_ASSERT (arc_htab->elf.srelbss != NULL);
- arc_htab->elf.srelbss->size += sizeof (Elf32_External_Rela);
- h->needs_copy = 1;
- }
-
- /* TODO: Move this also to arc_hash_table. */
- s = bfd_get_section_by_name (dynobj, ".dynbss");
- BFD_ASSERT (s != NULL);
-
- return _bfd_elf_adjust_dynamic_copy (info, h, s);
-}
-
-/* Function : elf_arc_finish_dynamic_symbol
- Brief : Finish up dynamic symbol handling. We set the
- contents of various dynamic sections here.
- Args : output_bfd :
- info :
- h :
- sym :
- Returns : True/False as the return status. */
-
-static bfd_boolean
-elf_arc_finish_dynamic_symbol (bfd * output_bfd,
- struct bfd_link_info *info,
- struct elf_link_hash_entry *h,
- Elf_Internal_Sym * sym)
-{
- if (h->plt.offset != (bfd_vma) -1)
- {
- relocate_plt_for_symbol (output_bfd, info, h);
-
- if (!h->def_regular)
- {
- /* Mark the symbol as undefined, rather than as defined in
- the .plt section. Leave the value alone. */
- sym->st_shndx = SHN_UNDEF;
- }
- }
-
-
- /* This function traverses list of GOT entries and
- create respective dynamic relocs. */
- /* TODO: Make function to get list and not access the list directly. */
- /* TODO: Move function to relocate_section create this relocs eagerly. */
- struct elf_arc_link_hash_entry *ah =
- (struct elf_arc_link_hash_entry *) h;
- create_got_dynrelocs_for_got_info (&ah->got_ents,
- output_bfd,
- info,
- h);
-
- if (h->needs_copy)
- {
- struct elf_arc_link_hash_table *arc_htab = elf_arc_hash_table (info);
-
- if (arc_htab == NULL)
- return FALSE;
-
- if (h->dynindx == -1
- || (h->root.type != bfd_link_hash_defined
- && h->root.type != bfd_link_hash_defweak)
- || arc_htab->elf.srelbss == NULL)
- abort ();
-
- bfd_vma rel_offset = (h->root.u.def.value
- + h->root.u.def.section->output_section->vma
- + h->root.u.def.section->output_offset);
-
- bfd_byte * loc = arc_htab->elf.srelbss->contents
- + (arc_htab->elf.srelbss->reloc_count * sizeof (Elf32_External_Rela));
- arc_htab->elf.srelbss->reloc_count++;
-
- Elf_Internal_Rela rel;
- rel.r_addend = 0;
- rel.r_offset = rel_offset;
-
- BFD_ASSERT (h->dynindx != -1);
- rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_COPY);
-
- bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
- }
-
- /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. */
- if (strcmp (h->root.root.string, "_DYNAMIC") == 0
- || strcmp (h->root.root.string, "__DYNAMIC") == 0
- || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
- sym->st_shndx = SHN_ABS;
-
- return TRUE;
-}
-
-#define GET_SYMBOL_OR_SECTION(TAG, SYMBOL, SECTION) \
- case TAG: \
- if (SYMBOL != NULL) \
- h = elf_link_hash_lookup (elf_hash_table (info), \
- SYMBOL, FALSE, FALSE, TRUE); \
- else if (SECTION != NULL) \
- s = bfd_get_linker_section (dynobj, SECTION); \
- break;
-
-
-struct obfd_info_group {
- bfd *output_bfd;
- struct bfd_link_info *info;
-};
-
-static bfd_boolean
-arc_create_forced_local_got_entries_for_tls (struct bfd_hash_entry *bh,
- void *data)
-{
- struct elf_arc_link_hash_entry * h =
- (struct elf_arc_link_hash_entry *) bh;
- struct obfd_info_group *tmp = (struct obfd_info_group *) data;
-
- if (h->got_ents != NULL)
- {
- BFD_ASSERT (h);
-
- struct got_entry *list = h->got_ents;
-
- while (list != NULL)
- {
- create_got_dynrelocs_for_single_entry (list, tmp->output_bfd,
- tmp->info,
- (struct elf_link_hash_entry *) h);
- list = list->next;
- }
- }
-
- return TRUE;
-}
-
-
-/* Function : elf_arc_finish_dynamic_sections
- Brief : Finish up the dynamic sections handling.
- Args : output_bfd :
- info :
- h :
- sym :
- Returns : True/False as the return status. */
-
-static bfd_boolean
-elf_arc_finish_dynamic_sections (bfd * output_bfd,
- struct bfd_link_info *info)
-{
- struct elf_link_hash_table *htab = elf_hash_table (info);
- bfd *dynobj = (elf_hash_table (info))->dynobj;
- asection *sdyn = bfd_get_linker_section (dynobj, ".dynamic");
-
- if (sdyn)
- {
- Elf32_External_Dyn *dyncon, *dynconend;
-
- dyncon = (Elf32_External_Dyn *) sdyn->contents;
- dynconend
- = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
- for (; dyncon < dynconend; dyncon++)
- {
- Elf_Internal_Dyn internal_dyn;
- bfd_boolean do_it = FALSE;
-
- struct elf_link_hash_entry *h = NULL;
- asection *s = NULL;
-
- bfd_elf32_swap_dyn_in (dynobj, dyncon, &internal_dyn);
-
- switch (internal_dyn.d_tag)
- {
- GET_SYMBOL_OR_SECTION (DT_INIT, info->init_function, NULL)
- GET_SYMBOL_OR_SECTION (DT_FINI, info->fini_function, NULL)
- GET_SYMBOL_OR_SECTION (DT_PLTGOT, NULL, ".plt")
- GET_SYMBOL_OR_SECTION (DT_JMPREL, NULL, ".rela.plt")
- GET_SYMBOL_OR_SECTION (DT_PLTRELSZ, NULL, ".rela.plt")
- GET_SYMBOL_OR_SECTION (DT_VERSYM, NULL, ".gnu.version")
- GET_SYMBOL_OR_SECTION (DT_VERDEF, NULL, ".gnu.version_d")
- GET_SYMBOL_OR_SECTION (DT_VERNEED, NULL, ".gnu.version_r")
- default:
- break;
- }
-
- /* In case the dynamic symbols should be updated with a symbol. */
- if (h != NULL
- && (h->root.type == bfd_link_hash_defined
- || h->root.type == bfd_link_hash_defweak))
- {
- asection *asec_ptr;
-
- internal_dyn.d_un.d_val = h->root.u.def.value;
- asec_ptr = h->root.u.def.section;
- if (asec_ptr->output_section != NULL)
- {
- internal_dyn.d_un.d_val +=
- (asec_ptr->output_section->vma
- + asec_ptr->output_offset);
- }
- else
- {
- /* The symbol is imported from another shared
- library and does not apply to this one. */
- internal_dyn.d_un.d_val = 0;
- }
- do_it = TRUE;
- }
- else if (s != NULL) /* With a section information. */
- {
- switch (internal_dyn.d_tag)
- {
- case DT_PLTGOT:
- case DT_JMPREL:
- case DT_VERSYM:
- case DT_VERDEF:
- case DT_VERNEED:
- internal_dyn.d_un.d_ptr = (s->output_section->vma
- + s->output_offset);
- do_it = TRUE;
- break;
-
- case DT_PLTRELSZ:
- internal_dyn.d_un.d_val = s->size;
- do_it = TRUE;
- break;
-
- default:
- break;
- }
- }
-
- if (do_it)
- bfd_elf32_swap_dyn_out (output_bfd, &internal_dyn, dyncon);
- }
-
- if (htab->splt->size > 0)
- {
- relocate_plt_for_entry (output_bfd, info);
- }
-
- /* TODO: Validate this. */
- if (htab->srelplt->output_section != bfd_abs_section_ptr)
- elf_section_data (htab->srelplt->output_section)
- ->this_hdr.sh_entsize = 12;
- }
-
- /* Fill in the first three entries in the global offset table. */
- if (htab->sgot)
- {
- struct elf_link_hash_entry *h;
- h = elf_link_hash_lookup (elf_hash_table (info), "_GLOBAL_OFFSET_TABLE_",
- FALSE, FALSE, TRUE);
-
- if (h != NULL && h->root.type != bfd_link_hash_undefined
- && h->root.u.def.section != NULL)
- {
- asection *sec = h->root.u.def.section;
-
- if (sdyn == NULL)
- bfd_put_32 (output_bfd, (bfd_vma) 0,
- sec->contents);
- else
- bfd_put_32 (output_bfd,
- sdyn->output_section->vma + sdyn->output_offset,
- sec->contents);
- bfd_put_32 (output_bfd, (bfd_vma) 0, sec->contents + 4);
- bfd_put_32 (output_bfd, (bfd_vma) 0, sec->contents + 8);
- }
- }
-
- struct obfd_info_group group;
- group.output_bfd = output_bfd;
- group.info = info;
- bfd_hash_traverse (&info->hash->table,
- arc_create_forced_local_got_entries_for_tls, &group);
-
- return TRUE;
-}
-
-#define ADD_DYNAMIC_SYMBOL(NAME, TAG) \
- h = elf_link_hash_lookup (elf_hash_table (info), \
- NAME, FALSE, FALSE, FALSE); \
- if ((h != NULL && (h->ref_regular || h->def_regular))) \
- if (! _bfd_elf_add_dynamic_entry (info, TAG, 0)) \
- return FALSE;
-
-/* Set the sizes of the dynamic sections. */
-static bfd_boolean
-elf_arc_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
- struct bfd_link_info *info)
-{
- bfd *dynobj;
- asection *s;
- bfd_boolean relocs_exist = FALSE;
- struct elf_link_hash_table *htab = elf_hash_table (info);
-
- dynobj = htab->dynobj;
- BFD_ASSERT (dynobj != NULL);
-
- if (htab->dynamic_sections_created)
- {
- struct elf_link_hash_entry *h;
-
- /* Set the contents of the .interp section to the
- interpreter. */
- if (bfd_link_executable (info) && !info->nointerp)
- {
- s = bfd_get_section_by_name (dynobj, ".interp");
- BFD_ASSERT (s != NULL);
- s->size = sizeof (ELF_DYNAMIC_INTERPRETER);
- s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
- }
-
- /* Add some entries to the .dynamic section. We fill in some of
- the values later, in elf_bfd_final_link, but we must add the
- entries now so that we know the final size of the .dynamic
- section. Checking if the .init section is present. We also
- create DT_INIT and DT_FINI entries if the init_str has been
- changed by the user. */
- ADD_DYNAMIC_SYMBOL (info->init_function, DT_INIT);
- ADD_DYNAMIC_SYMBOL (info->fini_function, DT_FINI);
- }
- else
- {
- /* We may have created entries in the .rela.got section.
- However, if we are not creating the dynamic sections, we will
- not actually use these entries. Reset the size of .rela.got,
- which will cause it to get stripped from the output file
- below. */
- if (htab->srelgot != NULL)
- htab->srelgot->size = 0;
- }
-
- for (s = dynobj->sections; s != NULL; s = s->next)
- {
- if ((s->flags & SEC_LINKER_CREATED) == 0)
- continue;
-
- if (s == htab->splt
- || s == htab->sgot
- || s == htab->sgotplt
- || s == htab->sdynbss)
- {
- /* Strip this section if we don't need it. */
- }
- else if (strncmp (s->name, ".rela", 5) == 0)
- {
- if (s->size != 0 && s != htab->srelplt)
- relocs_exist = TRUE;
-
- /* We use the reloc_count field as a counter if we need to
- copy relocs into the output file. */
- s->reloc_count = 0;
- }
- else
- {
- /* It's not one of our sections, so don't allocate space. */
- continue;
- }
-
- if (s->size == 0)
- {
- s->flags |= SEC_EXCLUDE;
- continue;
- }
-
- if ((s->flags & SEC_HAS_CONTENTS) == 0)
- continue;
-
- /* Allocate memory for the section contents. */
- s->contents = bfd_zalloc (dynobj, s->size);
- if (s->contents == NULL)
- return FALSE;
- }
-
- return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs_exist);
-}
-
-
-/* Classify dynamic relocs such that -z combreloc can reorder and combine
- them. */
-static enum elf_reloc_type_class
-elf32_arc_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
- const asection *rel_sec ATTRIBUTE_UNUSED,
- const Elf_Internal_Rela *rela)
-{
- switch ((int) ELF32_R_TYPE (rela->r_info))
- {
- case R_ARC_RELATIVE:
- return reloc_class_relative;
- case R_ARC_JMP_SLOT:
- return reloc_class_plt;
- case R_ARC_COPY:
- return reloc_class_copy;
- /* TODO: Needed in future to support ifunc. */
- /*
- case R_ARC_IRELATIVE:
- return reloc_class_ifunc;
- */
- default:
- return reloc_class_normal;
- }
-}
-
-const struct elf_size_info arc_elf32_size_info =
-{
- sizeof (Elf32_External_Ehdr),
- sizeof (Elf32_External_Phdr),
- sizeof (Elf32_External_Shdr),
- sizeof (Elf32_External_Rel),
- sizeof (Elf32_External_Rela),
- sizeof (Elf32_External_Sym),
- sizeof (Elf32_External_Dyn),
- sizeof (Elf_External_Note),
- 4,
- 1,
- 32, 2,
- ELFCLASS32, EV_CURRENT,
- bfd_elf32_write_out_phdrs,
- bfd_elf32_write_shdrs_and_ehdr,
- bfd_elf32_checksum_contents,
- bfd_elf32_write_relocs,
- bfd_elf32_swap_symbol_in,
- bfd_elf32_swap_symbol_out,
- bfd_elf32_slurp_reloc_table,
- bfd_elf32_slurp_symbol_table,
- bfd_elf32_swap_dyn_in,
- bfd_elf32_swap_dyn_out,
- bfd_elf32_swap_reloc_in,
- bfd_elf32_swap_reloc_out,
- bfd_elf32_swap_reloca_in,
- bfd_elf32_swap_reloca_out
-};
-
-#define elf_backend_size_info arc_elf32_size_info
-
-/* GDB expects general purpose registers to be in section .reg. However Linux
- kernel doesn't create this section and instead writes registers to NOTE
- section. It is up to the binutils to create a pseudo-section .reg from the
- contents of NOTE. Also BFD will read pid and signal number from NOTE. This
- function relies on offsets inside elf_prstatus structure in Linux to be
- stable. */
-
-static bfd_boolean
-elf32_arc_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
-{
- int offset;
- size_t size;
-
- switch (note->descsz)
- {
- default:
- return FALSE;
-
- case 236: /* sizeof (struct elf_prstatus) on Linux/arc. */
- /* pr_cursig */
- elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
- /* pr_pid */
- elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
- /* pr_regs */
- offset = 72;
- size = (40 * 4); /* There are 40 registers in user_regs_struct. */
- break;
- }
- /* Make a ".reg/999" section. */
- return _bfd_elfcore_make_pseudosection (abfd, ".reg", size,
- note->descpos + offset);
-}
-
-/* Determine whether an object attribute tag takes an integer, a
- string or both. */
-
-static int
-elf32_arc_obj_attrs_arg_type (int tag)
-{
- if (tag == Tag_ARC_CPU_name
- || tag == Tag_ARC_ISA_config
- || tag == Tag_ARC_ISA_apex)
- return ATTR_TYPE_FLAG_STR_VAL;
- else if (tag < (Tag_ARC_ISA_mpy_option + 1))
- return ATTR_TYPE_FLAG_INT_VAL;
- else
- return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
-}
-
-/* Attribute numbers >=14 can be safely ignored. */
-
-static bfd_boolean
-elf32_arc_obj_attrs_handle_unknown (bfd *abfd, int tag)
-{
- if ((tag & 127) < (Tag_ARC_ISA_mpy_option + 1))
- {
- _bfd_error_handler
- (_("%pB: unknown mandatory ARC object attribute %d"),
- abfd, tag);
- bfd_set_error (bfd_error_bad_value);
- return FALSE;
- }
- else
- {
- _bfd_error_handler
- (_("warning: %pB: unknown ARC object attribute %d"),
- abfd, tag);
- return TRUE;
- }
-}
-
-/* Handle an ARC specific section when reading an object file. This is
- called when bfd_section_from_shdr finds a section with an unknown
- type. */
-
-static bfd_boolean
-elf32_arc_section_from_shdr (bfd *abfd,
- Elf_Internal_Shdr * hdr,
- const char *name,
- int shindex)
-{
- switch (hdr->sh_type)
- {
- case 0x0c: /* MWDT specific section, don't complain about it. */
- case SHT_ARC_ATTRIBUTES:
- break;
-
- default:
- return FALSE;
- }
-
- if (!_bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
- return FALSE;
-
- return TRUE;
-}
-
-/* Relaxation hook.
-
- These are the current relaxing opportunities available:
-
- * R_ARC_GOTPC32 => R_ARC_PCREL.
-
-*/
-
-static bfd_boolean
-arc_elf_relax_section (bfd *abfd, asection *sec,
- struct bfd_link_info *link_info, bfd_boolean *again)
-{
- Elf_Internal_Shdr *symtab_hdr;
- Elf_Internal_Rela *internal_relocs;
- Elf_Internal_Rela *irel, *irelend;
- bfd_byte *contents = NULL;
- Elf_Internal_Sym *isymbuf = NULL;
-
- /* Assume nothing changes. */
- *again = FALSE;
-
- /* We don't have to do anything for a relocatable link, if this
- section does not have relocs, or if this is not a code
- section. */
- if (bfd_link_relocatable (link_info)
- || (sec->flags & SEC_RELOC) == 0
- || sec->reloc_count == 0
- || (sec->flags & SEC_CODE) == 0)
- return TRUE;
-
- symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
-
- /* Get a copy of the native relocations. */
- internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL,
- link_info->keep_memory);
- if (internal_relocs == NULL)
- goto error_return;
-
- /* Walk through them looking for relaxing opportunities. */
- irelend = internal_relocs + sec->reloc_count;
- for (irel = internal_relocs; irel < irelend; irel++)
- {
- /* If this isn't something that can be relaxed, then ignore
- this reloc. */
- if (ELF32_R_TYPE (irel->r_info) != (int) R_ARC_GOTPC32)
- continue;
-
- /* Get the section contents if we haven't done so already. */
- if (contents == NULL)
- {
- /* Get cached copy if it exists. */
- if (elf_section_data (sec)->this_hdr.contents != NULL)
- contents = elf_section_data (sec)->this_hdr.contents;
- /* Go get them off disk. */
- else if (!bfd_malloc_and_get_section (abfd, sec, &contents))
- goto error_return;
- }
-
- /* Read this BFD's local symbols if we haven't done so already. */
- if (isymbuf == NULL && symtab_hdr->sh_info != 0)
- {
- isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
- if (isymbuf == NULL)
- isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
- symtab_hdr->sh_info, 0,
- NULL, NULL, NULL);
- if (isymbuf == NULL)
- goto error_return;
- }
-
- struct elf_link_hash_entry *htop = NULL;
-
- if (ELF32_R_SYM (irel->r_info) >= symtab_hdr->sh_info)
- {
- /* An external symbol. */
- unsigned int indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
- htop = elf_sym_hashes (abfd)[indx];
- }
-
- if (ELF32_R_TYPE (irel->r_info) == (int) R_ARC_GOTPC32
- && SYMBOL_REFERENCES_LOCAL (link_info, htop))
- {
- unsigned int code;
-
- /* Get the opcode. */
- code = bfd_get_32_me (abfd, contents + irel->r_offset - 4);
-
- /* Note that we've changed the relocs, section contents, etc. */
- elf_section_data (sec)->relocs = internal_relocs;
- elf_section_data (sec)->this_hdr.contents = contents;
- symtab_hdr->contents = (unsigned char *) isymbuf;
-
- /* Fix the relocation's type. */
- irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_ARC_PC32);
-
- /* ld rA,[pcl,symbol@tgot] -> add rA,pcl,symbol@pcl. */
- /* 0010 0bbb aa11 0ZZX DBBB 1111 10AA AAAA.
- 111 00 000 0111 xx xxxx*/
- code &= ~0x27307F80;
- BFD_ASSERT (code <= 62UL);
- code |= 0x27007F80;
-
- /* Write back the new instruction. */
- bfd_put_32_me (abfd, code, contents + irel->r_offset - 4);
-
- /* The size isn't changed, don't redo. */
- *again = FALSE;
- }
- }
-
- if (isymbuf != NULL
- && symtab_hdr->contents != (unsigned char *) isymbuf)
- {
- if (!link_info->keep_memory)
- free (isymbuf);
- else
- /* Cache the symbols for elf_link_input_bfd. */
- symtab_hdr->contents = (unsigned char *) isymbuf;
- }
-
- if (contents != NULL
- && elf_section_data (sec)->this_hdr.contents != contents)
- {
- if (!link_info->keep_memory)
- free (contents);
- else
- /* Cache the section contents for elf_link_input_bfd. */
- elf_section_data (sec)->this_hdr.contents = contents;
- }
-
- if (elf_section_data (sec)->relocs != internal_relocs)
- free (internal_relocs);
-
- return TRUE;
-
- error_return:
- if (symtab_hdr->contents != (unsigned char *) isymbuf)
- free (isymbuf);
- if (elf_section_data (sec)->this_hdr.contents != contents)
- free (contents);
- if (elf_section_data (sec)->relocs != internal_relocs)
- free (internal_relocs);
-
- return FALSE;
-}
-
-#define TARGET_LITTLE_SYM arc_elf32_le_vec
-#define TARGET_LITTLE_NAME "elf32-littlearc"
-#define TARGET_BIG_SYM arc_elf32_be_vec
-#define TARGET_BIG_NAME "elf32-bigarc"
-#define ELF_ARCH bfd_arch_arc
-#define ELF_TARGET_ID ARC_ELF_DATA
-#define ELF_MACHINE_CODE EM_ARC_COMPACT
-#define ELF_MACHINE_ALT1 EM_ARC_COMPACT2
-#define ELF_MAXPAGESIZE 0x2000
-
-#define bfd_elf32_bfd_link_hash_table_create arc_elf_link_hash_table_create
-
-#define bfd_elf32_bfd_merge_private_bfd_data arc_elf_merge_private_bfd_data
-#define bfd_elf32_bfd_reloc_type_lookup arc_elf32_bfd_reloc_type_lookup
-#define bfd_elf32_bfd_set_private_flags arc_elf_set_private_flags
-#define bfd_elf32_bfd_print_private_bfd_data arc_elf_print_private_bfd_data
-#define bfd_elf32_bfd_copy_private_bfd_data arc_elf_copy_private_bfd_data
-#define bfd_elf32_bfd_relax_section arc_elf_relax_section
-
-#define elf_info_to_howto_rel arc_info_to_howto_rel
-#define elf_backend_object_p arc_elf_object_p
-#define elf_backend_final_write_processing arc_elf_final_write_processing
-
-#define elf_backend_relocate_section elf_arc_relocate_section
-#define elf_backend_check_relocs elf_arc_check_relocs
-#define elf_backend_create_dynamic_sections _bfd_elf_create_dynamic_sections
-
-#define elf_backend_reloc_type_class elf32_arc_reloc_type_class
-
-#define elf_backend_adjust_dynamic_symbol elf_arc_adjust_dynamic_symbol
-#define elf_backend_finish_dynamic_symbol elf_arc_finish_dynamic_symbol
-
-#define elf_backend_finish_dynamic_sections elf_arc_finish_dynamic_sections
-#define elf_backend_size_dynamic_sections elf_arc_size_dynamic_sections
-
-#define elf_backend_can_gc_sections 1
-#define elf_backend_want_got_plt 1
-#define elf_backend_plt_readonly 1
-#define elf_backend_rela_plts_and_copies_p 1
-#define elf_backend_want_plt_sym 0
-#define elf_backend_got_header_size 12
-#define elf_backend_dtrel_excludes_plt 1
-
-#define elf_backend_may_use_rel_p 0
-#define elf_backend_may_use_rela_p 1
-#define elf_backend_default_use_rela_p 1
-
-#define elf_backend_grok_prstatus elf32_arc_grok_prstatus
-
-#define elf_backend_default_execstack 0
-
-#undef elf_backend_obj_attrs_vendor
-#define elf_backend_obj_attrs_vendor "ARC"
-#undef elf_backend_obj_attrs_section
-#define elf_backend_obj_attrs_section ".ARC.attributes"
-#undef elf_backend_obj_attrs_arg_type
-#define elf_backend_obj_attrs_arg_type elf32_arc_obj_attrs_arg_type
-#undef elf_backend_obj_attrs_section_type
-#define elf_backend_obj_attrs_section_type SHT_ARC_ATTRIBUTES
-#define elf_backend_obj_attrs_handle_unknown elf32_arc_obj_attrs_handle_unknown
-
-#define elf_backend_section_from_shdr elf32_arc_section_from_shdr
-
-#include "elf32-target.h"
diff --git a/bfd/elflink.c b/bfd/elflink.c
index 998b72f2281..27b11a7f7b7 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -13234,7 +13234,7 @@ elf_gc_mark_debug_section (asection *sec ATTRIBUTE_UNUSED,
/* Return the local debug definition section. */
asection *isec = bfd_section_from_elf_index (sec->owner,
sym->st_shndx);
- if ((isec->flags & SEC_DEBUGGING) != 0)
+ if (isec && (isec->flags & SEC_DEBUGGING) != 0)
return isec;
}
diff --git a/bfd/elfnn-arc.c b/bfd/elfnn-arc.c
new file mode 100644
index 00000000000..f27f1ef5966
--- /dev/null
+++ b/bfd/elfnn-arc.c
@@ -0,0 +1,3556 @@
+/* ARC-specific support for 32-bit ELF
+ Copyright (C) 1994-2020 Free Software Foundation, Inc.
+ Contributed by Cupertino Miranda (cmiranda@synopsys.com).
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf/arc.h"
+#include "libiberty.h"
+#include "opcode/arc-func.h"
+#include "opcode/arc.h"
+
+#define RELA_SIZE sizeof(ElfNN_External_Rela)
+
+#include "arc-plt.h"
+
+#define FEATURE_LIST_NAME bfdNN_feature_list
+#define CONFLICT_LIST bfdNN_conflict_list
+#include "opcode/arc-attrs.h"
+
+
+#define ARCH_SIZE NN
+
+/* The name of the dynamic interpreter. This is put in the .interp
+ section. */
+
+#define ELF64_DYNAMIC_INTERPRETER "/lib/ld.so.1"
+#define ELF32_DYNAMIC_INTERPRETER "/sbin/ld-uClibc.so"
+
+#define LOG_FILE_ALIGN (ARCH_SIZE == 32 ? 2 : 3)
+
+/* Do not enable this unless you know what you are doing.
+ * Code under this macro is not safe for production.
+ * */
+/* #define ARC_ENABLE_DEBUG 1 */
+#ifdef ARC_ENABLE_DEBUG
+static const char *
+name_for_global_symbol (struct elf_link_hash_entry *h)
+{
+ static char *local_str = "(local)";
+ if (h == NULL)
+ return local_str;
+ return h->root.root.string;
+}
+#define ARC_DEBUG(fmt, args...) fprintf (stderr, fmt, ##args)
+#else
+#define ARC_DEBUG(...)
+#endif
+
+#define ADD_RELA(BFD, SECTION, OFFSET, SYM_IDX, TYPE, ADDEND) \
+ { \
+ struct elf_link_hash_table *_htab = elf_hash_table (info); \
+ Elf_Internal_Rela _rel; \
+ bfd_byte * _loc; \
+ const struct elf_backend_data *bed; \
+ bed = get_elf_backend_data (BFD); \
+ \
+ if (_htab->dynamic_sections_created == TRUE) \
+ { \
+ BFD_ASSERT (_htab->srel##SECTION &&_htab->srel##SECTION->contents); \
+ _loc = _htab->srel##SECTION->contents \
+ + ((_htab->srel##SECTION->reloc_count) \
+ * sizeof (ElfNN_External_Rela)); \
+ _htab->srel##SECTION->reloc_count++; \
+ _rel.r_addend = ADDEND; \
+ _rel.r_offset = (_htab->s##SECTION)->output_section->vma \
+ + (_htab->s##SECTION)->output_offset + OFFSET; \
+ BFD_ASSERT ((long) SYM_IDX != -1); \
+ _rel.r_info = ELFNN_R_INFO (SYM_IDX, TYPE); \
+ bed->s->swap_reloca_out (BFD, &_rel, _loc); \
+ } \
+ }
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+ case VALUE: \
+ return "R_" #TYPE; \
+ break;
+
+static ATTRIBUTE_UNUSED const char *
+reloc_type_to_name (unsigned int type)
+{
+ switch (type)
+ {
+#include "elf/arc-reloc.def"
+
+ default:
+ return "UNKNOWN";
+ break;
+ }
+}
+
+#undef ARC_RELOC_HOWTO
+
+/* Try to minimize the amount of space occupied by relocation tables
+ on the ROM (not that the ROM won't be swamped by other ELF overhead). */
+
+#define USE_REL 1
+
+/* Similar with bfd_get_32 but taking into account the
+ middle-endianess of the ARC CPUs. Only to be used in code
+ sections. */
+
+static bfd_vma
+bfd_get_32_me (bfd * abfd,const unsigned char * data)
+{
+ bfd_vma value = 0;
+
+ if (bfd_big_endian (abfd))
+ value = bfd_get_32 (abfd, data);
+ else
+ {
+ value = ((bfd_get_8 (abfd, data) & 255) << 16);
+ value |= ((bfd_get_8 (abfd, data + 1) & 255) << 24);
+ value |= (bfd_get_8 (abfd, data + 2) & 255);
+ value |= ((bfd_get_8 (abfd, data + 3) & 255) << 8);
+ }
+
+ return value;
+}
+
+static void
+bfd_put_32_me (bfd *abfd, bfd_vma value,unsigned char *data)
+{
+ bfd_put_16 (abfd, (value & 0xffff0000) >> 16, data);
+ bfd_put_16 (abfd, value & 0xffff, data + 2);
+}
+
+static ATTRIBUTE_UNUSED bfd_boolean
+is_reloc_PC_relative (reloc_howto_type *howto)
+{
+ return (strstr (howto->name, "PC") != NULL) ? TRUE : FALSE;
+}
+
+static bfd_boolean
+is_reloc_SDA_relative (reloc_howto_type *howto)
+{
+ return (strstr (howto->name, "SDA") != NULL) ? TRUE : FALSE;
+}
+
+static bfd_boolean
+is_reloc_for_GOT (reloc_howto_type * howto)
+{
+ if (strstr (howto->name, "TLS") != NULL)
+ return FALSE;
+ return (strstr (howto->name, "GOT") != NULL) ? TRUE : FALSE;
+}
+
+static bfd_boolean
+is_reloc_for_PLT (reloc_howto_type * howto)
+{
+ return (strstr (howto->name, "PLT") != NULL) ? TRUE : FALSE;
+}
+
+static bfd_boolean
+is_reloc_for_TLS (reloc_howto_type *howto)
+{
+ return (strstr (howto->name, "TLS") != NULL) ? TRUE : FALSE;
+}
+
+struct arc_relocation_data
+{
+ bfd_signed_vma reloc_offset;
+ bfd_signed_vma reloc_addend;
+ bfd_signed_vma got_offset_value;
+
+ bfd_signed_vma sym_value;
+ asection * sym_section;
+
+ reloc_howto_type *howto;
+
+ asection * input_section;
+
+ bfd_signed_vma sdata_begin_symbol_vma;
+ bfd_boolean sdata_begin_symbol_vma_set;
+ bfd_signed_vma got_symbol_vma;
+
+ bfd_boolean should_relocate;
+
+ const char * symbol_name;
+};
+
+/* ARC ELF linker hash entry. */
+struct elf_arc_link_hash_entry
+{
+ struct elf_link_hash_entry root;
+
+ struct got_entry *got_ents;
+};
+
+
+/* Should be included at this location due to static declarations
+ defined before this point. */
+#include "arc-got.h"
+
+#define arc_bfd_get_8(A,B,C) bfd_get_8(A,B)
+#define arc_bfd_get_16(A,B,C) bfd_get_16(A,B)
+#define arc_bfd_get_32(A,B,C) bfd_get_32(A,B)
+#define arc_bfd_put_8(A,B,C,D) bfd_put_8(A,B,C)
+#define arc_bfd_put_16(A,B,C,D) bfd_put_16(A,B,C)
+#define arc_bfd_put_32(A,B,C,D) bfd_put_32(A,B,C)
+
+
+static bfd_reloc_status_type
+arc_elf_reloc (bfd *abfd ATTRIBUTE_UNUSED,
+ arelent *reloc_entry,
+ asymbol *symbol_in,
+ void *data ATTRIBUTE_UNUSED,
+ asection *input_section,
+ bfd *output_bfd,
+ char ** error_message ATTRIBUTE_UNUSED)
+{
+ if (output_bfd != NULL)
+ {
+ reloc_entry->address += input_section->output_offset;
+
+ /* In case of relocateable link and if the reloc is against a
+ section symbol, the addend needs to be adjusted according to
+ where the section symbol winds up in the output section. */
+ if ((symbol_in->flags & BSF_SECTION_SYM) && symbol_in->section)
+ reloc_entry->addend += symbol_in->section->output_offset;
+
+ return bfd_reloc_ok;
+ }
+
+ return bfd_reloc_continue;
+}
+
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+ TYPE = VALUE,
+
+enum howto_list
+ {
+#include "elf/arc-reloc.def"
+ HOWTO_LIST_LAST
+ };
+
+#undef ARC_RELOC_HOWTO
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, RSIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+ [TYPE] = HOWTO (R_##TYPE, 0, RSIZE, BITSIZE, FALSE, 0, \
+ complain_overflow_##OVERFLOW, arc_elf_reloc, \
+ "R_" #TYPE, FALSE, 0, 0, FALSE),
+
+static struct reloc_howto_struct elf_arc_howto_table[] =
+ {
+#include "elf/arc-reloc.def"
+ /* Example of what is generated by the preprocessor. Currently kept as an
+ example.
+ HOWTO (R_ARC_NONE, // Type.
+ 0, // Rightshift.
+ 2, // Size (0 = byte, 1 = short, 2 = long).
+ 32, // Bitsize.
+ FALSE, // PC_relative.
+ 0, // Bitpos.
+ complain_overflow_bitfield, // Complain_on_overflow.
+ bfd_elf_generic_reloc, // Special_function.
+ "R_ARC_NONE", // Name.
+ TRUE, // Partial_inplace.
+ 0, // Src_mask.
+ 0, // Dst_mask.
+ FALSE), // PCrel_offset.
+ */
+ };
+#undef ARC_RELOC_HOWTO
+
+static void
+arc_elf_howto_init (void)
+{
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+ elf_arc_howto_table[TYPE].pc_relative = \
+ (strstr (#FORMULA, " P ") != NULL || strstr (#FORMULA, " PDATA ") != NULL); \
+ elf_arc_howto_table[TYPE].dst_mask = RELOC_FUNCTION(0, ~0); \
+ /* Only 32 bit data relocations should be marked as ME. */ \
+ if (strstr (#FORMULA, " ME ") != NULL) \
+ { \
+ BFD_ASSERT (SIZE == 2); \
+ }
+
+#include "elf/arc-reloc.def"
+
+}
+#undef ARC_RELOC_HOWTO
+
+static reloc_howto_type *
+arc_elf_howto (unsigned int r_type)
+{
+ if (elf_arc_howto_table[R_ARC_32].dst_mask == 0)
+ arc_elf_howto_init ();
+ return &elf_arc_howto_table[r_type];
+}
+
+/* Map BFD reloc types to ARC ELF reloc types. */
+
+struct arc_reloc_map
+{
+ bfd_reloc_code_real_type bfd_reloc_val;
+ unsigned char elf_reloc_val;
+};
+
+/* ARC ELF linker hash table. */
+struct elf_arc_link_hash_table
+{
+ struct elf_link_hash_table elf;
+};
+
+static struct bfd_hash_entry *
+elf_arc_link_hash_newfunc (struct bfd_hash_entry *entry,
+ struct bfd_hash_table *table,
+ const char *string)
+{
+ struct elf_arc_link_hash_entry * ret =
+ (struct elf_arc_link_hash_entry *) entry;
+
+ /* Allocate the structure if it has not already been allocated by a
+ subclass. */
+ if (ret == NULL)
+ ret = (struct elf_arc_link_hash_entry *)
+ bfd_hash_allocate (table, sizeof (struct elf_arc_link_hash_entry));
+ if (ret == NULL)
+ return (struct bfd_hash_entry *) ret;
+
+ /* Call the allocation method of the superclass. */
+ ret = ((struct elf_arc_link_hash_entry *)
+ _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
+ table, string));
+ if (ret != NULL)
+ {
+ ret->got_ents = NULL;
+ }
+
+ return (struct bfd_hash_entry *) ret;
+}
+
+/* Destroy an ARC ELF linker hash table. */
+static void
+elf_arc_link_hash_table_free (bfd *obfd)
+{
+ _bfd_elf_link_hash_table_free (obfd);
+}
+
+/* Create an ARC ELF linker hash table. */
+
+static struct bfd_link_hash_table *
+arc_elf_link_hash_table_create (bfd *abfd)
+{
+ struct elf_arc_link_hash_table *ret;
+ bfd_size_type amt = sizeof (struct elf_arc_link_hash_table);
+
+ ret = (struct elf_arc_link_hash_table *) bfd_zmalloc (amt);
+ if (ret == NULL)
+ return NULL;
+
+ if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd,
+ elf_arc_link_hash_newfunc,
+ sizeof (struct elf_arc_link_hash_entry),
+ ARC_ELF_DATA))
+ {
+ free (ret);
+ return NULL;
+ }
+
+ ret->elf.root.hash_table_free = elf_arc_link_hash_table_free;
+
+ return &ret->elf.root;
+}
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+ { BFD_RELOC_##TYPE, R_##TYPE },
+
+static const struct arc_reloc_map arc_reloc_map[] =
+ {
+#include "elf/arc-reloc.def"
+
+ {BFD_RELOC_NONE, R_ARC_NONE},
+ {BFD_RELOC_8, R_ARC_8},
+ {BFD_RELOC_16, R_ARC_16},
+ {BFD_RELOC_24, R_ARC_24},
+ {BFD_RELOC_32, R_ARC_32},
+ {BFD_RELOC_64, R_ARC_64},
+ };
+
+#undef ARC_RELOC_HOWTO
+
+typedef ATTRIBUTE_UNUSED bfd_vma (*replace_func) (unsigned, int ATTRIBUTE_UNUSED);
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+ case TYPE: \
+ func = (void *) RELOC_FUNCTION; \
+ break;
+
+static replace_func
+get_replace_function (bfd *abfd, unsigned int r_type)
+{
+ void *func = NULL;
+
+ switch (r_type)
+ {
+#include "elf/arc-reloc.def"
+ }
+
+ if (func == replace_bits24 && bfd_big_endian (abfd))
+ func = replace_bits24_be;
+
+ return (replace_func) func;
+}
+#undef ARC_RELOC_HOWTO
+
+static reloc_howto_type *
+arc_elfNN_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ bfd_reloc_code_real_type code)
+{
+ unsigned int i;
+
+ for (i = ARRAY_SIZE (arc_reloc_map); i--;)
+ {
+ if (arc_reloc_map[i].bfd_reloc_val == code)
+ return arc_elf_howto (arc_reloc_map[i].elf_reloc_val);
+ }
+
+ return NULL;
+}
+
+/* Function to set the ELF flag bits. */
+static bfd_boolean
+arc_elf_set_private_flags (bfd *abfd, flagword flags)
+{
+ elf_elfheader (abfd)->e_flags = flags;
+ elf_flags_init (abfd) = TRUE;
+ return TRUE;
+}
+
+/* Print private flags. */
+static bfd_boolean
+arc_elf_print_private_bfd_data (bfd *abfd, void * ptr)
+{
+ FILE *file = (FILE *) ptr;
+ flagword flags;
+
+ BFD_ASSERT (abfd != NULL && ptr != NULL);
+
+ /* Print normal ELF private data. */
+ _bfd_elf_print_private_bfd_data (abfd, ptr);
+
+ flags = elf_elfheader (abfd)->e_flags;
+ fprintf (file, _("private flags = 0x%lx:"), (unsigned long) flags);
+
+ switch (flags & EF_ARC_MACH_MSK)
+ {
+ case EF_ARC_CPU_ARCV2HS : fprintf (file, " -mcpu=ARCv2HS"); break;
+ case EF_ARC_CPU_ARCV2EM : fprintf (file, " -mcpu=ARCv2EM"); break;
+ case E_ARC_MACH_ARC600 : fprintf (file, " -mcpu=ARC600"); break;
+ case E_ARC_MACH_ARC601 : fprintf (file, " -mcpu=ARC601"); break;
+ case E_ARC_MACH_ARC700 : fprintf (file, " -mcpu=ARC700"); break;
+ default:
+ fprintf (file, "-mcpu=unknown");
+ break;
+ }
+
+ switch (flags & EF_ARC_OSABI_MSK)
+ {
+ case E_ARC_OSABI_ORIG : fprintf (file, " (ABI:legacy)"); break;
+ case E_ARC_OSABI_V2 : fprintf (file, " (ABI:v2)"); break;
+ case E_ARC_OSABI_V3 : fprintf (file, " (ABI:v3)"); break;
+ case E_ARC_OSABI_V4 : fprintf (file, " (ABI:v4)"); break;
+ default:
+ fprintf (file, " (ABI:unknown)");
+ break;
+ }
+
+ fputc ('\n', file);
+ return TRUE;
+}
+
+/* Copy backend specific data from one object module to another. */
+
+static bfd_boolean
+arc_elf_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
+{
+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour
+ || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
+ return TRUE;
+
+ BFD_ASSERT (!elf_flags_init (obfd)
+ || elf_elfheader (obfd)->e_flags == elf_elfheader (ibfd)->e_flags);
+
+ elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags;
+ elf_flags_init (obfd) = TRUE;
+
+ /* Copy object attributes. */
+ _bfd_elf_copy_obj_attributes (ibfd, obfd);
+
+ return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
+}
+
+static reloc_howto_type *
+bfd_elfNN_bfd_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ const char *r_name)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (elf_arc_howto_table); i++)
+ if (elf_arc_howto_table[i].name != NULL
+ && strcasecmp (elf_arc_howto_table[i].name, r_name) == 0)
+ return arc_elf_howto (i);
+
+ return NULL;
+}
+
+/* Set the howto pointer for an ARC ELF reloc. */
+
+static bfd_boolean
+arc_info_to_howto_rel (bfd * abfd,
+ arelent * cache_ptr,
+ Elf_Internal_Rela * dst)
+{
+ unsigned int r_type;
+
+ r_type = ELFNN_R_TYPE (dst->r_info);
+ if (r_type >= (unsigned int) R_ARC_max)
+ {
+ /* xgettext:c-format */
+ _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
+ abfd, r_type);
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+
+ cache_ptr->howto = arc_elf_howto (r_type);
+ return cache_ptr->howto != NULL;
+}
+
+/* Extract CPU features from an NTBS. */
+
+static unsigned
+arc_extract_features (const char *p)
+{
+ unsigned i, r = 0;
+
+ if (!p)
+ return 0;
+
+ for (i = 0; i < ARRAY_SIZE (FEATURE_LIST_NAME); i++)
+ {
+ char *t = strstr (p, FEATURE_LIST_NAME[i].attr);
+ unsigned l = strlen (FEATURE_LIST_NAME[i].attr);
+ if ((t != NULL)
+ && (t[l] == ','
+ || t[l] == '\0'))
+ r |= FEATURE_LIST_NAME[i].feature;
+ }
+
+ return r;
+}
+
+/* Concatenate two strings. s1 can be NULL but not
+ s2. */
+
+static char *
+arc_stralloc (char * s1, const char * s2)
+{
+ char *p;
+
+ /* Only s1 can be null. */
+ BFD_ASSERT (s2);
+
+ p = s1 ? concat (s1, ",", s2, NULL) : (char *)s2;
+
+ return p;
+}
+
+/* Merge ARC object attributes from IBFD into OBFD. Raise an error if
+ there are conflicting attributes. */
+
+static bfd_boolean
+arc_elf_merge_attributes (bfd *ibfd, struct bfd_link_info *info)
+{
+ bfd *obfd = info->output_bfd;
+ obj_attribute *in_attr;
+ obj_attribute *out_attr;
+ int i;
+ bfd_boolean result = TRUE;
+ const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
+ char *tagname = NULL;
+
+ /* Skip the linker stubs file. This preserves previous behavior
+ of accepting unknown attributes in the first input file - but
+ is that a bug? */
+ if (ibfd->flags & BFD_LINKER_CREATED)
+ return TRUE;
+
+ /* Skip any input that hasn't attribute section.
+ This enables to link object files without attribute section with
+ any others. */
+ if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
+ return TRUE;
+
+ if (!elf_known_obj_attributes_proc (obfd)[0].i)
+ {
+ /* This is the first object. Copy the attributes. */
+ _bfd_elf_copy_obj_attributes (ibfd, obfd);
+
+ out_attr = elf_known_obj_attributes_proc (obfd);
+
+ /* Use the Tag_null value to indicate the attributes have been
+ initialized. */
+ out_attr[0].i = 1;
+
+ return TRUE;
+ }
+
+ in_attr = elf_known_obj_attributes_proc (ibfd);
+ out_attr = elf_known_obj_attributes_proc (obfd);
+
+ for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
+ {
+ /* Merge this attribute with existing attributes. */
+ switch (i)
+ {
+ case Tag_ARC_PCS_config:
+ if (out_attr[i].i == 0)
+ out_attr[i].i = in_attr[i].i;
+ else if ((in_attr[i].i & 0xff) != 0
+ && ((out_attr[i].i & 0xff) != (in_attr[i].i & 0xff)))
+ {
+ const char *tagval[] = { "Absent", "Bare-metal/mwdt",
+ "Bare-metal/newlib", "Linux/uclibc",
+ "Linux/glibc" };
+ BFD_ASSERT ((in_attr[i].i & 0xff) < 5);
+ BFD_ASSERT ((out_attr[i].i & 0xff) < 5);
+ /* It's sometimes ok to mix different configs, so this is only
+ a warning. */
+ _bfd_error_handler
+ (_("warning: %pB: conflicting platform configuration "
+ "%s with %s"), ibfd,
+ tagval[in_attr[i].i & 0xff],
+ tagval[out_attr[i].i & 0xff]);
+ }
+ break;
+
+ case Tag_ARC_CPU_base:
+ if (out_attr[i].i == 0)
+ out_attr[i].i = in_attr[i].i;
+ else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i
+ && ((out_attr[i].i + in_attr[i].i) < 6))
+ {
+ const char *tagval[] = { "Absent", "ARC6xx", "ARC7xx",
+ "ARCEM", "ARCHS" };
+ BFD_ASSERT (in_attr[i].i < 5);
+ BFD_ASSERT (out_attr[i].i < 5);
+ /* We cannot mix code for different CPUs. */
+ _bfd_error_handler
+ (_("error: %pB: unable to merge CPU base attributes "
+ "%s with %s"),
+ obfd,
+ tagval[in_attr[i].i],
+ tagval[out_attr[i].i]);
+ result = FALSE;
+ break;
+ }
+ else
+ {
+ /* The CPUs may be different, check if we can still mix
+ the objects against the output choosen CPU. */
+ unsigned in_feature = 0;
+ unsigned out_feature = 0;
+ char *p1 = in_attr[Tag_ARC_ISA_config].s;
+ char *p2 = out_attr[Tag_ARC_ISA_config].s;
+ unsigned j;
+ unsigned cpu_out;
+ unsigned opcode_map[] = {0, ARC_OPCODE_ARC600, ARC_OPCODE_ARC700,
+ ARC_OPCODE_ARCv2EM, ARC_OPCODE_ARCv2HS};
+
+ BFD_ASSERT (in_attr[i].i < (sizeof (opcode_map)
+ / sizeof (unsigned)));
+ BFD_ASSERT (out_attr[i].i < (sizeof (opcode_map)
+ / sizeof (unsigned)));
+ cpu_out = opcode_map[out_attr[i].i];
+
+ in_feature = arc_extract_features (p1);
+ out_feature = arc_extract_features (p2);
+
+ /* First, check if a feature is compatible with the
+ output object chosen CPU. */
+ for (j = 0; j < ARRAY_SIZE (FEATURE_LIST_NAME); j++)
+ if (((in_feature | out_feature) & FEATURE_LIST_NAME[j].feature)
+ && (!(cpu_out & FEATURE_LIST_NAME[j].cpus)))
+ {
+ _bfd_error_handler
+ (_("error: %pB: unable to merge ISA extension attributes "
+ "%s"),
+ obfd, FEATURE_LIST_NAME[j].name);
+ result = FALSE;
+ break;
+ }
+ /* Second, if we have compatible features with the
+ chosen CPU, check if they are compatible among
+ them. */
+ for (j = 0; j < ARRAY_SIZE (CONFLICT_LIST); j++)
+ if (((in_feature | out_feature) & CONFLICT_LIST[j])
+ == CONFLICT_LIST[j])
+ {
+ unsigned k;
+ for (k = 0; k < ARRAY_SIZE (FEATURE_LIST_NAME); k++)
+ {
+ if (in_feature & FEATURE_LIST_NAME[k].feature
+ & CONFLICT_LIST[j])
+ p1 = (char *) FEATURE_LIST_NAME[k].name;
+ if (out_feature & FEATURE_LIST_NAME[k].feature
+ & CONFLICT_LIST[j])
+ p2 = (char *) FEATURE_LIST_NAME[k].name;
+ }
+ _bfd_error_handler
+ (_("error: %pB: conflicting ISA extension attributes "
+ "%s with %s"),
+ obfd, p1, p2);
+ result = FALSE;
+ break;
+ }
+ /* Everithing is alright. */
+ out_feature |= in_feature;
+ p1 = NULL;
+ for (j = 0; j < ARRAY_SIZE (FEATURE_LIST_NAME); j++)
+ if (out_feature & FEATURE_LIST_NAME[j].feature)
+ p1 = arc_stralloc (p1, FEATURE_LIST_NAME[j].attr);
+ if (p1)
+ out_attr[Tag_ARC_ISA_config].s =
+ _bfd_elf_attr_strdup (obfd, p1);
+ }
+ /* Fall through. */
+ case Tag_ARC_CPU_variation:
+ case Tag_ARC_ISA_mpy_option:
+ case Tag_ARC_ABI_osver:
+ /* Use the largest value specified. */
+ if (in_attr[i].i > out_attr[i].i)
+ out_attr[i].i = in_attr[i].i;
+ break;
+
+ /* The CPU name is given by the vendor, just choose an
+ existing one if missing or different. There are no fail
+ criteria if they different or both missing. */
+ case Tag_ARC_CPU_name:
+ if (!out_attr[i].s && in_attr[i].s)
+ out_attr[i].s = _bfd_elf_attr_strdup (obfd, in_attr[i].s);
+ break;
+
+ case Tag_ARC_ABI_rf16:
+ if (out_attr[i].i == 0)
+ out_attr[i].i = in_attr[i].i;
+ else if (out_attr[i].i != in_attr[i].i)
+ {
+ /* We cannot mix code with rf16 and without. */
+ _bfd_error_handler
+ (_("error: %pB: cannot mix rf16 with full register set %pB"),
+ obfd, ibfd);
+ result = FALSE;
+ }
+ break;
+
+ case Tag_ARC_ABI_pic:
+ tagname = "PIC";
+ /* fall through */
+ case Tag_ARC_ABI_sda:
+ if (!tagname)
+ tagname = "SDA";
+ /* fall through */
+ case Tag_ARC_ABI_tls:
+ {
+ const char *tagval[] = { "Absent", "MWDT", "GNU" };
+
+ if (!tagname)
+ tagname = "TLS";
+
+ BFD_ASSERT (in_attr[i].i < 3);
+ BFD_ASSERT (out_attr[i].i < 3);
+ if (out_attr[i].i == 0)
+ out_attr[i].i = in_attr[i].i;
+ else if (out_attr[i].i != 0 && in_attr[i].i != 0
+ && out_attr[i].i != in_attr[i].i)
+ {
+ _bfd_error_handler
+ (_("error: %pB: conflicting attributes %s: %s with %s"),
+ obfd, tagname,
+ tagval[in_attr[i].i],
+ tagval[out_attr[i].i]);
+ result = FALSE;
+ }
+ tagname = NULL;
+ break;
+ }
+
+ case Tag_ARC_ABI_double_size:
+ tagname = "Double size";
+ /* fall through */
+ case Tag_ARC_ABI_enumsize:
+ if (!tagname)
+ tagname = "Enum size";
+ /* fall through */
+ case Tag_ARC_ABI_exceptions:
+ if (!tagname)
+ tagname = "ABI exceptions";
+
+ if (out_attr[i].i == 0)
+ out_attr[i].i = in_attr[i].i;
+ else if (out_attr[i].i != 0 && in_attr[i].i != 0
+ && out_attr[i].i != in_attr[i].i)
+ {
+ _bfd_error_handler
+ (_("error: %pB: conflicting attributes %s"),
+ obfd, tagname);
+ result = FALSE;
+ }
+ break;
+
+ case Tag_ARC_ISA_apex:
+ break; /* Do nothing for APEX attributes. */
+
+ case Tag_ARC_ISA_config:
+ /* It is handled in Tag_ARC_CPU_base. */
+ break;
+
+ case Tag_ARC_ATR_version:
+ if (out_attr[i].i == 0)
+ out_attr[i].i = in_attr[i].i;
+ break;
+
+ default:
+ result
+ = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
+ }
+
+ /* If out_attr was copied from in_attr then it won't have a type yet. */
+ if (in_attr[i].type && !out_attr[i].type)
+ out_attr[i].type = in_attr[i].type;
+ }
+
+ /* Merge Tag_compatibility attributes and any common GNU ones. */
+ if (!_bfd_elf_merge_object_attributes (ibfd, info))
+ return FALSE;
+
+ /* Check for any attributes not known on ARC. */
+ result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
+
+ return result;
+}
+
+/* Merge backend specific data from an object file to the output
+ object file when linking. */
+
+static bfd_boolean
+arc_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
+{
+ bfd *obfd = info->output_bfd;
+ unsigned short mach_ibfd;
+ static unsigned short mach_obfd = EM_NONE;
+ flagword out_flags;
+ flagword in_flags;
+ asection *sec;
+
+ /* Check if we have the same endianess. */
+ if (! _bfd_generic_verify_endian_match (ibfd, info))
+ return FALSE;
+
+ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour
+ || bfd_get_flavour (obfd) != bfd_target_elf_flavour)
+ return TRUE;
+
+ /* Collect ELF flags. */
+ in_flags = elf_elfheader (ibfd)->e_flags & EF_ARC_MACH_MSK;
+ out_flags = elf_elfheader (obfd)->e_flags & EF_ARC_MACH_MSK;
+
+ if (!elf_flags_init (obfd)) /* First call, no flags set. */
+ {
+ elf_flags_init (obfd) = TRUE;
+ out_flags = in_flags;
+ }
+
+ if (!arc_elf_merge_attributes (ibfd, info))
+ return FALSE;
+
+ /* Check to see if the input BFD actually contains any sections. Do
+ not short-circuit dynamic objects; their section list may be
+ emptied by elf_link_add_object_symbols. */
+ if (!(ibfd->flags & DYNAMIC))
+ {
+ bfd_boolean null_input_bfd = TRUE;
+ bfd_boolean only_data_sections = TRUE;
+
+ for (sec = ibfd->sections; sec != NULL; sec = sec->next)
+ {
+ if ((bfd_section_flags (sec)
+ & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
+ == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
+ only_data_sections = FALSE;
+
+ null_input_bfd = FALSE;
+ }
+
+ if (null_input_bfd || only_data_sections)
+ return TRUE;
+ }
+
+ /* Complain about various flag/architecture mismatches. */
+ mach_ibfd = elf_elfheader (ibfd)->e_machine;
+ if (mach_obfd == EM_NONE)
+ {
+ mach_obfd = mach_ibfd;
+ }
+ else
+ {
+ if (mach_ibfd != mach_obfd)
+ {
+ /* xgettext:c-format */
+ _bfd_error_handler (_("error: attempting to link %pB "
+ "with a binary %pB of different architecture"),
+ ibfd, obfd);
+ return FALSE;
+ }
+ else if ((in_flags != out_flags)
+ /* If we have object attributes, then we already
+ checked the objects compatibility, skip it. */
+ && !bfd_elf_get_obj_attr_int (ibfd, OBJ_ATTR_PROC,
+ Tag_ARC_CPU_base))
+ {
+ if (in_flags && out_flags)
+ {
+ /* Warn if different flags. */
+ _bfd_error_handler
+ /* xgettext:c-format */
+ (_("%pB: uses different e_flags (%#x) fields than "
+ "previous modules (%#x)"),
+ ibfd, in_flags, out_flags);
+ return FALSE;
+ }
+ /* MWDT doesnt set the eflags hence make sure we choose the
+ eflags set by gcc. */
+ in_flags = in_flags > out_flags ? in_flags : out_flags;
+ }
+ else
+ {
+ /* Everything is correct; don't change the output flags. */
+ in_flags = out_flags;
+ }
+ }
+
+ /* Update the flags. */
+ elf_elfheader (obfd)->e_flags = in_flags;
+
+ if (bfd_get_mach (obfd) < bfd_get_mach (ibfd))
+ {
+ return bfd_set_arch_mach (obfd, bfd_arch_arc, bfd_get_mach (ibfd));
+ }
+
+ return TRUE;
+}
+
+/* Return a best guess for the machine number based on the attributes. */
+
+static unsigned int
+bfd_arc_get_mach_from_attributes (bfd * abfd)
+{
+ int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ARC_CPU_base);
+ unsigned e_machine = elf_elfheader (abfd)->e_machine;
+
+ switch (arch)
+ {
+ case TAG_CPU_ARC6xx:
+ return bfd_mach_arc_arc600;
+ case TAG_CPU_ARC7xx:
+ return bfd_mach_arc_arc700;
+ case TAG_CPU_ARCEM:
+ case TAG_CPU_ARCHS:
+ return bfd_mach_arc_arcv2;
+ default:
+ break;
+ }
+ return (e_machine == EM_ARC_COMPACT)
+ ? bfd_mach_arc_arc700 : bfd_mach_arc_arcv2;
+}
+
+/* Set the right machine number for an ARC ELF file. Make sure this
+ is initialised, or you'll have the potential of passing garbage---or
+ misleading values---into the call to bfd_default_set_arch_mach(). */
+
+static bfd_boolean
+arc_elf_object_p (bfd * abfd)
+{
+ unsigned int mach;
+ unsigned long arch = elf_elfheader (abfd)->e_flags & EF_ARC_MACH_MSK;
+ unsigned e_machine = elf_elfheader (abfd)->e_machine;
+
+#if ARCH_SIZE == 32
+ mach = bfd_mach_arc_arc700;
+#else
+ mach = bfd_mach_arcv3_64;
+#endif
+
+ switch (e_machine)
+ {
+ case EM_ARC_COMPACT:
+ case EM_ARC_COMPACT2:
+ switch (arch)
+ {
+ case E_ARC_MACH_ARC600:
+ mach = bfd_mach_arc_arc600;
+ break;
+ case E_ARC_MACH_ARC601:
+ mach = bfd_mach_arc_arc601;
+ break;
+ case E_ARC_MACH_ARC700:
+ mach = bfd_mach_arc_arc700;
+ break;
+ case EF_ARC_CPU_ARCV2HS:
+ case EF_ARC_CPU_ARCV2EM:
+ mach = bfd_mach_arc_arcv2;
+ break;
+ default:
+ mach = bfd_arc_get_mach_from_attributes (abfd);
+ break;
+ }
+ break;
+
+ case EM_ARC:
+ _bfd_error_handler
+ (_("error: the ARC4 architecture is no longer supported"));
+ return FALSE;
+
+ case EM_ARC_COMPACT3_64:
+ mach = bfd_mach_arcv3_64;
+ break;
+
+ case EM_ARC_COMPACT3:
+ mach = bfd_mach_arcv3_32;
+ break;
+
+ default:
+ _bfd_error_handler
+ (_("warning: unset or old architecture flags; "
+ "use default machine"));
+ }
+
+ return bfd_default_set_arch_mach (abfd, bfd_arch_arc, mach);
+}
+
+/* The final processing done just before writing out an ARC ELF object file.
+ This gets the ARC architecture right based on the machine number. */
+
+static bfd_boolean
+arc_elf_final_write_processing (bfd *abfd)
+{
+ unsigned long emf;
+ int osver = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC,
+ Tag_ARC_ABI_osver);
+ flagword e_flags = elf_elfheader (abfd)->e_flags & ~EF_ARC_OSABI_MSK;
+
+ switch (bfd_get_mach (abfd))
+ {
+ case bfd_mach_arc_arcv2:
+ emf = EM_ARC_COMPACT2;
+ break;
+ case bfd_mach_arcv3_64:
+ emf = EM_ARC_COMPACT3_64;
+ break;
+ case bfd_mach_arcv3_32:
+ emf = EM_ARC_COMPACT3;
+ break;
+ default:
+ emf = EM_ARC_COMPACT;
+ break;
+ }
+
+ elf_elfheader (abfd)->e_machine = emf;
+
+ /* Record whatever is the current syscall ABI version. */
+ if (osver)
+ e_flags |= ((osver & 0x0f) << 8);
+ else
+ e_flags |= E_ARC_OSABI_V3;
+
+ elf_elfheader (abfd)->e_flags |= e_flags;
+ return _bfd_elf_final_write_processing (abfd);
+}
+
+#ifdef ARC_ENABLE_DEBUG
+#define DEBUG_ARC_RELOC(A) debug_arc_reloc (A)
+
+static void
+debug_arc_reloc (struct arc_relocation_data reloc_data)
+{
+ ARC_DEBUG ("Reloc type=%s, should_relocate = %s\n",
+ reloc_data.howto->name,
+ reloc_data.should_relocate ? "true" : "false");
+ ARC_DEBUG (" offset = 0x%x, addend = 0x%x\n",
+ (unsigned int) reloc_data.reloc_offset,
+ (unsigned int) reloc_data.reloc_addend);
+ ARC_DEBUG (" Symbol:\n");
+ ARC_DEBUG (" value = 0x%08x\n",
+ (unsigned int) reloc_data.sym_value);
+ if (reloc_data.sym_section != NULL)
+ {
+ ARC_DEBUG (" Symbol Section:\n");
+ ARC_DEBUG (" section name = %s, output_offset 0x%08x",
+ reloc_data.sym_section->name,
+ (unsigned int) reloc_data.sym_section->output_offset);
+ if (reloc_data.sym_section->output_section != NULL)
+ ARC_DEBUG (", output_section->vma = 0x%08x",
+ ((unsigned int) reloc_data.sym_section->output_section->vma));
+ ARC_DEBUG ("\n");
+ if (reloc_data.sym_section->owner
+ && reloc_data.sym_section->owner->filename)
+ ARC_DEBUG (" file: %s\n", reloc_data.sym_section->owner->filename);
+ }
+ else
+ {
+ ARC_DEBUG (" symbol section is NULL\n");
+ }
+
+ ARC_DEBUG (" Input_section:\n");
+ if (reloc_data.input_section != NULL)
+ {
+ ARC_DEBUG (" section name = %s, output_offset 0x%08x, " \
+ "output_section->vma = 0x%08x\n",
+ reloc_data.input_section->name,
+ (unsigned int) reloc_data.input_section->output_offset,
+ (unsigned int) reloc_data.input_section->output_section->vma);
+ ARC_DEBUG (" changed_address = 0x%08x\n",
+ (unsigned int) (reloc_data.input_section->output_section->vma
+ + reloc_data.input_section->output_offset
+ + reloc_data.reloc_offset));
+ ARC_DEBUG (" file: %s\n", reloc_data.input_section->owner->filename);
+ }
+ else
+ {
+ ARC_DEBUG (" input section is NULL\n");
+ }
+}
+#else
+#define DEBUG_ARC_RELOC(A)
+#endif /* ARC_ENABLE_DEBUG */
+
+static bfd_vma
+middle_endian_convert (bfd_vma insn, bfd_boolean do_it)
+{
+ if (do_it)
+ {
+ insn
+ = ((insn & 0xffff0000) >> 16)
+ | ((insn & 0xffff) << 16);
+ }
+ return insn;
+}
+
+/* This function is called for relocations that are otherwise marked as NOT
+ requiring overflow checks. In here we perform non-standard checks of
+ the relocation value. */
+
+static inline bfd_reloc_status_type
+arc_special_overflow_checks (const struct arc_relocation_data reloc_data,
+ bfd_signed_vma relocation,
+ struct bfd_link_info *info ATTRIBUTE_UNUSED)
+{
+ switch (reloc_data.howto->type)
+ {
+ case R_ARC_NPS_CMEM16:
+ if (((relocation >> 16) & 0xffff) != NPS_CMEM_HIGH_VALUE)
+ {
+ if (reloc_data.reloc_addend == 0)
+ _bfd_error_handler
+ /* xgettext:c-format */
+ (_("%pB(%pA+%#" PRIx64 "): CMEM relocation to `%s' is invalid, "
+ "16 MSB should be %#x (value is %#" PRIx64 ")"),
+ reloc_data.input_section->owner,
+ reloc_data.input_section,
+ (uint64_t) reloc_data.reloc_offset,
+ reloc_data.symbol_name,
+ NPS_CMEM_HIGH_VALUE,
+ (uint64_t) relocation);
+ else
+ _bfd_error_handler
+ /* xgettext:c-format */
+ (_("%pB(%pA+%#" PRIx64 "): CMEM relocation to `%s+%#" PRIx64
+ "' is invalid, 16 MSB should be %#x (value is %#" PRIx64 ")"),
+ reloc_data.input_section->owner,
+ reloc_data.input_section,
+ (uint64_t) reloc_data.reloc_offset,
+ reloc_data.symbol_name,
+ (uint64_t) reloc_data.reloc_addend,
+ NPS_CMEM_HIGH_VALUE,
+ (uint64_t) relocation);
+ return bfd_reloc_overflow;
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ return bfd_reloc_ok;
+}
+
+#define ME(reloc) (reloc)
+
+#define IS_ME(FORMULA,BFD) ((strstr (FORMULA, "ME") != NULL) \
+ && (!bfd_big_endian (BFD)))
+
+#define S ((bfd_signed_vma) (reloc_data.sym_value \
+ + (reloc_data.sym_section->output_section != NULL ? \
+ (reloc_data.sym_section->output_offset \
+ + reloc_data.sym_section->output_section->vma) : 0)))
+#define L ((bfd_signed_vma) (reloc_data.sym_value \
+ + (reloc_data.sym_section->output_section != NULL ? \
+ (reloc_data.sym_section->output_offset \
+ + reloc_data.sym_section->output_section->vma) : 0)))
+#define A (reloc_data.reloc_addend)
+#define B (0)
+#define G (reloc_data.got_offset_value)
+#define GOT (reloc_data.got_symbol_vma)
+#define GOT_BEGIN (htab->sgot->output_section->vma)
+
+#define MES (0)
+/* P: relative offset to PCL The offset should be to the
+ current location aligned to 32 bits. */
+#define P ((bfd_signed_vma) ( \
+ ( \
+ (reloc_data.input_section->output_section != NULL ? \
+ reloc_data.input_section->output_section->vma : 0) \
+ + reloc_data.input_section->output_offset \
+ + (reloc_data.reloc_offset - (bitsize >= 32 ? 4 : 0))) \
+ & ~0x3))
+#define PDATA ((bfd_signed_vma) ( \
+ (reloc_data.input_section->output_section->vma \
+ + reloc_data.input_section->output_offset \
+ + (reloc_data.reloc_offset))))
+#define SECTSTART (bfd_signed_vma) (reloc_data.sym_section->output_section->vma \
+ + reloc_data.sym_section->output_offset)
+#define FINAL_SECTSTART \
+ (bfd_signed_vma) (reloc_data.sym_section->output_section->vma)
+#define JLI (bfd_signed_vma) (reloc_data.sym_section->output_section->vma)
+#define _SDA_BASE_ (bfd_signed_vma) (reloc_data.sdata_begin_symbol_vma)
+#define TLS_REL (bfd_signed_vma) \
+ ((elf_hash_table (info))->tls_sec->output_section->vma)
+#define TLS_TBSS (align_power(TCB_SIZE, \
+ reloc_data.sym_section->alignment_power))
+#define ICARRY insn
+#define DEREFP (insn)
+
+#define none (0)
+
+#ifdef ARC_ENABLE_DEBUG
+#define PRINT_DEBUG_RELOC_INFO_BEFORE(FORMULA, TYPE) \
+ do \
+ { \
+ asection *sym_section = reloc_data.sym_section; \
+ asection *input_section = reloc_data.input_section; \
+ ARC_DEBUG ("RELOC_TYPE = " TYPE "\n"); \
+ ARC_DEBUG ("FORMULA = " FORMULA "\n"); \
+ ARC_DEBUG ("S = %#lx\n", S); \
+ ARC_DEBUG ("A = %#lx\n", A); \
+ ARC_DEBUG ("L = %lx\n", L); \
+ if (sym_section->output_section != NULL) \
+ ARC_DEBUG ("symbol_section->vma = %#lx\n", \
+ sym_section->output_section->vma \
+ + sym_section->output_offset); \
+ else \
+ ARC_DEBUG ("symbol_section->vma = NULL\n"); \
+ if (input_section->output_section != NULL) \
+ ARC_DEBUG ("input_section->vma = %#lx\n", \
+ input_section->output_section->vma \
+ + input_section->output_offset); \
+ else \
+ ARC_DEBUG ("input_section->vma = NULL\n"); \
+ ARC_DEBUG ("PCL = %#lx\n", P); \
+ ARC_DEBUG ("P = %#lx\n", P); \
+ ARC_DEBUG ("G = %#lx\n", G); \
+ ARC_DEBUG ("SDA_OFFSET = %#lx\n", _SDA_BASE_); \
+ ARC_DEBUG ("SDA_SET = %d\n", reloc_data.sdata_begin_symbol_vma_set); \
+ ARC_DEBUG ("GOT_OFFSET = %#lx\n", GOT); \
+ ARC_DEBUG ("relocation = %#08lx\n", relocation); \
+ ARC_DEBUG ("before = %#08x\n", (unsigned) insn); \
+ ARC_DEBUG ("data = %08x (%u) (%d)\n", (unsigned) relocation, \
+ (unsigned) relocation, (int) relocation); \
+ } \
+ while (0)
+
+#define PRINT_DEBUG_RELOC_INFO_AFTER \
+ do \
+ { \
+ ARC_DEBUG ("after = 0x%08x\n", (unsigned int) insn); \
+ } \
+ while (0)
+
+#else
+
+#define PRINT_DEBUG_RELOC_INFO_BEFORE(...)
+#define PRINT_DEBUG_RELOC_INFO_AFTER
+
+#endif /* ARC_ENABLE_DEBUG */
+
+#define ARC_RELOC_HOWTO(TYPE, VALUE, SIZE, BITSIZE, RELOC_FUNCTION, OVERFLOW, FORMULA) \
+ case R_##TYPE: \
+ { \
+ bfd_signed_vma bitsize ATTRIBUTE_UNUSED = BITSIZE; \
+ relocation = FORMULA ; \
+ PRINT_DEBUG_RELOC_INFO_BEFORE (#FORMULA, #TYPE); \
+ insn = middle_endian_convert (insn, IS_ME (#FORMULA, abfd)); \
+ insn = (* get_replace_function (abfd, TYPE)) (insn, relocation); \
+ insn = middle_endian_convert (insn, IS_ME (#FORMULA, abfd)); \
+ PRINT_DEBUG_RELOC_INFO_AFTER; \
+ } \
+ break;
+
+static bfd_reloc_status_type
+arc_do_relocation (bfd_byte * contents,
+ struct arc_relocation_data reloc_data,
+ struct bfd_link_info *info)
+{
+ bfd_signed_vma relocation = 0;
+ bfd_vma insn;
+ bfd_vma orig_insn ATTRIBUTE_UNUSED;
+ bfd * abfd = reloc_data.input_section->owner;
+ struct elf_link_hash_table *htab ATTRIBUTE_UNUSED = elf_hash_table (info);
+ bfd_reloc_status_type flag;
+
+ if (!reloc_data.should_relocate)
+ return bfd_reloc_ok;
+
+ switch (reloc_data.howto->size)
+ {
+ case 2:
+ insn = arc_bfd_get_32 (abfd,
+ contents + reloc_data.reloc_offset,
+ reloc_data.input_section);
+ break;
+ case 1:
+ insn = arc_bfd_get_16 (abfd,
+ contents + reloc_data.reloc_offset,
+ reloc_data.input_section);
+ break;
+ case 0:
+ insn = arc_bfd_get_8 (abfd,
+ contents + reloc_data.reloc_offset,
+ reloc_data.input_section);
+ break;
+ default:
+ insn = 0;
+ BFD_ASSERT (0);
+ break;
+ }
+
+ orig_insn = insn;
+
+ switch (reloc_data.howto->type)
+ {
+#include "elf/arc-reloc.def"
+
+ default:
+ BFD_ASSERT (0);
+ break;
+ }
+
+ /* Check for relocation overflow. */
+ if (reloc_data.howto->complain_on_overflow != complain_overflow_dont)
+ flag = bfd_check_overflow (reloc_data.howto->complain_on_overflow,
+ reloc_data.howto->bitsize,
+ reloc_data.howto->rightshift,
+ bfd_arch_bits_per_address (abfd),
+ relocation);
+ else
+ flag = arc_special_overflow_checks (reloc_data, relocation, info);
+
+ if (flag != bfd_reloc_ok)
+ {
+ ARC_DEBUG ("Relocation overflows !\n");
+ DEBUG_ARC_RELOC (reloc_data);
+ ARC_DEBUG ("Relocation value = signed -> %d, unsigned -> %u"
+ ", hex -> (0x%08x)\n",
+ (int) relocation, (unsigned) relocation, (int) relocation);
+
+ return flag;
+ }
+
+ /* Write updated instruction back to memory. */
+ switch (reloc_data.howto->size)
+ {
+ case 2:
+ arc_bfd_put_32 (abfd, insn,
+ contents + reloc_data.reloc_offset,
+ reloc_data.input_section);
+ break;
+ case 1:
+ arc_bfd_put_16 (abfd, insn,
+ contents + reloc_data.reloc_offset,
+ reloc_data.input_section);
+ break;
+ case 0:
+ arc_bfd_put_8 (abfd, insn,
+ contents + reloc_data.reloc_offset,
+ reloc_data.input_section);
+ break;
+ default:
+ ARC_DEBUG ("size = %d\n", reloc_data.howto->size);
+ BFD_ASSERT (0);
+ break;
+ }
+
+ return bfd_reloc_ok;
+}
+#undef S
+#undef A
+#undef B
+#undef G
+#undef GOT
+#undef L
+#undef MES
+#undef P
+#undef SECTSTAR
+#undef SECTSTART
+#undef JLI
+#undef _SDA_BASE_
+#undef ICARRY
+#undef none
+
+#undef ARC_RELOC_HOWTO
+
+
+/* Relocate an arc ELF section.
+ Function : elf_arc_relocate_section
+ Brief : Relocate an arc section, by handling all the relocations
+ appearing in that section.
+ Args : output_bfd : The bfd being written to.
+ info : Link information.
+ input_bfd : The input bfd.
+ input_section : The section being relocated.
+ contents : contents of the section being relocated.
+ relocs : List of relocations in the section.
+ local_syms : is a pointer to the swapped in local symbols.
+ local_section : is an array giving the section in the input file
+ corresponding to the st_shndx field of each
+ local symbol. */
+static bfd_boolean
+elf_arc_relocate_section (bfd * output_bfd,
+ struct bfd_link_info * info,
+ bfd * input_bfd,
+ asection * input_section,
+ bfd_byte * contents,
+ Elf_Internal_Rela * relocs,
+ Elf_Internal_Sym * local_syms,
+ asection ** local_sections)
+{
+ Elf_Internal_Shdr * symtab_hdr;
+ struct elf_link_hash_entry ** sym_hashes;
+ Elf_Internal_Rela * rel;
+ Elf_Internal_Rela * wrel;
+ Elf_Internal_Rela * relend;
+ struct elf_link_hash_table * htab = elf_hash_table (info);
+ const struct elf_backend_data *bed;
+
+ bed = get_elf_backend_data (output_bfd);
+ symtab_hdr = &((elf_tdata (input_bfd))->symtab_hdr);
+ sym_hashes = elf_sym_hashes (input_bfd);
+
+ rel = wrel = relocs;
+ relend = relocs + input_section->reloc_count;
+ for (; rel < relend; wrel++, rel++)
+ {
+ enum elf_arc_reloc_type r_type;
+ reloc_howto_type * howto;
+ unsigned long r_symndx;
+ struct elf_link_hash_entry * h;
+ Elf_Internal_Sym * sym;
+ asection * sec;
+ struct elf_link_hash_entry * h2;
+ const char * msg;
+ bfd_boolean unresolved_reloc = FALSE;
+ bfd_boolean resolved_to_zero;
+
+ struct arc_relocation_data reloc_data =
+ {
+ .reloc_offset = 0,
+ .reloc_addend = 0,
+ .got_offset_value = 0,
+ .sym_value = 0,
+ .sym_section = NULL,
+ .howto = NULL,
+ .input_section = NULL,
+ .sdata_begin_symbol_vma = 0,
+ .sdata_begin_symbol_vma_set = FALSE,
+ .got_symbol_vma = 0,
+ .should_relocate = FALSE
+ };
+
+ r_type = ELFNN_R_TYPE (rel->r_info);
+
+ if (r_type >= (int) R_ARC_max)
+ {
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+ howto = arc_elf_howto (r_type);
+
+ r_symndx = ELFNN_R_SYM (rel->r_info);
+
+ /* If we are generating another .o file and the symbol in not
+ local, skip this relocation. */
+ if (bfd_link_relocatable (info))
+ {
+ /* This is a relocateable link. We don't have to change
+ anything, unless the reloc is against a section symbol,
+ in which case we have to adjust according to where the
+ section symbol winds up in the output section. */
+
+ /* Checks if this is a local symbol and thus the reloc
+ might (will??) be against a section symbol. */
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ if (ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+ {
+ sec = local_sections[r_symndx];
+
+ /* For RELA relocs. Just adjust the addend
+ value in the relocation entry. */
+ rel->r_addend += sec->output_offset + sym->st_value;
+
+ ARC_DEBUG ("local symbols reloc (section=%d %s) seen in %s\n",
+ (int) r_symndx, local_sections[r_symndx]->name,
+ __PRETTY_FUNCTION__);
+ }
+ }
+ }
+
+ h2 = elf_link_hash_lookup (elf_hash_table (info), "__SDATA_BEGIN__",
+ FALSE, FALSE, TRUE);
+
+ if (!reloc_data.sdata_begin_symbol_vma_set
+ && h2 != NULL && h2->root.type != bfd_link_hash_undefined
+ && h2->root.u.def.section->output_section != NULL)
+ /* TODO: Verify this condition. */
+ {
+ reloc_data.sdata_begin_symbol_vma =
+ (h2->root.u.def.value
+ + h2->root.u.def.section->output_section->vma);
+ reloc_data.sdata_begin_symbol_vma_set = TRUE;
+ }
+
+ reloc_data.input_section = input_section;
+ reloc_data.howto = howto;
+ reloc_data.reloc_offset = rel->r_offset;
+ reloc_data.reloc_addend = rel->r_addend;
+
+ /* This is a final link. */
+ h = NULL;
+ sym = NULL;
+ sec = NULL;
+
+ if (r_symndx < symtab_hdr->sh_info) /* A local symbol. */
+ {
+ sym = local_syms + r_symndx;
+ sec = local_sections[r_symndx];
+ }
+ else
+ {
+ bfd_boolean warned, ignored;
+ bfd_vma relocation ATTRIBUTE_UNUSED;
+
+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+ r_symndx, symtab_hdr, sym_hashes,
+ h, sec, relocation,
+ unresolved_reloc, warned, ignored);
+
+ /* TODO: This code is repeated from below. We should
+ clean it and remove duplications.
+ Sec is used check for discarded sections.
+ Need to redesign code below. */
+
+ /* Get the symbol's entry in the symtab. */
+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+ /* If we have encountered a definition for this symbol. */
+ if (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak)
+ {
+ reloc_data.sym_value = h->root.u.def.value;
+ sec = h->root.u.def.section;
+ }
+ }
+
+ /* Clean relocs for symbols in discarded sections. */
+ if (sec != NULL && discarded_section (sec))
+ {
+ _bfd_clear_contents (howto, input_bfd, input_section,
+ contents, rel->r_offset);
+ rel->r_info = 0;
+ rel->r_addend = 0;
+
+ /* For ld -r, remove relocations in debug sections against
+ sections defined in discarded sections. Not done for
+ eh_frame editing code expects to be present. */
+ if (bfd_link_relocatable (info)
+ && (input_section->flags & SEC_DEBUGGING))
+ wrel--;
+
+ continue;
+ }
+
+ if (bfd_link_relocatable (info))
+ {
+ if (wrel != rel)
+ *wrel = *rel;
+ continue;
+ }
+
+ resolved_to_zero = (h != NULL && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
+
+ if (r_symndx < symtab_hdr->sh_info) /* A local symbol. */
+ {
+ reloc_data.sym_value = sym->st_value;
+ reloc_data.sym_section = sec;
+ reloc_data.symbol_name =
+ bfd_elf_string_from_elf_section (input_bfd,
+ symtab_hdr->sh_link,
+ sym->st_name);
+
+ /* Mergeable section handling. */
+ if ((sec->flags & SEC_MERGE)
+ && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+ {
+ asection *msec;
+ msec = sec;
+ rel->r_addend = _bfd_elf_rel_local_sym (output_bfd, sym,
+ &msec, rel->r_addend);
+ rel->r_addend -= (sec->output_section->vma
+ + sec->output_offset
+ + sym->st_value);
+ rel->r_addend += msec->output_section->vma + msec->output_offset;
+
+ reloc_data.reloc_addend = rel->r_addend;
+ }
+
+ BFD_ASSERT (htab->sgot != NULL || !is_reloc_for_GOT (howto));
+ if (htab->sgot != NULL)
+ reloc_data.got_symbol_vma = htab->sgot->output_section->vma
+ + htab->sgot->output_offset;
+
+ reloc_data.should_relocate = TRUE;
+ }
+ else /* Global symbol. */
+ {
+ /* FIXME: We should use the RELOC_FOR_GLOBAL_SYMBOL macro
+ (defined in elf-bfd.h) here. */
+
+ /* Get the symbol's entry in the symtab. */
+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ {
+ struct elf_arc_link_hash_entry *ah_old
+ = (struct elf_arc_link_hash_entry *) h;
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+ struct elf_arc_link_hash_entry *ah
+ = (struct elf_arc_link_hash_entry *) h;
+
+ if (ah->got_ents == 0 && ah_old->got_ents != ah->got_ents)
+ ah->got_ents = ah_old->got_ents;
+ }
+
+ /* TODO: Need to validate what was the intention. */
+ /* BFD_ASSERT ((h->dynindx == -1) || (h->forced_local != 0)); */
+ reloc_data.symbol_name = h->root.root.string;
+
+ /* If we have encountered a definition for this symbol. */
+ if (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak)
+ {
+ reloc_data.sym_value = h->root.u.def.value;
+ reloc_data.sym_section = h->root.u.def.section;
+
+ reloc_data.should_relocate = TRUE;
+
+ if (is_reloc_for_GOT (howto) && !bfd_link_pic (info))
+ {
+ struct elf_arc_link_hash_entry *ah =
+ (struct elf_arc_link_hash_entry *) h;
+ /* TODO: Change it to use arc_do_relocation with
+ ARC_32 reloc. Try to use ADD_RELA macro. */
+ bfd_vma relocation =
+ reloc_data.sym_value + reloc_data.reloc_addend
+ + (reloc_data.sym_section->output_section != NULL ?
+ (reloc_data.sym_section->output_offset
+ + reloc_data.sym_section->output_section->vma)
+ : 0);
+
+ BFD_ASSERT (ah->got_ents);
+ bfd_vma got_offset = ah->got_ents->offset;
+ bfd_put_32 (output_bfd, relocation,
+ htab->sgot->contents + got_offset);
+ }
+ if (is_reloc_for_PLT (howto) && h->plt.offset != (bfd_vma) -1)
+ {
+ /* TODO: This is repeated up here. */
+ reloc_data.sym_value = h->plt.offset;
+ reloc_data.sym_section = htab->splt;
+ }
+ }
+ else if (h->root.type == bfd_link_hash_undefweak)
+ {
+ /* Is weak symbol and has no definition. */
+ if (is_reloc_for_GOT (howto))
+ {
+ reloc_data.sym_value = h->root.u.def.value;
+ reloc_data.sym_section = htab->sgot;
+ reloc_data.should_relocate = TRUE;
+ }
+ else if (is_reloc_for_PLT (howto)
+ && h->plt.offset != (bfd_vma) -1)
+ {
+ /* TODO: This is repeated up here. */
+ reloc_data.sym_value = h->plt.offset;
+ reloc_data.sym_section = htab->splt;
+ reloc_data.should_relocate = TRUE;
+ }
+ /* See pr22269. */
+ else if (!resolved_to_zero)
+ continue;
+ }
+ else
+ {
+ if (is_reloc_for_GOT (howto))
+ {
+ reloc_data.sym_value = h->root.u.def.value;
+ reloc_data.sym_section = htab->sgot;
+
+ reloc_data.should_relocate = TRUE;
+ }
+ else if (is_reloc_for_PLT (howto))
+ {
+ /* Fail if it is linking for PIE and the symbol is
+ undefined. */
+ if (bfd_link_executable (info))
+ (*info->callbacks->undefined_symbol)
+ (info, h->root.root.string, input_bfd, input_section,
+ rel->r_offset, TRUE);
+ reloc_data.sym_value = h->plt.offset;
+ reloc_data.sym_section = htab->splt;
+
+ reloc_data.should_relocate = TRUE;
+ }
+ else if (!bfd_link_pic (info) || bfd_link_executable (info))
+ (*info->callbacks->undefined_symbol)
+ (info, h->root.root.string, input_bfd, input_section,
+ rel->r_offset, TRUE);
+ }
+
+ BFD_ASSERT (htab->sgot != NULL || !is_reloc_for_GOT (howto));
+ if (htab->sgot != NULL)
+ reloc_data.got_symbol_vma = htab->sgot->output_section->vma
+ + htab->sgot->output_offset;
+ }
+
+ if ((is_reloc_for_GOT (howto)
+ || is_reloc_for_TLS (howto)))
+ {
+ reloc_data.should_relocate = TRUE;
+
+ struct got_entry **list
+ = get_got_entry_list_for_symbol (input_bfd, r_symndx, h);
+
+ reloc_data.got_offset_value
+ = relocate_fix_got_relocs_for_got_info (list,
+ tls_type_for_reloc (howto),
+ info,
+ output_bfd,
+ r_symndx,
+ local_syms,
+ local_sections,
+ h,
+ &reloc_data);
+
+ if (h == NULL)
+ {
+ create_got_dynrelocs_for_single_entry
+ (got_entry_for_type (list,
+ arc_got_entry_type_for_reloc (howto)),
+ output_bfd, info, NULL);
+ }
+ }
+
+
+#define IS_ARC_PCREL_TYPE(TYPE) \
+ ( (TYPE == R_ARC_PC32) \
+ || (TYPE == R_ARC_32_PCREL))
+
+ switch (r_type)
+ {
+ case R_ARC_64:
+ case R_ARC_32:
+ case R_ARC_32_ME:
+ case R_ARC_PC32:
+ case R_ARC_32_PCREL:
+ case R_ARC_HI32_ME:
+ case R_ARC_LO32_ME:
+ if (bfd_link_pic (info)
+ && !resolved_to_zero
+ && (input_section->flags & SEC_ALLOC) != 0
+ && (!IS_ARC_PCREL_TYPE (r_type)
+ || (h != NULL
+ && h->dynindx != -1
+ && (!SYMBOL_REFERENCES_LOCAL (info, h)))))
+ {
+ Elf_Internal_Rela outrel;
+ bfd_byte *loc;
+ bfd_boolean skip = FALSE;
+ bfd_boolean relocate = FALSE;
+ asection *sreloc = _bfd_elf_get_dynamic_reloc_section
+ (input_bfd, input_section,
+ /*RELA*/ TRUE);
+
+ BFD_ASSERT (sreloc != NULL);
+
+ outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+ info,
+ input_section,
+ rel->r_offset);
+
+ if (outrel.r_offset == (bfd_vma) -1)
+ skip = TRUE;
+
+ outrel.r_addend = rel->r_addend;
+ outrel.r_offset += (input_section->output_section->vma
+ + input_section->output_offset);
+
+ if (skip)
+ {
+ memset (&outrel, 0, sizeof outrel);
+ relocate = FALSE;
+ }
+ else if (h != NULL
+ && h->dynindx != -1
+ && (IS_ARC_PCREL_TYPE (r_type)
+ || !(bfd_link_executable (info)
+ || SYMBOLIC_BIND (info, h))
+ || ! h->def_regular))
+ {
+ BFD_ASSERT (h != NULL);
+ if ((input_section->flags & SEC_ALLOC) != 0)
+ relocate = FALSE;
+ else
+ relocate = TRUE;
+
+ BFD_ASSERT (h->dynindx != -1);
+ outrel.r_info = ELFNN_R_INFO (h->dynindx, r_type);
+ }
+ else
+ {
+ /* Handle local symbols, they either do not have a
+ global hash table entry (h == NULL), or are
+ forced local due to a version script
+ (h->forced_local), or the third condition is
+ legacy, it appears to say something like, for
+ links where we are pre-binding the symbols, or
+ there's not an entry for this symbol in the
+ dynamic symbol table, and it's a regular symbol
+ not defined in a shared object, then treat the
+ symbol as local, resolve it now. */
+ relocate = TRUE;
+ /* outrel.r_addend = 0; */
+ outrel.r_info = ELFNN_R_INFO (0, R_ARC_RELATIVE);
+ }
+
+ BFD_ASSERT (sreloc->contents != 0);
+
+ loc = sreloc->contents;
+ loc += sreloc->reloc_count * sizeof (ElfNN_External_Rela);
+ sreloc->reloc_count += 1;
+
+ bed->s->swap_reloca_out (output_bfd, &outrel, loc);
+
+ if (!relocate)
+ continue;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (is_reloc_SDA_relative (howto)
+ && !reloc_data.sdata_begin_symbol_vma_set)
+ {
+ _bfd_error_handler
+ ("error: linker symbol __SDATA_BEGIN__ not found");
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+
+ DEBUG_ARC_RELOC (reloc_data);
+
+ /* Make sure we have with a dynamic linker. In case of GOT and PLT
+ the sym_section should point to .got or .plt respectively. */
+ if ((is_reloc_for_GOT (howto) || is_reloc_for_PLT (howto))
+ && reloc_data.sym_section == NULL)
+ {
+ _bfd_error_handler
+ (_("GOT and PLT relocations cannot be fixed with a non dynamic" \
+ " linker"));
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+
+ msg = NULL;
+ switch (arc_do_relocation (contents, reloc_data, info))
+ {
+ case bfd_reloc_ok:
+ continue; /* The reloc processing loop. */
+
+ case bfd_reloc_overflow:
+ (*info->callbacks->reloc_overflow)
+ (info, (h ? &h->root : NULL), reloc_data.symbol_name, howto->name,
+ (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
+ break;
+
+ case bfd_reloc_undefined:
+ (*info->callbacks->undefined_symbol)
+ (info, reloc_data.symbol_name, input_bfd, input_section,
+ rel->r_offset, TRUE);
+ break;
+
+ case bfd_reloc_other:
+ /* xgettext:c-format */
+ msg = _("%pB(%pA): warning: unaligned access to symbol '%s' in the" \
+ " small data area");
+ break;
+
+ case bfd_reloc_outofrange:
+ /* xgettext:c-format */
+ msg = _("%pB(%pA): internal error: out of range error");
+ break;
+
+ case bfd_reloc_notsupported:
+ /* xgettext:c-format */
+ msg = _("%pB(%pA): internal error: unsupported relocation error");
+ break;
+
+ case bfd_reloc_dangerous:
+ /* xgettext:c-format */
+ msg = _("%pB(%pA): internal error: dangerous relocation");
+ break;
+
+ default:
+ /* xgettext:c-format */
+ msg = _("%pB(%pA): internal error: unknown error");
+ break;
+ }
+
+ if (msg)
+ _bfd_error_handler (msg, input_bfd, input_section,
+ reloc_data.symbol_name);
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+#define elf_arc_hash_table(p) \
+ (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \
+ == ARC_ELF_DATA ? ((struct elf_arc_link_hash_table *) ((p)->hash)) : NULL)
+
+static bfd_boolean
+elf_arc_check_relocs (bfd * abfd,
+ struct bfd_link_info * info,
+ asection * sec,
+ const Elf_Internal_Rela * relocs)
+{
+ Elf_Internal_Shdr * symtab_hdr;
+ struct elf_link_hash_entry ** sym_hashes;
+ const Elf_Internal_Rela * rel;
+ const Elf_Internal_Rela * rel_end;
+ bfd * dynobj;
+ asection * sreloc = NULL;
+ struct elf_link_hash_table * htab = elf_hash_table (info);
+
+ if (bfd_link_relocatable (info))
+ return TRUE;
+
+ if (htab->dynobj == NULL)
+ htab->dynobj = abfd;
+
+ dynobj = (elf_hash_table (info))->dynobj;
+ symtab_hdr = &((elf_tdata (abfd))->symtab_hdr);
+ sym_hashes = elf_sym_hashes (abfd);
+
+ rel_end = relocs + sec->reloc_count;
+ for (rel = relocs; rel < rel_end; rel++)
+ {
+ enum elf_arc_reloc_type r_type;
+ reloc_howto_type *howto;
+ unsigned long r_symndx;
+ struct elf_link_hash_entry *h;
+
+ r_type = ELFNN_R_TYPE (rel->r_info);
+
+ if (r_type >= (int) R_ARC_max)
+ {
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+ howto = arc_elf_howto (r_type);
+
+ /* Load symbol information. */
+ r_symndx = ELFNN_R_SYM (rel->r_info);
+ if (r_symndx < symtab_hdr->sh_info) /* Is a local symbol. */
+ h = NULL;
+ else /* Global one. */
+ {
+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+ }
+
+
+ switch (r_type)
+ {
+ case R_ARC_8:
+ case R_ARC_16:
+ case R_ARC_32:
+ case R_ARC_64:
+ case R_ARC_32_ME:
+ case R_ARC_HI32_ME:
+ case R_ARC_LO32_ME:
+ /* During shared library creation, these relocs should not
+ appear in a shared library (as memory will be read only
+ and the dynamic linker can not resolve these. However
+ the error should not occur for e.g. debugging or
+ non-readonly sections. */
+ if (h != NULL
+ && (bfd_link_dll (info) && !bfd_link_pie (info))
+ && (sec->flags & SEC_ALLOC) != 0
+ && (sec->flags & SEC_READONLY) != 0
+ && ((sec->flags & SEC_CODE) != 0
+ || (sec->flags & SEC_DEBUGGING) != 0))
+ {
+ const char *name;
+ if (h)
+ name = h->root.root.string;
+ else
+ name = "UNKNOWN";
+ _bfd_error_handler
+ /* xgettext:c-format */
+ (_("%pB: relocation %s against `%s' can not be used"
+ " when making a shared object; recompile with -fPIC"),
+ abfd,
+ arc_elf_howto (r_type)->name,
+ name);
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+
+ /* In some cases we are not setting the 'non_got_ref' flag,
+ even though the relocations don't require a GOT access.
+ We should extend the testing in this area to ensure that
+ no significant cases are being missed. */
+ if (h)
+ h->non_got_ref = 1;
+
+ /* We don't need to handle relocs into sections not going
+ into the "real" output. */
+ if ((sec->flags & SEC_ALLOC) == 0)
+ break;
+
+ /* No need to do anything if we're not creating a shared
+ object. */
+ if (!bfd_link_pic (info)
+ || (h != NULL
+ && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)))
+ break;
+
+ /* FALLTHROUGH */
+ case R_ARC_PC32:
+ case R_ARC_32_PCREL:
+ if (!bfd_link_pic (info))
+ break;
+
+ if (((r_type != R_ARC_PC32 && r_type != R_ARC_32_PCREL)
+ || (!SYMBOL_REFERENCES_LOCAL (info, h))))
+ {
+ if (sreloc == NULL)
+ {
+ if (info->dynamic
+ && ! htab->dynamic_sections_created
+ && ! _bfd_elf_link_create_dynamic_sections (abfd, info))
+ return FALSE;
+ sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj,
+ 2, abfd,
+ /*rela*/
+ TRUE);
+
+ if (sreloc == NULL)
+ return FALSE;
+ }
+ sreloc->size += sizeof (ElfNN_External_Rela);
+ }
+ default:
+ break;
+ }
+
+ if (is_reloc_for_PLT (howto))
+ {
+ if (h == NULL)
+ continue;
+ else
+ if (h->forced_local == 0)
+ h->needs_plt = 1;
+ }
+
+ /* Add info to the symbol got_entry_list. */
+ if (is_reloc_for_GOT (howto)
+ || is_reloc_for_TLS (howto))
+ {
+ if (bfd_link_dll (info) && !bfd_link_pie (info)
+ && (r_type == R_ARC_TLS_LE_32 || r_type == R_ARC_TLS_LE_S9))
+ {
+ const char *name;
+ if (h)
+ name = h->root.root.string;
+ else
+ /* bfd_elf_sym_name (abfd, symtab_hdr, isym, NULL); */
+ name = "UNKNOWN";
+ _bfd_error_handler
+ /* xgettext:c-format */
+ (_("%pB: relocation %s against `%s' can not be used"
+ " when making a shared object; recompile with -fPIC"),
+ abfd,
+ arc_elf_howto (r_type)->name,
+ name);
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+ if (! _bfd_elf_create_got_section (dynobj, info))
+ return FALSE;
+
+ arc_fill_got_info_for_reloc
+ (arc_got_entry_type_for_reloc (howto),
+ get_got_entry_list_for_symbol (abfd, r_symndx, h),
+ info,
+ h);
+ }
+ }
+
+ return TRUE;
+}
+
+static struct plt_version_t *
+arc_get_plt_version (struct bfd_link_info *info)
+{
+ int i;
+
+ for (i = 0; i < 1; i++)
+ {
+ ARC_DEBUG ("%d: size1 = %d, size2 = %d\n", i,
+ (int) plt_versions[i].entry_size,
+ (int) plt_versions[i].elem_size);
+ }
+
+ if (bfd_get_mach (info->output_bfd) == bfd_mach_arcv3_64
+ || bfd_get_mach(info->output_bfd) == bfd_mach_arcv3_32)
+ {
+ return &(plt_versions[ELF_ARCV3_PIC]);
+// if (bfd_link_pic (info))
+// else
+// return &(plt_versions[ELF_ARCV2_ABS]);
+ }
+ if (bfd_get_mach (info->output_bfd) == bfd_mach_arc_arcv2)
+ {
+ if (bfd_link_pic (info))
+ return &(plt_versions[ELF_ARCV2_PIC]);
+ else
+ return &(plt_versions[ELF_ARCV2_ABS]);
+ }
+ else
+ {
+ if (bfd_link_pic (info))
+ return &(plt_versions[ELF_ARC_PIC]);
+ else
+ return &(plt_versions[ELF_ARC_ABS]);
+ }
+ BFD_ASSERT(0);
+ return NULL;
+}
+
+static bfd_vma
+add_symbol_to_plt (struct bfd_link_info *info)
+{
+ struct elf_link_hash_table *htab = elf_hash_table (info);
+ bfd_vma ret;
+
+ struct plt_version_t *plt_data = arc_get_plt_version (info);
+
+ /* If this is the first .plt entry, make room for the special first
+ entry. */
+ if (htab->splt->size == 0)
+ htab->splt->size += plt_data->entry_size;
+
+ ret = htab->splt->size;
+
+ htab->splt->size += plt_data->elem_size;
+ ARC_DEBUG ("PLT_SIZE = %d\n", (int) htab->splt->size);
+
+ htab->sgotplt->size += GOT_ENTRY_SIZE;
+ htab->srelplt->size += sizeof (ElfNN_External_Rela);
+ return ret;
+}
+
+#define PLT_DO_RELOCS_FOR_ENTRY(ABFD, DS, RELOCS) \
+ plt_do_relocs_for_symbol (ABFD, DS, RELOCS, 0, 0)
+
+static void
+plt_do_relocs_for_symbol (bfd *abfd,
+ struct elf_link_hash_table *htab,
+ const struct plt_reloc *reloc,
+ bfd_vma plt_offset,
+ bfd_vma symbol_got_offset)
+{
+ while (SYM_ONLY (reloc->symbol) != LAST_RELOC)
+ {
+ bfd_vma relocation = 0;
+
+ switch (SYM_ONLY (reloc->symbol))
+ {
+ case SGOT:
+ relocation
+ = htab->sgotplt->output_section->vma
+ + htab->sgotplt->output_offset + symbol_got_offset;
+ break;
+ }
+ relocation += reloc->addend;
+
+ if (IS_RELATIVE (reloc->symbol))
+ {
+ bfd_vma reloc_offset = reloc->offset;
+ reloc_offset -= (IS_INSN_32 (reloc->symbol)) ? 4 : 0;
+ reloc_offset -= (IS_INSN_24 (reloc->symbol)) ? 2 : 0;
+
+ relocation -= htab->splt->output_section->vma
+ + htab->splt->output_offset
+ + plt_offset + reloc_offset;
+ }
+
+ /* TODO: being ME is not a property of the relocation but of the
+ section of which is applying the relocation. */
+ if (IS_MIDDLE_ENDIAN (reloc->symbol) && !bfd_big_endian (abfd))
+ {
+ relocation
+ = ((relocation & 0xffff0000) >> 16)
+ | ((relocation & 0xffff) << 16);
+ }
+
+ switch (reloc->size)
+ {
+ case 32:
+ bfd_put_32 (htab->splt->output_section->owner,
+ relocation,
+ htab->splt->contents + plt_offset + reloc->offset);
+ break;
+ }
+
+ reloc = &(reloc[1]); /* Jump to next relocation. */
+ }
+}
+
+static void
+relocate_plt_for_symbol (bfd *output_bfd,
+ struct bfd_link_info *info,
+ struct elf_link_hash_entry *h)
+{
+ struct plt_version_t *plt_data = arc_get_plt_version (info);
+ struct elf_link_hash_table *htab = elf_hash_table (info);
+ const struct elf_backend_data *bed;
+
+ bfd_vma plt_index = (h->plt.offset - plt_data->entry_size)
+ / plt_data->elem_size;
+ bfd_vma got_offset = (plt_index + 3) * GOT_ENTRY_SIZE;
+ bed = get_elf_backend_data (output_bfd);
+
+ ARC_DEBUG ("arc_info: PLT_OFFSET = %#lx, PLT_ENTRY_VMA = %#lx, \
+GOT_ENTRY_OFFSET = %#lx, GOT_ENTRY_VMA = %#lx, for symbol %s\n",
+ (long) h->plt.offset,
+ (long) (htab->splt->output_section->vma
+ + htab->splt->output_offset
+ + h->plt.offset),
+ (long) got_offset,
+ (long) (htab->sgotplt->output_section->vma
+ + htab->sgotplt->output_offset
+ + got_offset),
+ h->root.root.string);
+
+ {
+ bfd_vma i = 0;
+ uint16_t *ptr = (uint16_t *) plt_data->elem;
+
+ for (i = 0; i < plt_data->elem_size/2; i++)
+ {
+ uint16_t data = ptr[i];
+ bfd_put_16 (output_bfd,
+ (bfd_vma) data,
+ htab->splt->contents + h->plt.offset + (i*2));
+ }
+ }
+
+ plt_do_relocs_for_symbol (output_bfd, htab,
+ plt_data->elem_relocs,
+ h->plt.offset,
+ got_offset);
+
+ /* Fill in the entry in the global offset table. */
+ bfd_put_32 (output_bfd,
+ (bfd_vma) (htab->splt->output_section->vma
+ + htab->splt->output_offset),
+ htab->sgotplt->contents + got_offset);
+
+ /* TODO: Fill in the entry in the .rela.plt section. */
+ {
+ Elf_Internal_Rela rel;
+ bfd_byte *loc;
+
+ rel.r_offset = (htab->sgotplt->output_section->vma
+ + htab->sgotplt->output_offset
+ + got_offset);
+ rel.r_addend = 0;
+
+ BFD_ASSERT (h->dynindx != -1);
+ rel.r_info = ELFNN_R_INFO (h->dynindx, R_ARC_JMP_SLOT);
+
+ loc = htab->srelplt->contents;
+ loc += plt_index * sizeof (ElfNN_External_Rela); /* relA */
+ bed->s->swap_reloca_out (output_bfd, &rel, loc);
+ }
+}
+
+static void
+relocate_plt_for_entry (bfd *abfd,
+ struct bfd_link_info *info)
+{
+ struct plt_version_t *plt_data = arc_get_plt_version (info);
+ struct elf_link_hash_table *htab = elf_hash_table (info);
+
+ {
+ bfd_vma i = 0;
+ uint16_t *ptr = (uint16_t *) plt_data->entry;
+ for (i = 0; i < plt_data->entry_size/2; i++)
+ {
+ uint16_t data = ptr[i];
+ bfd_put_16 (abfd,
+ (bfd_vma) data,
+ htab->splt->contents + (i*2));
+ }
+ }
+ PLT_DO_RELOCS_FOR_ENTRY (abfd, htab, plt_data->entry_relocs);
+}
+
+/* Desc : Adjust a symbol defined by a dynamic object and referenced
+ by a regular object. The current definition is in some section of
+ the dynamic object, but we're not including those sections. We
+ have to change the definition to something the rest of the link can
+ understand. */
+
+static bfd_boolean
+elf_arc_adjust_dynamic_symbol (struct bfd_link_info *info,
+ struct elf_link_hash_entry *h)
+{
+ asection *s;
+ bfd *dynobj = (elf_hash_table (info))->dynobj;
+ struct elf_link_hash_table *htab = elf_hash_table (info);
+
+ if (h->type == STT_FUNC
+ || h->type == STT_GNU_IFUNC
+ || h->needs_plt == 1)
+ {
+ if (!bfd_link_pic (info) && !h->def_dynamic && !h->ref_dynamic)
+ {
+ /* This case can occur if we saw a PLT32 reloc in an input
+ file, but the symbol was never referred to by a dynamic
+ object. In such a case, we don't actually need to build
+ a procedure linkage table, and we can just do a PC32
+ reloc instead. */
+ BFD_ASSERT (h->needs_plt);
+ return TRUE;
+ }
+
+ /* Make sure this symbol is output as a dynamic symbol. */
+ if (h->dynindx == -1 && !h->forced_local
+ && !bfd_elf_link_record_dynamic_symbol (info, h))
+ return FALSE;
+
+ if (bfd_link_pic (info)
+ || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
+ {
+ bfd_vma loc = add_symbol_to_plt (info);
+
+ if (bfd_link_executable (info) && !h->def_regular)
+ {
+ h->root.u.def.section = htab->splt;
+ h->root.u.def.value = loc;
+ }
+ h->plt.offset = loc;
+ }
+ else
+ {
+ h->plt.offset = (bfd_vma) -1;
+ h->needs_plt = 0;
+ }
+ return TRUE;
+ }
+
+ /* If this is a weak symbol, and there is a real definition, the
+ processor independent code will have arranged for us to see the
+ real definition first, and we can just use the same value. */
+ if (h->is_weakalias)
+ {
+ struct elf_link_hash_entry *def = weakdef (h);
+ BFD_ASSERT (def->root.type == bfd_link_hash_defined);
+ h->root.u.def.section = def->root.u.def.section;
+ h->root.u.def.value = def->root.u.def.value;
+ return TRUE;
+ }
+
+ /* This is a reference to a symbol defined by a dynamic object which
+ is not a function. */
+
+ /* If we are creating a shared library, we must presume that the
+ only references to the symbol are via the global offset table.
+ For such cases we need not do anything here; the relocations will
+ be handled correctly by relocate_section. */
+ if (!bfd_link_executable (info))
+ return TRUE;
+
+ /* If there are no non-GOT references, we do not need a copy
+ relocation. */
+ if (!h->non_got_ref)
+ return TRUE;
+
+ /* If -z nocopyreloc was given, we won't generate them either. */
+ if (info->nocopyreloc)
+ {
+ h->non_got_ref = 0;
+ return TRUE;
+ }
+
+ /* We must allocate the symbol in our .dynbss section, which will
+ become part of the .bss section of the executable. There will be
+ an entry for this symbol in the .dynsym section. The dynamic
+ object will contain position independent code, so all references
+ from the dynamic object to this symbol will go through the global
+ offset table. The dynamic linker will use the .dynsym entry to
+ determine the address it must put in the global offset table, so
+ both the dynamic object and the regular object will refer to the
+ same memory location for the variable. */
+
+ if (htab == NULL)
+ return FALSE;
+
+ /* We must generate a R_ARC_COPY reloc to tell the dynamic linker to
+ copy the initial value out of the dynamic object and into the
+ runtime process image. We need to remember the offset into the
+ .rela.bss section we are going to use. */
+ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0)
+ {
+ struct elf_arc_link_hash_table *arc_htab = elf_arc_hash_table (info);
+
+ BFD_ASSERT (arc_htab->elf.srelbss != NULL);
+ arc_htab->elf.srelbss->size += sizeof (ElfNN_External_Rela);
+ h->needs_copy = 1;
+ }
+
+ /* TODO: Move this also to arc_hash_table. */
+ s = bfd_get_section_by_name (dynobj, ".dynbss");
+ BFD_ASSERT (s != NULL);
+
+ return _bfd_elf_adjust_dynamic_copy (info, h, s);
+}
+
+/* Function : elf_arc_finish_dynamic_symbol
+ Brief : Finish up dynamic symbol handling. We set the
+ contents of various dynamic sections here.
+ Args : output_bfd :
+ info :
+ h :
+ sym :
+ Returns : True/False as the return status. */
+
+static bfd_boolean
+elf_arc_finish_dynamic_symbol (bfd * output_bfd,
+ struct bfd_link_info *info,
+ struct elf_link_hash_entry *h,
+ Elf_Internal_Sym * sym)
+{
+ const struct elf_backend_data *bed;
+
+ bed = get_elf_backend_data (output_bfd);
+
+ if (h->plt.offset != (bfd_vma) -1)
+ {
+ relocate_plt_for_symbol (output_bfd, info, h);
+
+ if (!h->def_regular)
+ {
+ /* Mark the symbol as undefined, rather than as defined in
+ the .plt section. Leave the value alone. */
+ sym->st_shndx = SHN_UNDEF;
+ }
+ }
+
+
+ /* This function traverses list of GOT entries and
+ create respective dynamic relocs. */
+ /* TODO: Make function to get list and not access the list directly. */
+ /* TODO: Move function to relocate_section create this relocs eagerly. */
+ struct elf_arc_link_hash_entry *ah =
+ (struct elf_arc_link_hash_entry *) h;
+ create_got_dynrelocs_for_got_info (&ah->got_ents,
+ output_bfd,
+ info,
+ h);
+
+ if (h->needs_copy)
+ {
+ struct elf_arc_link_hash_table *arc_htab = elf_arc_hash_table (info);
+
+ if (arc_htab == NULL)
+ return FALSE;
+
+ if (h->dynindx == -1
+ || (h->root.type != bfd_link_hash_defined
+ && h->root.type != bfd_link_hash_defweak)
+ || arc_htab->elf.srelbss == NULL)
+ abort ();
+
+ bfd_vma rel_offset = (h->root.u.def.value
+ + h->root.u.def.section->output_section->vma
+ + h->root.u.def.section->output_offset);
+
+ bfd_byte * loc = arc_htab->elf.srelbss->contents
+ + (arc_htab->elf.srelbss->reloc_count * sizeof (ElfNN_External_Rela));
+ arc_htab->elf.srelbss->reloc_count++;
+
+ Elf_Internal_Rela rel;
+ rel.r_addend = 0;
+ rel.r_offset = rel_offset;
+
+ BFD_ASSERT (h->dynindx != -1);
+ rel.r_info = ELFNN_R_INFO (h->dynindx, R_ARC_COPY);
+
+ bed->s->swap_reloca_out (output_bfd, &rel, loc);
+ }
+
+ /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. */
+ if (strcmp (h->root.root.string, "_DYNAMIC") == 0
+ || strcmp (h->root.root.string, "__DYNAMIC") == 0
+ || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0)
+ sym->st_shndx = SHN_ABS;
+
+ return TRUE;
+}
+
+#define GET_SYMBOL_OR_SECTION(TAG, SYMBOL, SECTION) \
+ case TAG: \
+ if (SYMBOL != NULL) \
+ h = elf_link_hash_lookup (elf_hash_table (info), \
+ SYMBOL, FALSE, FALSE, TRUE); \
+ else if (SECTION != NULL) \
+ s = bfd_get_linker_section (dynobj, SECTION); \
+ break;
+
+
+struct obfd_info_group {
+ bfd *output_bfd;
+ struct bfd_link_info *info;
+};
+
+static bfd_boolean
+arc_create_forced_local_got_entries_for_tls (struct bfd_hash_entry *bh,
+ void *data)
+{
+ struct elf_arc_link_hash_entry * h =
+ (struct elf_arc_link_hash_entry *) bh;
+ struct obfd_info_group *tmp = (struct obfd_info_group *) data;
+
+ if (h->got_ents != NULL)
+ {
+ BFD_ASSERT (h);
+
+ struct got_entry *list = h->got_ents;
+
+ while (list != NULL)
+ {
+ create_got_dynrelocs_for_single_entry (list, tmp->output_bfd,
+ tmp->info,
+ (struct elf_link_hash_entry *) h);
+ list = list->next;
+ }
+ }
+
+ return TRUE;
+}
+
+
+/* Function : elf_arc_finish_dynamic_sections
+ Brief : Finish up the dynamic sections handling.
+ Args : output_bfd :
+ info :
+ h :
+ sym :
+ Returns : True/False as the return status. */
+
+static bfd_boolean
+elf_arc_finish_dynamic_sections (bfd * output_bfd,
+ struct bfd_link_info *info)
+{
+ struct elf_link_hash_table *htab = elf_hash_table (info);
+ bfd *dynobj = (elf_hash_table (info))->dynobj;
+ asection *sdyn = bfd_get_linker_section (dynobj, ".dynamic");
+ const struct elf_backend_data *bed = get_elf_backend_data (output_bfd);
+
+ if (sdyn)
+ {
+ ElfNN_External_Dyn *dyncon, *dynconend;
+
+ dyncon = (ElfNN_External_Dyn *) sdyn->contents;
+ dynconend
+ = (ElfNN_External_Dyn *) (sdyn->contents + sdyn->size);
+ for (; dyncon < dynconend; dyncon++)
+ {
+ Elf_Internal_Dyn internal_dyn;
+ bfd_boolean do_it = FALSE;
+
+ struct elf_link_hash_entry *h = NULL;
+ asection *s = NULL;
+
+ bed->s->swap_dyn_in (dynobj, dyncon, &internal_dyn);
+
+ switch (internal_dyn.d_tag)
+ {
+ GET_SYMBOL_OR_SECTION (DT_INIT, info->init_function, NULL)
+ GET_SYMBOL_OR_SECTION (DT_FINI, info->fini_function, NULL)
+ GET_SYMBOL_OR_SECTION (DT_PLTGOT, NULL, ".plt")
+ GET_SYMBOL_OR_SECTION (DT_JMPREL, NULL, ".rela.plt")
+ GET_SYMBOL_OR_SECTION (DT_PLTRELSZ, NULL, ".rela.plt")
+ GET_SYMBOL_OR_SECTION (DT_VERSYM, NULL, ".gnu.version")
+ GET_SYMBOL_OR_SECTION (DT_VERDEF, NULL, ".gnu.version_d")
+ GET_SYMBOL_OR_SECTION (DT_VERNEED, NULL, ".gnu.version_r")
+ default:
+ break;
+ }
+
+ /* In case the dynamic symbols should be updated with a symbol. */
+ if (h != NULL
+ && (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak))
+ {
+ asection *asec_ptr;
+
+ internal_dyn.d_un.d_val = h->root.u.def.value;
+ asec_ptr = h->root.u.def.section;
+ if (asec_ptr->output_section != NULL)
+ {
+ internal_dyn.d_un.d_val +=
+ (asec_ptr->output_section->vma
+ + asec_ptr->output_offset);
+ }
+ else
+ {
+ /* The symbol is imported from another shared
+ library and does not apply to this one. */
+ internal_dyn.d_un.d_val = 0;
+ }
+ do_it = TRUE;
+ }
+ else if (s != NULL) /* With a section information. */
+ {
+ switch (internal_dyn.d_tag)
+ {
+ case DT_PLTGOT:
+ case DT_JMPREL:
+ case DT_VERSYM:
+ case DT_VERDEF:
+ case DT_VERNEED:
+ internal_dyn.d_un.d_ptr = (s->output_section->vma
+ + s->output_offset);
+ do_it = TRUE;
+ break;
+
+ case DT_PLTRELSZ:
+ internal_dyn.d_un.d_val = s->size;
+ do_it = TRUE;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (do_it)
+ bed->s->swap_dyn_out (output_bfd, &internal_dyn, dyncon);
+ }
+
+ if (htab->splt->size > 0)
+ {
+ relocate_plt_for_entry (output_bfd, info);
+ }
+
+ /* TODO: Validate this. */
+ if (htab->srelplt->output_section != bfd_abs_section_ptr)
+ elf_section_data (htab->srelplt->output_section)
+ ->this_hdr.sh_entsize = GOT_ENTRY_SIZE * 3;
+ }
+
+ /* Fill in the first three entries in the global offset table. */
+ if (htab->sgot)
+ {
+ struct elf_link_hash_entry *h;
+ h = elf_link_hash_lookup (elf_hash_table (info), "_GLOBAL_OFFSET_TABLE_",
+ FALSE, FALSE, TRUE);
+
+ if (h != NULL && h->root.type != bfd_link_hash_undefined
+ && h->root.u.def.section != NULL)
+ {
+ asection *sec = h->root.u.def.section;
+
+ if (sdyn == NULL) {
+ write_in_got(output_bfd, (bfd_vma) 0,
+ sec->contents);
+ }
+ else {
+ write_in_got(output_bfd,
+ sdyn->output_section->vma + sdyn->output_offset,
+ sec->contents);
+ }
+ write_in_got(output_bfd, (bfd_vma) 0, sec->contents + (GOT_ENTRY_SIZE));
+ write_in_got(output_bfd, (bfd_vma) 0, sec->contents + (GOT_ENTRY_SIZE * 2));
+ }
+ }
+
+ struct obfd_info_group group;
+ group.output_bfd = output_bfd;
+ group.info = info;
+ bfd_hash_traverse (&info->hash->table,
+ arc_create_forced_local_got_entries_for_tls, &group);
+
+ return TRUE;
+}
+
+#define ADD_DYNAMIC_SYMBOL(NAME, TAG) \
+ h = elf_link_hash_lookup (elf_hash_table (info), \
+ NAME, FALSE, FALSE, FALSE); \
+ if ((h != NULL && (h->ref_regular || h->def_regular))) \
+ if (! _bfd_elf_add_dynamic_entry (info, TAG, 0)) \
+ return FALSE;
+
+/* Set the sizes of the dynamic sections. */
+static bfd_boolean
+elf_arc_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ struct bfd_link_info *info)
+{
+ bfd *dynobj;
+ asection *s;
+ bfd_boolean relocs_exist = FALSE;
+ bfd_boolean reltext_exist = FALSE;
+ struct elf_link_hash_table *htab = elf_hash_table (info);
+
+ dynobj = htab->dynobj;
+ BFD_ASSERT (dynobj != NULL);
+
+ if (htab->dynamic_sections_created)
+ {
+ struct elf_link_hash_entry *h;
+
+ /* Set the contents of the .interp section to the
+ interpreter. */
+ if (bfd_link_executable (info) && !info->nointerp)
+ {
+ s = bfd_get_section_by_name (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+ s->size = sizeof (ELFNN_DYNAMIC_INTERPRETER);
+ s->contents = (unsigned char *) ELFNN_DYNAMIC_INTERPRETER;
+ }
+
+ /* Add some entries to the .dynamic section. We fill in some of
+ the values later, in elf_bfd_final_link, but we must add the
+ entries now so that we know the final size of the .dynamic
+ section. Checking if the .init section is present. We also
+ create DT_INIT and DT_FINI entries if the init_str has been
+ changed by the user. */
+ ADD_DYNAMIC_SYMBOL (info->init_function, DT_INIT);
+ ADD_DYNAMIC_SYMBOL (info->fini_function, DT_FINI);
+ }
+ else
+ {
+ /* We may have created entries in the .rela.got section.
+ However, if we are not creating the dynamic sections, we will
+ not actually use these entries. Reset the size of .rela.got,
+ which will cause it to get stripped from the output file
+ below. */
+ if (htab->srelgot != NULL)
+ htab->srelgot->size = 0;
+ }
+
+ for (s = dynobj->sections; s != NULL; s = s->next)
+ {
+ if ((s->flags & SEC_LINKER_CREATED) == 0)
+ continue;
+
+ if (s == htab->splt
+ || s == htab->sgot
+ || s == htab->sgotplt
+ || s == htab->sdynbss)
+ {
+ /* Strip this section if we don't need it. */
+ }
+ else if (strncmp (s->name, ".rela", 5) == 0)
+ {
+ if (s->size != 0 && s != htab->srelplt)
+ {
+ if (!reltext_exist)
+ {
+ const char *name = s->name + 5;
+ bfd *ibfd;
+ for (ibfd = info->input_bfds; ibfd; ibfd = ibfd->link.next)
+ if (bfd_get_flavour (ibfd) == bfd_target_elf_flavour
+ && ibfd->flags & DYNAMIC)
+ {
+ asection *target = bfd_get_section_by_name (ibfd, name);
+ if (target != NULL
+ && elf_section_data (target)->sreloc == s
+ && ((target->output_section->flags
+ & (SEC_READONLY | SEC_ALLOC))
+ == (SEC_READONLY | SEC_ALLOC)))
+ {
+ reltext_exist = TRUE;
+ break;
+ }
+ }
+ }
+ relocs_exist = TRUE;
+ }
+
+ /* We use the reloc_count field as a counter if we need to
+ copy relocs into the output file. */
+ s->reloc_count = 0;
+ }
+ else
+ {
+ /* It's not one of our sections, so don't allocate space. */
+ continue;
+ }
+
+ if (s->size == 0)
+ {
+ s->flags |= SEC_EXCLUDE;
+ continue;
+ }
+
+ if ((s->flags & SEC_HAS_CONTENTS) == 0)
+ continue;
+
+ /* Allocate memory for the section contents. */
+ s->contents = bfd_zalloc (dynobj, s->size);
+ if (s->contents == NULL)
+ return FALSE;
+ }
+
+ if (htab->dynamic_sections_created)
+ {
+ /* TODO: Check if this is needed. */
+ if (!bfd_link_pic (info))
+ if (!_bfd_elf_add_dynamic_entry (info, DT_DEBUG, 0))
+ return FALSE;
+
+ if (htab->splt && (htab->splt->flags & SEC_EXCLUDE) == 0)
+ if (!_bfd_elf_add_dynamic_entry (info, DT_PLTGOT, 0)
+ || !_bfd_elf_add_dynamic_entry (info, DT_PLTRELSZ, 0)
+ || !_bfd_elf_add_dynamic_entry (info, DT_PLTREL, DT_RELA)
+ || !_bfd_elf_add_dynamic_entry (info, DT_JMPREL, 0))
+ return FALSE;
+
+ if (relocs_exist)
+ if (!_bfd_elf_add_dynamic_entry (info, DT_RELA, 0)
+ || !_bfd_elf_add_dynamic_entry (info, DT_RELASZ, 0)
+ || !_bfd_elf_add_dynamic_entry (info, DT_RELAENT,
+ sizeof (ElfNN_External_Rela)))
+ return FALSE;
+
+ if (reltext_exist)
+ if (!_bfd_elf_add_dynamic_entry (info, DT_TEXTREL, 0))
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+
+/* Classify dynamic relocs such that -z combreloc can reorder and combine
+ them. */
+static enum elf_reloc_type_class
+arc_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
+ const asection *rel_sec ATTRIBUTE_UNUSED,
+ const Elf_Internal_Rela *rela)
+{
+ switch ((int) ELFNN_R_TYPE (rela->r_info))
+ {
+ case R_ARC_RELATIVE:
+ return reloc_class_relative;
+ case R_ARC_JMP_SLOT:
+ return reloc_class_plt;
+ case R_ARC_COPY:
+ return reloc_class_copy;
+ /* TODO: Needed in future to support ifunc. */
+ /*
+ case R_ARC_IRELATIVE:
+ return reloc_class_ifunc;
+ */
+ default:
+ return reloc_class_normal;
+ }
+}
+
+/* We use this so we can override certain functions
+ (though currently we don't). */
+
+const struct elf_size_info arc_elfNN_size_info =
+ {
+ sizeof (ElfNN_External_Ehdr),
+ sizeof (ElfNN_External_Phdr),
+ sizeof (ElfNN_External_Shdr),
+ sizeof (ElfNN_External_Rel),
+ sizeof (ElfNN_External_Rela),
+ sizeof (ElfNN_External_Sym),
+ sizeof (ElfNN_External_Dyn),
+ sizeof (Elf_External_Note),
+ 4,
+ 1,
+ ARCH_SIZE,
+ LOG_FILE_ALIGN,
+ ELFCLASSNN, EV_CURRENT,
+ bfd_elfNN_write_out_phdrs,
+ bfd_elfNN_write_shdrs_and_ehdr,
+ bfd_elfNN_checksum_contents,
+ bfd_elfNN_write_relocs,
+ bfd_elfNN_swap_symbol_in,
+ bfd_elfNN_swap_symbol_out,
+ bfd_elfNN_slurp_reloc_table,
+ bfd_elfNN_slurp_symbol_table,
+ bfd_elfNN_swap_dyn_in,
+ bfd_elfNN_swap_dyn_out,
+ bfd_elfNN_swap_reloc_in,
+ bfd_elfNN_swap_reloc_out,
+ bfd_elfNN_swap_reloca_in,
+ bfd_elfNN_swap_reloca_out
+ };
+
+/* GDB expects general purpose registers to be in section .reg. However Linux
+ kernel doesn't create this section and instead writes registers to NOTE
+ section. It is up to the binutils to create a pseudo-section .reg from the
+ contents of NOTE. Also BFD will read pid and signal number from NOTE. This
+ function relies on offsets inside elf_prstatus structure in Linux to be
+ stable. */
+
+static bfd_boolean
+elfNN_arc_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
+{
+ int offset;
+ size_t size;
+
+ switch (note->descsz)
+ {
+ default:
+ return FALSE;
+
+ case 236: /* sizeof (struct elf_prstatus) on Linux/arc. */
+ /* pr_cursig */
+ elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
+ /* pr_pid */
+ elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
+ /* pr_regs */
+ offset = 72;
+ size = (40 * 4); /* There are 40 registers in user_regs_struct. */
+ break;
+ }
+ /* Make a ".reg/999" section. */
+ return _bfd_elfcore_make_pseudosection (abfd, ".reg", size,
+ note->descpos + offset);
+}
+
+/* Determine whether an object attribute tag takes an integer, a
+ string or both. */
+
+static int
+elfNN_arc_obj_attrs_arg_type (int tag)
+{
+ if (tag == Tag_ARC_CPU_name
+ || tag == Tag_ARC_ISA_config
+ || tag == Tag_ARC_ISA_apex)
+ return ATTR_TYPE_FLAG_STR_VAL;
+ else if (tag < (Tag_ARC_ISA_mpy_option + 1))
+ return ATTR_TYPE_FLAG_INT_VAL;
+ else
+ return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
+}
+
+/* Attribute numbers >=14 can be safely ignored. */
+
+static bfd_boolean
+elfNN_arc_obj_attrs_handle_unknown (bfd *abfd, int tag)
+{
+ if ((tag & 127) < (Tag_ARC_ISA_mpy_option + 1))
+ {
+ _bfd_error_handler
+ (_("%pB: unknown mandatory ARC object attribute %d"),
+ abfd, tag);
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+ else
+ {
+ _bfd_error_handler
+ (_("warning: %pB: unknown ARC object attribute %d"),
+ abfd, tag);
+ return TRUE;
+ }
+}
+
+/* Handle an ARC specific section when reading an object file. This is
+ called when bfd_section_from_shdr finds a section with an unknown
+ type. */
+
+static bfd_boolean
+elfNN_arc_section_from_shdr (bfd *abfd,
+ Elf_Internal_Shdr * hdr,
+ const char *name,
+ int shindex)
+{
+ switch (hdr->sh_type)
+ {
+ case 0x0c: /* MWDT specific section, don't complain about it. */
+ case SHT_ARC_ATTRIBUTES:
+ break;
+
+ default:
+ return FALSE;
+ }
+
+ if (!_bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
+ return FALSE;
+
+ return TRUE;
+}
+
+/* Delete a number of bytes from a given section while relaxing. */
+
+static bfd_boolean
+arc_relax_delete_bytes (struct bfd_link_info *link_info, bfd *abfd,
+ asection *sec, bfd_vma addr, int count)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ unsigned int sec_shndx;
+ bfd_byte *contents;
+ Elf_Internal_Rela *irel, *irelend;
+ bfd_vma toaddr;
+ Elf_Internal_Sym *isym;
+ Elf_Internal_Sym *isymend;
+ struct elf_link_hash_entry **sym_hashes;
+ struct elf_link_hash_entry **end_hashes;
+ struct elf_link_hash_entry **start_hashes;
+ unsigned int symcount;
+
+ sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
+
+ contents = elf_section_data (sec)->this_hdr.contents;
+
+ toaddr = sec->size;
+
+ irel = elf_section_data (sec)->relocs;
+ irelend = irel + sec->reloc_count;
+
+ /* Actually delete the bytes. */
+ memmove (contents + addr, contents + addr + count,
+ (size_t) (toaddr - addr - count));
+ sec->size -= count;
+
+ /* Adjust all the relocs. */
+ for (irel = elf_section_data (sec)->relocs; irel < irelend; irel++)
+ /* Get the new reloc address. */
+ if ((irel->r_offset > addr && irel->r_offset < toaddr))
+ irel->r_offset -= count;
+
+ /* Adjust the local symbols defined in this section. */
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ isym = (Elf_Internal_Sym *) symtab_hdr->contents;
+ for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
+ {
+ if (isym->st_shndx == sec_shndx
+ && isym->st_value > addr
+ && isym->st_value <= toaddr)
+ {
+ /* Adjust the addend of SWITCH relocations in this section,
+ which reference this local symbol. */
+ isym->st_value -= count;
+ }
+ }
+
+ /* Now adjust the global symbols defined in this section. */
+ symcount = (symtab_hdr->sh_size / sizeof (ElfNN_External_Sym)
+ - symtab_hdr->sh_info);
+ sym_hashes = start_hashes = elf_sym_hashes (abfd);
+ end_hashes = sym_hashes + symcount;
+
+ for (; sym_hashes < end_hashes; sym_hashes++)
+ {
+ struct elf_link_hash_entry *sym_hash = *sym_hashes;
+
+ /* The '--wrap SYMBOL' option is causing a pain when the object file,
+ containing the definition of __wrap_SYMBOL, includes a direct
+ call to SYMBOL as well. Since both __wrap_SYMBOL and SYMBOL reference
+ the same symbol (which is __wrap_SYMBOL), but still exist as two
+ different symbols in 'sym_hashes', we don't want to adjust
+ the global symbol __wrap_SYMBOL twice.
+ This check is only relevant when symbols are being wrapped. */
+ if (link_info->wrap_hash != NULL)
+ {
+ struct elf_link_hash_entry **cur_sym_hashes;
+
+ /* Loop only over the symbols whom been already checked. */
+ for (cur_sym_hashes = start_hashes; cur_sym_hashes < sym_hashes;
+ cur_sym_hashes++)
+ /* If the current symbol is identical to 'sym_hash', that means
+ the symbol was already adjusted (or at least checked). */
+ if (*cur_sym_hashes == sym_hash)
+ break;
+
+ /* Don't adjust the symbol again. */
+ if (cur_sym_hashes < sym_hashes)
+ continue;
+ }
+
+ if ((sym_hash->root.type == bfd_link_hash_defined
+ || sym_hash->root.type == bfd_link_hash_defweak)
+ && sym_hash->root.u.def.section == sec)
+ {
+ /* As above, adjust the value if needed. */
+ if (sym_hash->root.u.def.value > addr
+ && sym_hash->root.u.def.value <= toaddr)
+ sym_hash->root.u.def.value -= count;
+
+ /* As above, adjust the size if needed. */
+ if (sym_hash->root.u.def.value <= addr
+ && sym_hash->root.u.def.value + sym_hash->size > addr
+ && sym_hash->root.u.def.value + sym_hash->size <= toaddr)
+ sym_hash->size -= count;
+ }
+ }
+
+ return TRUE;
+}
+
+/* Check Tag_ARC_PCS_config if we can relax. */
+static bfd_boolean
+arc_can_relax_p (bfd *abfd)
+{
+ obj_attribute *attr = elf_known_obj_attributes_proc (abfd);
+
+ if (attr[Tag_ARC_PCS_config].i & 0x100)
+ return TRUE;
+ return FALSE;
+}
+
+/* Relaxation hook.
+
+ These are the current relaxing opportunities available:
+
+ * R_ARC_GOTPC32 => R_ARC_PCREL.
+ * R_ARC_S25W_PCREL => R_ARC_S13_PCREL.
+
+ This is a two step relaxation procedure, in the first round, we
+ relax all the above opportunities. In the second round, we deal
+ with function align by removing unnecessary NOP_S placed by the
+ assembler.
+
+ Inspired from CRX and RISCV backends. */
+
+static bfd_boolean
+arc_elf_relax_section (bfd *abfd, asection *sec,
+ struct bfd_link_info *link_info, bfd_boolean *again)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ Elf_Internal_Rela *internal_relocs;
+ Elf_Internal_Rela *irel, *irelend;
+ bfd_byte *contents = NULL;
+ Elf_Internal_Sym *isymbuf = NULL;
+ bfd_boolean do_relax = FALSE;
+
+ /* Assume nothing changes. */
+ *again = FALSE;
+
+ /* Check if we can do size related relaxation. */
+ do_relax = arc_can_relax_p (abfd);
+
+ /* We don't have to do anything for a relocatable link, if this
+ section does not have relocs, or if this is not a code
+ section. */
+ if (bfd_link_relocatable (link_info)
+ || (sec->flags & SEC_RELOC) == 0
+ || sec->reloc_count == 0
+ || sec->sec_flg0
+ || (sec->flags & SEC_CODE) == 0)
+ return TRUE;
+
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+
+ /* Get a copy of the native relocations. */
+ internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL,
+ link_info->keep_memory);
+ if (internal_relocs == NULL)
+ goto error_return;
+
+ /* Walk through them looking for relaxing opportunities. */
+ irelend = internal_relocs + sec->reloc_count;
+ for (irel = internal_relocs; irel < irelend; irel++)
+ {
+ asection *sym_sec;
+ struct elf_link_hash_entry *htop = NULL;
+ bfd_vma symval;
+
+ /* If this isn't something that can be relaxed, then ignore this
+ reloc. */
+ if (ELFNN_R_TYPE (irel->r_info) != (int) R_ARC_GOTPC32
+ && ELFNN_R_TYPE (irel->r_info) != (int) R_ARC_S25W_PCREL
+ && ELFNN_R_TYPE (irel->r_info) != (int) R_ARC_ALIGN)
+ continue;
+
+ /* Get the section contents if we haven't done so already. */
+ if (contents == NULL)
+ {
+ /* Get cached copy if it exists. */
+ if (elf_section_data (sec)->this_hdr.contents != NULL)
+ contents = elf_section_data (sec)->this_hdr.contents;
+ /* Go get them off disk. */
+ else if (!bfd_malloc_and_get_section (abfd, sec, &contents))
+ goto error_return;
+ }
+
+ /* Read this BFD's local symbols if we haven't done so already. */
+ if (isymbuf == NULL && symtab_hdr->sh_info != 0)
+ {
+ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
+ if (isymbuf == NULL)
+ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
+ symtab_hdr->sh_info, 0,
+ NULL, NULL, NULL);
+ if (isymbuf == NULL)
+ goto error_return;
+ }
+
+ /* Get the value of the symbol referred to by the reloc. */
+ if (ELFNN_R_SYM (irel->r_info) < symtab_hdr->sh_info)
+ {
+ /* A local symbol. */
+ Elf_Internal_Sym *isym;
+
+ isym = isymbuf + ELFNN_R_SYM (irel->r_info);
+ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
+ symval = isym->st_value;
+ /* If the reloc is absolute, it will not have
+ a symbol or section associated with it. */
+ if (sym_sec)
+ symval += sym_sec->output_section->vma
+ + sym_sec->output_offset;
+ }
+ else
+ {
+ /* An external symbol. */
+ unsigned int indx = ELFNN_R_SYM (irel->r_info) - symtab_hdr->sh_info;
+ htop = elf_sym_hashes (abfd)[indx];
+
+ BFD_ASSERT (htop != NULL);
+ if (htop->root.type != bfd_link_hash_defined
+ && htop->root.type != bfd_link_hash_defweak)
+ /* This appears to be a reference to an undefined
+ symbol. Just ignore it--it will be caught by the
+ regular reloc processing. */
+ continue;
+
+ symval = (htop->root.u.def.value
+ + htop->root.u.def.section->output_section->vma
+ + htop->root.u.def.section->output_offset);
+ sym_sec = htop->root.u.def.section;
+ }
+
+ if (ELFNN_R_TYPE (irel->r_info) == (int) R_ARC_GOTPC32
+ && SYMBOL_REFERENCES_LOCAL (link_info, htop)
+ && link_info->relax_pass == 0)
+ {
+ unsigned int code;
+
+ /* Get the opcode. */
+ code = bfd_get_32_me (abfd, contents + irel->r_offset - 4);
+
+ /* Note that we've changed the relocs, section contents, etc. */
+ elf_section_data (sec)->relocs = internal_relocs;
+ elf_section_data (sec)->this_hdr.contents = contents;
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+
+ /* Fix the relocation's type. */
+ irel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info), R_ARC_PC32);
+
+ /* ld rA,[pcl,symbol@tgot] -> add rA,pcl,symbol@pcl. */
+ /* 0010 0bbb aa11 0ZZX DBBB 1111 10AA AAAA.
+ 111 00 000 0111 xx xxxx*/
+ code &= ~0x27307F80;
+ BFD_ASSERT (code <= 62UL);
+ code |= 0x27007F80;
+
+ /* Write back the new instruction. */
+ bfd_put_32_me (abfd, code, contents + irel->r_offset - 4);
+
+ /* The size isn't changed, don't redo. */
+ }
+
+ /* Any of the next relax rules are changing the size, allow them
+ is assembler was informed. */
+ if (!do_relax)
+ continue;
+
+ if (ELFNN_R_TYPE (irel->r_info) == (int) R_ARC_S25W_PCREL
+ && link_info->relax_pass == 0)
+ {
+ unsigned int code;
+ bfd_vma value = symval + irel->r_addend;
+ bfd_vma dot, gap;
+
+ /* Get the address (PCL) of this instruction. */
+ dot = (sec->output_section->vma
+ + sec->output_offset + irel->r_offset) & ~0x03;
+
+ /* Compute the distance from this insn to the branch target. */
+ gap = value - dot;
+
+ /* Check if the gap falls in the range that can be
+ accomodated in 13bit signed range (32-bit aligned). */
+ if ((int) gap < -4094 || (int) gap > 4097 || ((int) gap & 0x3) != 0)
+ continue;
+
+ /* Get the opcode. */
+ code = bfd_get_32_me (abfd, contents + irel->r_offset);
+ /* bl @symb@pcl -> bl_s @symb@pcl. */
+ /* 0000 1sss ssss ss10 SSSS SSSS SSNR tttt. */
+ BFD_ASSERT ((code & 0xF8030000) == 0x08020000);
+
+ /* Check for delay slot bit. */
+ if (code & 0x20)
+ continue;
+
+ /* Note that we've changed the relocs, section contents, etc. */
+ elf_section_data (sec)->relocs = internal_relocs;
+ elf_section_data (sec)->this_hdr.contents = contents;
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+
+ /* Fix the relocation's type. */
+ irel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info),
+ R_ARC_S13_PCREL);
+
+ /* Write back bl_s instruction. */
+ bfd_put_16 (abfd, 0xF800, contents + irel->r_offset);
+ /* Delete two bytes of data. */
+ if (!arc_relax_delete_bytes (link_info, abfd, sec,
+ irel->r_offset + 2, 2))
+ goto error_return;
+
+ *again = TRUE;
+ }
+
+ if (ELFNN_R_TYPE (irel->r_info) == (int) R_ARC_ALIGN
+ && link_info->relax_pass == 1)
+ {
+ bfd_vma aligned_addr;
+ bfd_vma nop_bytes;
+ bfd_vma alignment = 4;
+
+ if (irel->r_addend == 2)
+ alignment = 2;
+ aligned_addr = ((irel->r_offset - 1) & ~(alignment - 1)) + alignment;
+ nop_bytes = aligned_addr - irel->r_offset;
+
+ /* Cannot remove more than we have left. */
+ BFD_ASSERT (irel->r_addend >= nop_bytes);
+ /* I should be always 16bit multiple quantum. */
+ BFD_ASSERT (nop_bytes == 0 || nop_bytes == 2);
+
+ /* Once we aligned we cannot relax anything else. */
+ sec->sec_flg0 = TRUE;
+
+ /* Note that we've changed the relocs, section contents, etc. */
+ elf_section_data (sec)->relocs = internal_relocs;
+ elf_section_data (sec)->this_hdr.contents = contents;
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+
+ /* Delete the relocation's type. */
+ irel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info),
+ R_ARC_NONE);
+
+ /* Add an NOP_S if needed. */
+ if (nop_bytes != 0)
+ bfd_put_16 (abfd, 0x78E0, contents + irel->r_offset);
+
+ /* Delete nop_bytes bytes of data. */
+ if (!arc_relax_delete_bytes (link_info, abfd, sec,
+ irel->r_offset + nop_bytes,
+ irel->r_addend - nop_bytes))
+ goto error_return;
+
+ *again = TRUE;
+ }
+ }
+
+ if (isymbuf != NULL
+ && symtab_hdr->contents != (unsigned char *) isymbuf)
+ {
+ if (!link_info->keep_memory)
+ free (isymbuf);
+ else
+ /* Cache the symbols for elf_link_input_bfd. */
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+ }
+
+ if (contents != NULL
+ && elf_section_data (sec)->this_hdr.contents != contents)
+ {
+ if (!link_info->keep_memory)
+ free (contents);
+ else
+ /* Cache the section contents for elf_link_input_bfd. */
+ elf_section_data (sec)->this_hdr.contents = contents;
+ }
+
+ if (elf_section_data (sec)->relocs != internal_relocs)
+ free (internal_relocs);
+
+ return TRUE;
+
+ error_return:
+ if (symtab_hdr->contents != (unsigned char *) isymbuf)
+ free (isymbuf);
+ if (elf_section_data (sec)->this_hdr.contents != contents)
+ free (contents);
+ if (elf_section_data (sec)->relocs != internal_relocs)
+ free (internal_relocs);
+
+ return FALSE;
+}
+
+#define TARGET_LITTLE_SYM arc_elfNN_le_vec
+#define TARGET_LITTLE_NAME "elfNN-littlearc"
+#define TARGET_BIG_SYM arc_elfNN_be_vec
+#define TARGET_BIG_NAME "elfNN-bigarc"
+#define ELF_ARCH bfd_arch_arc
+#define ELF_TARGET_ID ARC_ELF_DATA
+
+#if ARCH_SIZE == 32
+# define ELF_MACHINE_CODE EM_ARC_COMPACT
+# define ELF_MACHINE_ALT1 EM_ARC_COMPACT2
+# define ELF_MACHINE_ALT2 EM_ARC_COMPACT3_64
+#else
+# define ELF_MACHINE_CODE EM_ARC_COMPACT3_64
+# define ELF_MACHINE_ALT1 EM_ARC_COMPACT2
+/* To be deprecated and instead used for ARCv3 32 bit machine. */
+# define ELF_MACHINE_ALT2 EM_ARC_COMPACT
+#endif
+
+#define ELF_MAXPAGESIZE 0x2000
+
+#define bfd_elfNN_bfd_link_hash_table_create arc_elf_link_hash_table_create
+
+#define bfd_elfNN_bfd_merge_private_bfd_data arc_elf_merge_private_bfd_data
+#define bfd_elfNN_bfd_reloc_type_lookup arc_elfNN_bfd_reloc_type_lookup
+#define bfd_elfNN_bfd_set_private_flags arc_elf_set_private_flags
+#define bfd_elfNN_bfd_print_private_bfd_data arc_elf_print_private_bfd_data
+#define bfd_elfNN_bfd_copy_private_bfd_data arc_elf_copy_private_bfd_data
+#define bfd_elfNN_bfd_relax_section arc_elf_relax_section
+
+#define elf_backend_size_info arc_elfNN_size_info
+
+#define elf_info_to_howto_rel arc_info_to_howto_rel
+#define elf_backend_object_p arc_elf_object_p
+#define elf_backend_final_write_processing arc_elf_final_write_processing
+
+#define elf_backend_relocate_section elf_arc_relocate_section
+#define elf_backend_check_relocs elf_arc_check_relocs
+#define elf_backend_create_dynamic_sections _bfd_elf_create_dynamic_sections
+
+#define elf_backend_reloc_type_class arc_reloc_type_class
+
+#define elf_backend_adjust_dynamic_symbol elf_arc_adjust_dynamic_symbol
+#define elf_backend_finish_dynamic_symbol elf_arc_finish_dynamic_symbol
+
+#define elf_backend_finish_dynamic_sections elf_arc_finish_dynamic_sections
+#define elf_backend_size_dynamic_sections elf_arc_size_dynamic_sections
+
+#define elf_backend_can_gc_sections 1
+#define elf_backend_want_got_plt 1
+#define elf_backend_plt_readonly 1
+#define elf_backend_rela_plts_and_copies_p 1
+#define elf_backend_want_plt_sym 0
+#define elf_backend_got_header_size (GOT_ENTRY_SIZE * 3)
+#define elf_backend_dtrel_excludes_plt 1
+
+#define elf_backend_may_use_rel_p 0
+#define elf_backend_may_use_rela_p 1
+#define elf_backend_default_use_rela_p 1
+
+#define elf_backend_grok_prstatus elfNN_arc_grok_prstatus
+
+#define elf_backend_default_execstack 0
+
+#undef elf_backend_obj_attrs_vendor
+#define elf_backend_obj_attrs_vendor "ARC"
+#undef elf_backend_obj_attrs_section
+#define elf_backend_obj_attrs_section ".ARC.attributes"
+#undef elf_backend_obj_attrs_arg_type
+#define elf_backend_obj_attrs_arg_type elfNN_arc_obj_attrs_arg_type
+#undef elf_backend_obj_attrs_section_type
+#define elf_backend_obj_attrs_section_type SHT_ARC_ATTRIBUTES
+#define elf_backend_obj_attrs_handle_unknown elfNN_arc_obj_attrs_handle_unknown
+
+#define elf_backend_section_from_shdr elfNN_arc_section_from_shdr
+
+#include "elfNN-target.h"
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index b97534fc9fe..66309455417 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -1834,6 +1834,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARC_16",
"BFD_RELOC_ARC_24",
"BFD_RELOC_ARC_32",
+ "BFD_RELOC_ARC_64",
"BFD_RELOC_ARC_N8",
"BFD_RELOC_ARC_N16",
"BFD_RELOC_ARC_N24",
@@ -1898,6 +1899,25 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARC_S21H_PCREL_PLT",
"BFD_RELOC_ARC_NPS_CMEM16",
"BFD_RELOC_ARC_JLI_SECTOFF",
+ "BFD_RELOC_ARC_S7H_PCREL",
+ "BFD_RELOC_ARC_S8H_PCREL",
+ "BFD_RELOC_ARC_S9H_PCREL",
+ "BFD_RELOC_ARC_S10H_PCREL",
+ "BFD_RELOC_ARC_S13H_PCREL",
+ "BFD_RELOC_ARC_ALIGN",
+ "BFD_RELOC_ARC_ADD8",
+ "BFD_RELOC_ARC_ADD16",
+ "BFD_RELOC_ARC_SUB8",
+ "BFD_RELOC_ARC_SUB16",
+ "BFD_RELOC_ARC_SUB32",
+ "BFD_RELOC_ARC_LO32",
+ "BFD_RELOC_ARC_HI32",
+ "BFD_RELOC_ARC_LO32_ME",
+ "BFD_RELOC_ARC_HI32_ME",
+ "BFD_RELOC_ARC_N64",
+ "BFD_RELOC_ARC_SDA_LDST3",
+ "BFD_RELOC_ARC_NLO32",
+ "BFD_RELOC_ARC_NLO32_ME",
"BFD_RELOC_BFIN_16_IMM",
"BFD_RELOC_BFIN_16_HIGH",
"BFD_RELOC_BFIN_4_PCREL",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index 9aba84ca81e..c2dfd10e879 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -3588,6 +3588,8 @@ ENUMX
BFD_RELOC_ARC_24
ENUMX
BFD_RELOC_ARC_32
+ENUMX
+ BFD_RELOC_ARC_64
ENUMX
BFD_RELOC_ARC_N8
ENUMX
@@ -3716,6 +3718,44 @@ ENUMX
BFD_RELOC_ARC_NPS_CMEM16
ENUMX
BFD_RELOC_ARC_JLI_SECTOFF
+ENUMX
+ BFD_RELOC_ARC_S7H_PCREL
+ENUMX
+ BFD_RELOC_ARC_S8H_PCREL
+ENUMX
+ BFD_RELOC_ARC_S9H_PCREL
+ENUMX
+ BFD_RELOC_ARC_S10H_PCREL
+ENUMX
+ BFD_RELOC_ARC_S13H_PCREL
+ENUMX
+ BFD_RELOC_ARC_ALIGN
+ENUMX
+ BFD_RELOC_ARC_ADD8
+ENUMX
+ BFD_RELOC_ARC_ADD16
+ENUMX
+ BFD_RELOC_ARC_SUB8
+ENUMX
+ BFD_RELOC_ARC_SUB16
+ENUMX
+ BFD_RELOC_ARC_SUB32
+ENUMX
+ BFD_RELOC_ARC_LO32
+ENUMX
+ BFD_RELOC_ARC_HI32
+ENUMX
+ BFD_RELOC_ARC_LO32_ME
+ENUMX
+ BFD_RELOC_ARC_HI32_ME
+ENUMX
+ BFD_RELOC_ARC_N64
+ENUMX
+ BFD_RELOC_ARC_SDA_LDST3
+ENUMX
+ BFD_RELOC_ARC_NLO32
+ENUMX
+ BFD_RELOC_ARC_NLO32_ME
ENUMDOC
ARC relocs.
diff --git a/bfd/targets.c b/bfd/targets.c
index 0732c5e4292..77a6c225070 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -677,6 +677,7 @@ extern const bfd_target am33_elf32_linux_vec;
extern const bfd_target aout_vec;
extern const bfd_target arc_elf32_be_vec;
extern const bfd_target arc_elf32_le_vec;
+extern const bfd_target arc_elf64_le_vec;
extern const bfd_target arm_elf32_be_vec;
extern const bfd_target arm_elf32_le_vec;
extern const bfd_target arm_elf32_fdpic_be_vec;
@@ -983,6 +984,10 @@ static const bfd_target * const _bfd_target_vector[] =
&aarch64_elf64_le_vec,
&aarch64_elf64_le_cloudabi_vec,
&aarch64_mach_o_vec,
+
+ &arc_elf32_be_vec,
+ &arc_elf32_le_vec,
+ &arc_elf64_le_vec,
#endif
#ifdef BFD64
@@ -1001,9 +1006,6 @@ static const bfd_target * const _bfd_target_vector[] =
&aout_vec,
#endif
- &arc_elf32_be_vec,
- &arc_elf32_le_vec,
-
&arm_elf32_be_vec,
&arm_elf32_le_vec,
&arm_elf32_fdpic_be_vec,
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 6057515a89b..d6c0b13cba6 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -836,6 +836,8 @@ guess_is_rela (unsigned int e_machine)
case EM_ARC:
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
+ case EM_ARC_COMPACT3:
+ case EM_ARC_COMPACT3_64:
case EM_AVR:
case EM_AVR_OLD:
case EM_BLACKFIN:
@@ -1457,6 +1459,8 @@ dump_relocations (Filedata * filedata,
case EM_ARC:
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
+ case EM_ARC_COMPACT3:
+ case EM_ARC_COMPACT3_64:
rtype = elf_arc_reloc_type (type);
break;
@@ -2579,6 +2583,8 @@ get_machine_name (unsigned e_machine)
case EM_CYGNUS_FRV: return "Fujitsu FR-V";
case EM_S12Z: return "Freescale S12Z";
case EM_CSKY: return "C-SKY";
+ case EM_ARC_COMPACT3: return "ARCv3_32";
+ case EM_ARC_COMPACT3_64: return "ARCv3_64";
default:
snprintf (buff, sizeof (buff), _("<unknown>: 0x%x"), e_machine);
@@ -2623,6 +2629,10 @@ decode_ARC_machine_flags (unsigned e_flags, unsigned e_machine, char buf[])
strcat (buf, ", ARC700");
break;
+ case EF_ARC_CPU_ARC64:
+ strcat (buf, ", ARC 64");
+ break;
+
/* The only times we should end up here are (a) A corrupt ELF, (b) A
new ELF with new architecture being read by an old version of
readelf, or (c) An ELF built with non-GNU compiler that does not
@@ -3160,6 +3170,8 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
case EM_ARC_COMPACT2:
case EM_ARC_COMPACT:
+ case EM_ARC_COMPACT3:
+ case EM_ARC_COMPACT3_64:
decode_ARC_machine_flags (e_flags, e_machine, buf);
break;
@@ -4362,6 +4374,8 @@ get_section_type_name (Filedata * filedata, unsigned int sh_type)
case EM_ARC:
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
+ case EM_ARC_COMPACT3:
+ case EM_ARC_COMPACT3_64:
result = get_arc_section_type_name (sh_type);
break;
case EM_MIPS:
@@ -12752,6 +12766,8 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
return reloc_type == 1; /* R_ARC_32. */
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
+ case EM_ARC_COMPACT3:
+ case EM_ARC_COMPACT3_64:
return reloc_type == 4; /* R_ARC_32. */
case EM_ARM:
return reloc_type == 2; /* R_ARM_ABS32 */
@@ -12947,6 +12963,8 @@ is_32bit_pcrel_reloc (Filedata * filedata, unsigned int reloc_type)
return reloc_type == 10; /* R_ALPHA_SREL32. */
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
+ case EM_ARC_COMPACT3:
+ case EM_ARC_COMPACT3_64:
return reloc_type == 49; /* R_ARC_32_PCREL. */
case EM_ARM:
return reloc_type == 3; /* R_ARM_REL32 */
@@ -13011,6 +13029,8 @@ is_64bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
{
case EM_AARCH64:
return reloc_type == 257; /* R_AARCH64_ABS64. */
+ case EM_ARC_COMPACT3_64:
+ return reloc_type == 5; /* R_ARC_64. */
case EM_ALPHA:
return reloc_type == 2; /* R_ALPHA_REFQUAD. */
case EM_IA_64:
@@ -13112,6 +13132,8 @@ is_16bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
case EM_ARC:
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
+ case EM_ARC_COMPACT3:
+ case EM_ARC_COMPACT3_64:
return reloc_type == 2; /* R_ARC_16. */
case EM_ADAPTEVA_EPIPHANY:
return reloc_type == 5;
@@ -13364,6 +13386,8 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
case EM_ARC: /* R_ARC_NONE. */
case EM_ARC_COMPACT2: /* R_ARC_NONE. */
case EM_ARC_COMPACT: /* R_ARC_NONE. */
+ case EM_ARC_COMPACT3: /* R_ARC_NONE. */
+ case EM_ARC_COMPACT3_64: /* R_ARC_NONE. */
case EM_ARM: /* R_ARM_NONE. */
case EM_C166: /* R_XC16X_NONE. */
case EM_CRIS: /* R_CRIS_NONE. */
@@ -14983,27 +15007,31 @@ display_arc_attribute (unsigned char * p,
case Tag_ARC_PCS_config:
READ_ULEB (val, p, end);
printf (" Tag_ARC_PCS_config: ");
- switch (val)
+ switch (val & 0xff)
{
case 0:
- printf (_("Absent/Non standard\n"));
+ printf (_("Absent/Non standard"));
break;
case 1:
- printf (_("Bare metal/mwdt\n"));
+ printf (_("Bare metal/mwdt"));
break;
case 2:
- printf (_("Bare metal/newlib\n"));
+ printf (_("Bare metal/newlib"));
break;
case 3:
- printf (_("Linux/uclibc\n"));
+ printf (_("Linux/uclibc"));
break;
case 4:
- printf (_("Linux/glibc\n"));
+ printf (_("Linux/glibc"));
break;
default:
- printf (_("Unknown\n"));
+ printf (_("Unknown"));
break;
}
+ if (val & 0x100)
+ printf (_(" -linkrelax-\n"));
+ else
+ printf (_("\n"));
break;
case Tag_ARC_CPU_base:
@@ -20031,6 +20059,8 @@ process_arch_specific (Filedata * filedata)
case EM_ARC:
case EM_ARC_COMPACT:
case EM_ARC_COMPACT2:
+ case EM_ARC_COMPACT3:
+ case EM_ARC_COMPACT3_64:
return process_attributes (filedata, "ARC", SHT_ARC_ATTRIBUTES,
display_arc_attribute,
display_generic_attribute);
diff --git a/config.sub b/config.sub
index f02d43ad500..ba11553d56f 100755
--- a/config.sub
+++ b/config.sub
@@ -1163,7 +1163,7 @@ case $cpu-$vendor in
| alphapca5[67] | alpha64pca5[67] \
| am33_2.0 \
| amdgcn \
- | arc | arceb \
+ | arc | arceb | arc64 \
| arm | arm[lb]e | arme[lb] | armv* \
| avr | avr32 \
| asmjs \
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index f8d469cc2e1..7a2f5a4656d 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -48,6 +48,11 @@
#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
&& (SUB_OPCODE (x) == 0x28))
+
+#ifndef DEFAULT_ARCH
+#define DEFAULT_ARCH "arc"
+#endif /* DEFAULT_ARCH */
+
#ifndef TARGET_WITH_CPU
#define TARGET_WITH_CPU "arc700"
#endif /* TARGET_WITH_CPU */
@@ -121,6 +126,9 @@ enum arc_rlx_types
/* Generic assembler global variables which must be defined by all
targets. */
+/* Default architecture. */
+static const char default_arch[] = DEFAULT_ARCH;
+
/* Characters which always start a comment. */
const char comment_chars[] = "#;";
@@ -141,14 +149,18 @@ const char FLT_CHARS[] = "rRsSfFdD";
/* Byte order. */
extern int target_big_endian;
-const char *arc_target_format = DEFAULT_TARGET_FORMAT;
static int byte_order = DEFAULT_BYTE_ORDER;
/* Arc extension section. */
static segT arcext_section;
/* By default relaxation is disabled. */
-static int relaxation_state = 0;
+static bfd_boolean relaxation_state = FALSE;
+
+/* Status of the linker relaxation. It is a tristate variable: 0 is
+ non initialized/disabled, 1 is enabled, -1 forced disable (no PCS
+ attribute found). */
+static int do_linker_relax = 0;
extern int arc_get_mach (char *);
@@ -164,6 +176,7 @@ const pseudo_typeS md_pseudo_table[] =
{
/* Make sure that .word is 32 bits. */
{ "word", cons, 4 },
+ { "xword", cons, 8},
{ "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
{ "lcomm", arc_lcomm, 0 },
@@ -199,6 +212,7 @@ enum options
OPTION_CD,
OPTION_RELAX,
OPTION_NPS400,
+ OPTION_LINKER_RELAX,
OPTION_SPFP,
OPTION_DPFP,
@@ -243,6 +257,7 @@ struct option md_longopts[] =
{ "mcode-density", no_argument, NULL, OPTION_CD },
{ "mrelax", no_argument, NULL, OPTION_RELAX },
{ "mnps400", no_argument, NULL, OPTION_NPS400 },
+ { "mlinker-relax", no_argument, NULL, OPTION_LINKER_RELAX },
/* Floating point options */
{ "mspfp", no_argument, NULL, OPTION_SPFP},
@@ -439,25 +454,29 @@ static struct hash_control *arc_aux_hash;
/* The hash table of address types. */
static struct hash_control *arc_addrtype_hash;
-#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
+#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
+ { #NAME, "arc", ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
E_ARC_MACH_ARC600, EXTRA}
-#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
+#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
+ { #NAME, "arc", ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
E_ARC_MACH_ARC700, EXTRA}
-#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
+#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
+ { #NAME, "arc", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
EF_ARC_CPU_ARCV2EM, EXTRA}
-#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
- { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
+#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
+ { #NAME, "arc", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
EF_ARC_CPU_ARCV2HS, EXTRA}
-#define ARC_CPU_TYPE_NONE \
- { 0, 0, 0, 0, 0 }
+#define ARC_CPU_TYPE_A64x(NAME,EXTRA) \
+ { #NAME, "arc64", ARC_OPCODE_ARC64, bfd_mach_arcv3_64, \
+ EF_ARC_CPU_ARC64, EXTRA}
+#define ARC_CPU_TYPE_NONE \
+ { 0, 0, 0, 0, 0, 0 }
/* A table of CPU names and opcode sets. */
static const struct cpu_type
{
const char *name;
+ const char *arch;
unsigned flags;
int mach;
unsigned eflags;
@@ -469,7 +488,7 @@ static const struct cpu_type
};
/* Information about the cpu/variant we're assembling for. */
-static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
+static struct cpu_type selected_cpu = { 0, 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
/* TRUE if current assembly code uses RF16 only registers. */
static bfd_boolean rf16_only = TRUE;
@@ -501,7 +520,9 @@ static unsigned cl_features = 0;
#define O_tpoff O_md9 /* @tpoff relocation. */
#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
#define O_dtpoff O_md11 /* @dtpoff relocation. */
-#define O_last O_dtpoff
+#define O_u32 O_md12 /* @u32 modifier. */
+#define O_s32 O_md13 /* @u32 modifier. */
+#define O_last O_md13
/* Used to define a bracket as operand in tokens. */
#define O_bracket O_md32
@@ -554,6 +575,8 @@ static const struct arc_reloc_op_tag
DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
+ DEF (u32, BFD_RELOC_ARC_LO32_ME, 1),
+ DEF (s32, BFD_RELOC_ARC_32_ME, 1),
};
static const int arc_num_reloc_op
@@ -841,7 +864,7 @@ static void
arc_select_cpu (const char *arg, enum mach_selection_type sel)
{
int i;
- static struct cpu_type old_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
+ static struct cpu_type old_cpu = { 0, 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
/* We should only set a default if we've not made a selection from some
other source. */
@@ -893,7 +916,7 @@ arc_select_cpu (const char *arg, enum mach_selection_type sel)
if (mach_selection_mode != MACH_SELECTION_NONE
&& (old_cpu.mach != selected_cpu.mach))
{
- bfd_find_target (arc_target_format, stdoutput);
+ bfd_find_target (arc_target_format (), stdoutput);
if (! bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
as_warn (_("Could not set architecture and machine"));
}
@@ -1091,6 +1114,8 @@ debug_exp (expressionS *t)
case O_tpoff: namemd = "O_tpoff"; break;
case O_dtpoff9: namemd = "O_dtpoff9"; break;
case O_dtpoff: namemd = "O_dtpoff"; break;
+ case O_u32: namemd = "O_u32"; break;
+ case O_s32: namemd = "O_s32"; break;
}
pr_debug ("%s (%s, %s, %d, %s)", name,
@@ -1243,8 +1268,11 @@ tokenize_arguments (char *str,
++num_args;
break;
- case '{':
case '[':
+ /* Silence the error detection. */
+ saw_comma = TRUE;
+ /* fallthru */
+ case '{':
input_line_pointer++;
if (brk_lvl || num_args == ntok)
goto err;
@@ -1314,8 +1342,8 @@ tokenize_arguments (char *str,
debug_exp (tok);
if (tok->X_op == O_illegal
- || tok->X_op == O_absent
- || num_args == ntok)
+ || tok->X_op == O_absent
+ || num_args == ntok)
goto err;
saw_comma = FALSE;
@@ -1701,6 +1729,7 @@ parse_opcode_flags (const struct arc_opcode *opcode,
/* Found it. */
cl_matches++;
pflag->flgp = pf;
+ pflag->insert = cl_flags->insert;
lnflg--;
break;
}
@@ -1724,6 +1753,7 @@ parse_opcode_flags (const struct arc_opcode *opcode,
return FALSE;
cl_matches++;
pflag->flgp = flg_operand;
+ pflag->insert = cl_flags->insert;
lnflg--;
break; /* goto next flag class and parsed flag. */
}
@@ -1760,6 +1790,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
expressionS bktok[MAX_INSN_ARGS];
int bkntok;
expressionS emptyE;
+ unsigned int tmp = 0;
arc_opcode_hash_entry_iterator_init (&iter);
memset (&emptyE, 0, sizeof (emptyE));
@@ -1880,6 +1911,24 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
goto match_failed;
break;
+ case (ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED):
+ /* Signed extended 32 bit, only available for ARC64. */
+ if (tok[tokidx].X_op == O_constant)
+ {
+ offsetT val = tok[tokidx].X_add_number;
+ const offsetT min = -(1LL << 31);
+ const offsetT max = (1LL << 31) - 1;
+
+ if (val > max || val < min)
+ goto match_failed;
+ break;
+ }
+ /* By default a symbol is zero extended. */
+ else if (tok[tokidx].X_op == O_symbol
+ && tok[tokidx].X_md == O_absent)
+ goto match_failed;
+
+ /* FALLTHRU */
case ARC_OPERAND_LIMM:
case ARC_OPERAND_SIGNED:
case ARC_OPERAND_UNSIGNED:
@@ -1912,8 +1961,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
if (opcode->insn_class != AUXREG)
goto de_fault;
- p = S_GET_NAME (tok[tokidx].X_add_symbol);
+ p = S_GET_NAME (tok[tokidx].X_add_symbol);
/* For compatibility reasons, an aux register can
be spelled with upper or lower case
letters. */
@@ -2016,15 +2065,25 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
/* Relocs requiring long immediate. FIXME! make it
generic and move it to a function. */
+ tmp = ARC_OPERAND_SIGNED;
switch (tok[tokidx].X_md)
{
- case O_gotoff:
+ /* All offsets needs to be mapped into a signed
+ limm. */
case O_gotpc:
- case O_pcl:
case O_tpoff:
- case O_dtpoff:
- case O_tlsgd:
case O_tlsie:
+ case O_tlsgd:
+ case O_pcl:
+ case O_s32:
+ tmp = 0; /* Fail if is not signed. */
+ /* Fall through. */
+ case O_u32:
+ if ((operand->flags & ARC_OPERAND_SIGNED) == tmp)
+ goto match_failed;
+ /* Fall through. */
+ case O_gotoff: /* Not generated by ARC64. */
+ case O_dtpoff: /* Not generated by ARC64. */
if (!(operand->flags & ARC_OPERAND_LIMM))
goto match_failed;
/* Fall through. */
@@ -2196,6 +2255,26 @@ find_pseudo_insn (const char *opname,
return pseudo_insn;
}
}
+
+ /* ARC64 pseudo instructions. */
+ if (strcmp (default_arch, "arc64") != 0)
+ return NULL;
+
+ for (i = 0; i < arc64_num_pseudo_insn; i++)
+ {
+ pseudo_insn = &arc64_pseudo_insns[i];
+ if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
+ {
+ op = pseudo_insn->operand;
+ for (j = 0; j < ntok; ++j)
+ if (!pseudo_operand_match (&tok[j], &op[j]))
+ break;
+
+ /* Found the right instruction. */
+ if (j == ntok)
+ return pseudo_insn;
+ }
+ }
return NULL;
}
@@ -2558,6 +2637,25 @@ declare_register_set (void)
}
}
+/* Helper use for declaration of fp refisters. */
+static void
+declare_fp_set (void)
+{
+ int i;
+ for (i = 0; i < 32; ++i)
+ {
+ char name[32];
+
+ sprintf (name, "f%d", i);
+ declare_register (name, i);
+ if ((i & 0x01) == 0)
+ {
+ sprintf (name, "f%df%d", i, i+1);
+ declare_register (name, i);
+ }
+ }
+}
+
/* Construct a symbol for an address type. */
static void
@@ -2574,6 +2672,17 @@ declare_addrtype (const char *name, int number)
name, err);
}
+/* Initialize the default cpu. */
+
+static void
+init_default_arch (void)
+{
+ if (strcmp (default_arch, "arc64") == 0)
+ arc_select_cpu ("arc64", MACH_SELECTION_FROM_DEFAULT);
+ else
+ arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
+}
+
/* Port-specific assembler initialization. This function is called
once, at assembler startup time. */
@@ -2583,7 +2692,7 @@ md_begin (void)
const struct arc_opcode *opcode = arc_opcodes;
if (mach_selection_mode == MACH_SELECTION_NONE)
- arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
+ init_default_arch ();
/* The endianness can be chosen "at the factory". */
target_big_endian = byte_order == BIG_ENDIAN;
@@ -2618,12 +2727,22 @@ md_begin (void)
as_fatal (_("Virtual memory exhausted"));
declare_register_set ();
- declare_register ("gp", 26);
+ if (selected_cpu.mach == bfd_mach_arcv3_64)
+ {
+ declare_register ("gp", 30);
+ declare_fp_set ();
+ }
+ else
+ declare_register ("gp", 26);
declare_register ("fp", 27);
declare_register ("sp", 28);
declare_register ("ilink", 29);
- declare_register ("ilink1", 29);
- declare_register ("ilink2", 30);
+ if (selected_cpu.mach == bfd_mach_arc_arc600
+ || selected_cpu.mach == bfd_mach_arc_arc700)
+ {
+ declare_register ("ilink1", 29);
+ declare_register ("ilink2", 30);
+ }
declare_register ("blink", 31);
/* XY memory registers. */
@@ -2710,6 +2829,8 @@ md_begin (void)
declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
+
+ linkrelax = (do_linker_relax == 1) ? 1 : 0;
}
/* Write a value out to the object file, using the appropriate
@@ -2788,6 +2909,11 @@ md_pcrel_from_section (fixS *fixP,
case BFD_RELOC_ARC_S13_PCREL:
case BFD_RELOC_ARC_S21W_PCREL:
case BFD_RELOC_ARC_S25W_PCREL:
+ case BFD_RELOC_ARC_S10H_PCREL:
+ case BFD_RELOC_ARC_S13H_PCREL:
+ case BFD_RELOC_ARC_S9H_PCREL:
+ case BFD_RELOC_ARC_S8H_PCREL:
+ case BFD_RELOC_ARC_S7H_PCREL:
base &= ~3;
break;
default:
@@ -2886,6 +3012,29 @@ insert_operand (unsigned long long insn,
return insn;
}
+/* Called by TARGET_FORMAT. */
+
+const char *
+arc_target_format (void)
+{
+
+ /* We don't get a chance to initialize anything before we're called,
+ so handle that now. */
+ if (mach_selection_mode == MACH_SELECTION_NONE)
+ init_default_arch ();
+
+ if (selected_cpu.name == NULL)
+ return DEFAULT_TARGET_FORMAT;
+
+ if (selected_cpu.mach == bfd_mach_arcv3_64)
+ return "elf64-littlearc";
+
+ if (byte_order == LITTLE_ENDIAN)
+ return "elf32-littlearc";
+
+ return "elf32-bigarc";
+}
+
/* Apply a fixup to the object code. At this point all symbol values
should be fully resolved, and we attempt to completely resolve the
reloc. If we can not do that, we determine the correct reloc code
@@ -2903,7 +3052,6 @@ md_apply_fix (fixS *fixP,
symbolS *fx_addsy, *fx_subsy;
offsetT fx_offset;
segT add_symbol_segment = absolute_section;
- segT sub_symbol_segment = absolute_section;
const struct arc_operand *operand = NULL;
extended_bfd_reloc_code_real_type reloc;
@@ -2922,34 +3070,9 @@ md_apply_fix (fixS *fixP,
add_symbol_segment = S_GET_SEGMENT (fx_addsy);
}
- if (fx_subsy
- && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
- && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
- && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
- {
- resolve_symbol_value (fx_subsy);
- sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
-
- if (sub_symbol_segment == absolute_section)
- {
- /* The symbol is really a constant. */
- fx_offset -= S_GET_VALUE (fx_subsy);
- fx_subsy = NULL;
- }
- else
- {
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("can't resolve `%s' {%s section} - `%s' {%s section}"),
- fx_addsy ? S_GET_NAME (fx_addsy) : "0",
- segment_name (add_symbol_segment),
- S_GET_NAME (fx_subsy),
- segment_name (sub_symbol_segment));
- return;
- }
- }
-
if (fx_addsy
- && !S_IS_WEAK (fx_addsy))
+ && !S_IS_WEAK (fx_addsy)
+ && !fx_subsy)
{
if (add_symbol_segment == seg
&& fixP->fx_pcrel)
@@ -3119,6 +3242,11 @@ md_apply_fix (fixS *fixP,
case BFD_RELOC_ARC_S21H_PCREL:
case BFD_RELOC_ARC_S25H_PCREL:
case BFD_RELOC_ARC_S13_PCREL:
+ case BFD_RELOC_ARC_S10H_PCREL:
+ case BFD_RELOC_ARC_S13H_PCREL:
+ case BFD_RELOC_ARC_S9H_PCREL:
+ case BFD_RELOC_ARC_S8H_PCREL:
+ case BFD_RELOC_ARC_S7H_PCREL:
solve_plt:
operand = find_operand_for_reloc (reloc);
gas_assert (operand);
@@ -3454,12 +3582,10 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
}
case OPTION_EB:
- arc_target_format = "elf32-bigarc";
byte_order = BIG_ENDIAN;
break;
case OPTION_EL:
- arc_target_format = "elf32-littlearc";
byte_order = LITTLE_ENDIAN;
break;
@@ -3470,7 +3596,13 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
break;
case OPTION_RELAX:
- relaxation_state = 1;
+ relaxation_state = TRUE;
+ do_linker_relax = -1;
+ break;
+
+ case OPTION_LINKER_RELAX:
+ relaxation_state = FALSE;
+ do_linker_relax = (do_linker_relax == 0) ? 1 : do_linker_relax;
break;
case OPTION_NPS400:
@@ -3541,6 +3673,9 @@ arc_show_cpu_list (FILE *stream)
{
bfd_boolean last = (cpu_types[i + 1].name == NULL);
+ if (strcmp (default_arch, cpu_types[i].arch) != 0)
+ continue;
+
/* If displaying the new cpu name string, and the ', ' (for all
but the last one) will take us past a target width of 80
characters, then it's time for a new line. */
@@ -3555,8 +3690,8 @@ arc_show_cpu_list (FILE *stream)
}
}
-void
-md_show_usage (FILE *stream)
+static void
+md_show_usage32 (FILE *stream)
{
fprintf (stream, _("ARC-specific assembler options:\n"));
@@ -3617,6 +3752,26 @@ md_show_usage (FILE *stream)
" -mxy\n"));
}
+static void
+md_show_usage64 (FILE *stream)
+{
+ fprintf (stream, _("ARC64-specific assembler options:\n"));
+
+ fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>,"
+ "one of:\n");
+ arc_show_cpu_list (stream);
+ fprintf (stream, "\n");
+}
+
+void
+md_show_usage (FILE *stream)
+{
+ if (strcmp (default_arch, "arc64") == 0)
+ md_show_usage64 (stream);
+ else
+ md_show_usage32 (stream);
+}
+
/* Find the proper relocation for the given opcode. */
static extended_bfd_reloc_code_real_type
@@ -3986,6 +4141,9 @@ assemble_insn (const struct arc_opcode *opcode,
case O_gotoff:
case O_gotpc:
needGOTSymbol = TRUE;
+ /* Fall through. */
+ case O_u32:
+ case O_s32:
reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
break;
case O_pcl:
@@ -4141,8 +4299,22 @@ assemble_insn (const struct arc_opcode *opcode,
}
}
else
- image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
- << flg_operand->shift;
+ {
+ unsigned int flag_encoding;
+ flag_encoding = (flg_operand->code & ((1 << flg_operand->bits) - 1));
+
+ if (pflags[i].insert)
+ {
+ /* We can have a special flag which needs an insertion
+ function. */
+ const char *errmsg = NULL;
+ image = (*pflags[i].insert) (image, flag_encoding, &errmsg);
+ }
+ else
+ {
+ image |= flag_encoding << flg_operand->shift;
+ }
+ }
}
insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
@@ -4171,26 +4343,64 @@ assemble_insn (const struct arc_opcode *opcode,
arc_last_insns[0].opcode->name);
}
+static void
+arc_make_nops (char *buf, bfd_vma bytes)
+{
+ bfd_vma i = 0;
+
+ /* ARC instructions cannot begin or end on odd addresses, so this case
+ means we are not within a valid instruction sequence. It is thus safe
+ to use a zero byte, even though that is not a valid instruction. */
+ if (bytes % 2 == 1)
+ buf[i++] = 0;
+
+ /* Use 2-byte NOP. */
+ for ( ; i < bytes; i += 2)
+ md_number_to_chars_midend (buf + i, NOP_OPCODE_S, 2);
+}
+
+/* Implement HANDLE_ALIGN. */
+
void
arc_handle_align (fragS* fragP)
{
- if ((fragP)->fr_type == rs_align_code)
+ char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
+ valueT count = ((fragP)->fr_next->fr_address
+ - (fragP)->fr_address - (fragP)->fr_fix);
+ bfd_signed_vma size = count & ~0x01;
+ bfd_signed_vma excess = count & 0x01;
+ expressionS ex;
+
+ if (fragP->fr_type != rs_align_code)
+ return;
+
+ if (count <= 0)
+ return;
+
+ /* Insert zeros to get 2 byte alignment. */
+ if (excess && fragP->fr_type == rs_align_code)
{
- char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
- valueT count = ((fragP)->fr_next->fr_address
- - (fragP)->fr_address - (fragP)->fr_fix);
+ arc_make_nops (dest, excess);
+ fragP->fr_fix += excess;
+ dest += excess;
+ }
- (fragP)->fr_var = 2;
+ /* Only emit this reloc when linker relaxation is required. */
+ if (linkrelax && size)
+ {
+ ex.X_op = O_constant;
+ ex.X_add_number = size;
+ fix_new_exp (fragP, fragP->fr_fix, 0, &ex, FALSE, BFD_RELOC_ARC_ALIGN);
+ }
+ else
+ {
+ if (size > MAX_MEM_FOR_RS_ALIGN_CODE)
+ size &= MAX_MEM_FOR_RS_ALIGN_CODE;
- if (count & 1)/* Padding in the gap till the next 2-byte
- boundary with 0s. */
- {
- (fragP)->fr_fix++;
- *dest++ = 0;
- }
- /* Writing nop_s. */
- md_number_to_chars (dest, NOP_OPCODE_S, 2);
+ /* Insert variable number of 2 bytes NOPs. */
+ arc_make_nops (dest, size);
}
+ fragP->fr_fix += size;
}
/* Here we decide which fixups can be adjusted to make them relative
@@ -4202,7 +4412,6 @@ arc_handle_align (fragS* fragP)
int
tc_arc_fix_adjustable (fixS *fixP)
{
-
/* Prevent all adjustments to global symbols. */
if (S_IS_EXTERNAL (fixP->fx_addsy))
return 0;
@@ -4224,7 +4433,7 @@ tc_arc_fix_adjustable (fixS *fixP)
break;
}
- return 1;
+ return !linkrelax;
}
/* Compute the reloc type of an expression EXP. */
@@ -4255,23 +4464,88 @@ arc_cons_fix_new (fragS *frag,
switch (size)
{
case 1:
- r_type = BFD_RELOC_8;
+ if (exp->X_op == O_subtract && exp->X_op_symbol != NULL && linkrelax)
+ {
+ if (S_IS_LOCAL (exp->X_add_symbol) && S_IS_LOCAL (exp->X_op_symbol))
+ {
+ expressionS exps;
+ memcpy (&exps, exp, sizeof (expressionS));
+ exps.X_op = O_symbol;
+ exps.X_add_symbol = exp->X_op_symbol;
+ exps.X_op_symbol = NULL;
+ exp->X_op_symbol = NULL;
+ exp->X_op = O_symbol;
+ fix_new_exp (frag, off, size, exp, 0, BFD_RELOC_ARC_ADD8);
+ fix_new_exp (frag, off, size, &exps, 0, BFD_RELOC_ARC_SUB8);
+ return;
+ }
+ else
+ as_bad_where (frag->fr_file, frag->fr_line,
+ _("Unknown substract operation. "
+ "Cannot generate reloc"));
+ }
+ else
+ r_type = BFD_RELOC_8;
break;
case 2:
- r_type = BFD_RELOC_16;
+ if (exp->X_op == O_subtract && exp->X_op_symbol != NULL && linkrelax)
+ {
+ if (S_IS_LOCAL (exp->X_add_symbol) && S_IS_LOCAL (exp->X_op_symbol))
+ {
+ expressionS exps;
+ memcpy (&exps, exp, sizeof (expressionS));
+ exps.X_op = O_symbol;
+ exps.X_add_symbol = exp->X_op_symbol;
+ exps.X_op_symbol = NULL;
+ exp->X_op_symbol = NULL;
+ exp->X_op = O_symbol;
+ fix_new_exp (frag, off, size, exp, 0, BFD_RELOC_ARC_ADD16);
+ fix_new_exp (frag, off, size, &exps, 0, BFD_RELOC_ARC_SUB16);
+ return;
+ }
+ else
+ as_bad_where (frag->fr_file, frag->fr_line,
+ _("Unknown substract operation. "
+ "Cannot generate reloc"));
+ }
+ else
+ r_type = BFD_RELOC_16;
break;
case 3:
+ gas_assert (!linkrelax);
r_type = BFD_RELOC_24;
break;
case 4:
- r_type = BFD_RELOC_32;
+ if (exp->X_op == O_subtract && exp->X_op_symbol != NULL && linkrelax)
+ {
+ if (S_IS_LOCAL (exp->X_add_symbol) && S_IS_LOCAL (exp->X_op_symbol))
+ {
+ expressionS exps;
+ memcpy (&exps, exp, sizeof (expressionS));
+ exps.X_op = O_symbol;
+ exps.X_add_symbol = exp->X_op_symbol;
+ exps.X_op_symbol = NULL;
+ exp->X_op_symbol = NULL;
+ exp->X_op = O_symbol;
+ fix_new_exp (frag, off, size, exp, 0, BFD_RELOC_32);
+ fix_new_exp (frag, off, size, &exps, 0, BFD_RELOC_ARC_SUB32);
+ return;
+ }
+ else
+ as_bad_where (frag->fr_file, frag->fr_line,
+ _("Unknown substract operation. "
+ "Cannot generate reloc"));
+ }
+ else
+ r_type = BFD_RELOC_32;
arc_check_reloc (exp, &r_type);
break;
case 8:
+ gas_assert (!linkrelax);
r_type = BFD_RELOC_64;
break;
@@ -4291,6 +4565,7 @@ check_zol (symbolS *s)
switch (selected_cpu.mach)
{
case bfd_mach_arc_arcv2:
+ case bfd_mach_arcv3_64:
if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
return;
@@ -5066,6 +5341,17 @@ arc_set_public_attributes (void)
"register file"));
bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_ABI_rf16, 0);
}
+
+ /* Tag_ARC_PCS_config. */
+ if (attributes_set_explicitly[Tag_ARC_PCS_config])
+ {
+ int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
+ Tag_ARC_PCS_config);
+ val |= (do_linker_relax == 1) ? 0x100 : 0x00;
+ bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_PCS_config, val);
+ }
+ else if (do_linker_relax == 1)
+ arc_set_attribute_int (Tag_ARC_PCS_config, 0x100);
}
/* Add the default contents for the .ARC.attributes section. */
@@ -5075,9 +5361,6 @@ arc_md_end (void)
{
arc_set_public_attributes ();
- if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
- as_fatal (_("could not set architecture and machine"));
-
bfd_set_private_flags (stdoutput, selected_cpu.eflags);
}
@@ -5126,6 +5409,26 @@ int arc_convert_symbolic_attribute (const char *name)
return -1;
}
+/* Implements md_allow_local_substract. */
+
+bfd_boolean arc_allow_local_subtract (expressionS * left,
+ expressionS * right,
+ segT section)
+{
+ /* if we don't relax allow substraction. */
+ if (!linkrelax)
+ return TRUE;
+
+ /* if the symbols are not in a code section then they are OK. */
+ if ((section->flags & SEC_CODE) == 0)
+ return TRUE;
+
+ if (left->X_add_symbol == right->X_add_symbol)
+ return TRUE;
+
+ return FALSE;
+}
+
/* Local variables:
eval: (c-set-style "gnu")
indent-tabs-mode: t
diff --git a/gas/config/tc-arc.h b/gas/config/tc-arc.h
index 2aa61e0ef8b..6b1a85563af 100644
--- a/gas/config/tc-arc.h
+++ b/gas/config/tc-arc.h
@@ -48,28 +48,25 @@
#undef BIG_ENDIAN
#define BIG_ENDIAN 4321
-#ifdef TARGET_BYTES_BIG_ENDIAN
+#ifndef TARGET_BYTES_BIG_ENDIAN
+/* You should define this macro to be non-zero if the target is big
+ endian, and zero if the target is little endian. */
+#define TARGET_BYTES_BIG_ENDIAN 0
+#endif
+#if TARGET_BYTES_BIG_ENDIAN == 1
# define DEFAULT_TARGET_FORMAT "elf32-bigarc"
# define DEFAULT_BYTE_ORDER BIG_ENDIAN
-
#else
-/* You should define this macro to be non-zero if the target is big
- endian, and zero if the target is little endian. */
-# define TARGET_BYTES_BIG_ENDIAN 0
-
# define DEFAULT_TARGET_FORMAT "elf32-littlearc"
# define DEFAULT_BYTE_ORDER LITTLE_ENDIAN
#endif /* TARGET_BYTES_BIG_ENDIAN. */
-/* The endianness of the target format may change based on command
- line arguments. */
-extern const char *arc_target_format;
-
/* This macro is the BFD target name to use when creating the output
file. This will normally depend upon the `OBJ_FMT' macro. */
-#define TARGET_FORMAT arc_target_format
+#define TARGET_FORMAT arc_target_format()
+extern const char *arc_target_format (void);
/* `md_short_jump_size'
`md_long_jump_size'
@@ -103,9 +100,6 @@ extern const char *arc_target_format;
fixp->fx_frag->fr_address. */
#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
-/* [ ] is index operator. */
-#define NEED_INDEX_OPERATOR
-
#define MAX_MEM_FOR_RS_ALIGN_CODE (1+2)
/* HANDLE_ALIGN called after all the assembly has been done,
@@ -125,6 +119,10 @@ extern const char *arc_target_format;
#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \
arc_cons_fix_new ((FRAG), (OFF), (LEN), (EXP), (RELOC))
+/* We don't want to do any fixup when linker is relaxing. */
+#define TC_LINKRELAX_FIXUP(SEG) 1
+#define LINKER_RELAXING_SHRINKS_ONLY 1
+
/* We don't want gas to fixup the following program memory related
relocations. Check also that fx_addsy is not NULL, in order to
make sure that the fixup refers to some sort of label. */
@@ -134,26 +132,21 @@ extern const char *arc_target_format;
|| FIXP->fx_r_type == BFD_RELOC_ARC_S25W_PCREL_PLT \
|| FIXP->fx_r_type == BFD_RELOC_ARC_S25H_PCREL_PLT \
|| FIXP->fx_r_type == BFD_RELOC_ARC_S21W_PCREL_PLT \
- || FIXP->fx_r_type == BFD_RELOC_ARC_S21H_PCREL_PLT) \
- && FIXP->fx_addsy != NULL \
- && FIXP->fx_subsy == NULL) \
+ || FIXP->fx_r_type == BFD_RELOC_ARC_S21H_PCREL_PLT \
+ || (linkrelax \
+ && (FIXP->fx_r_type == BFD_RELOC_ARC_S7H_PCREL \
+ || FIXP->fx_r_type == BFD_RELOC_ARC_S8H_PCREL))) \
+ && (FIXP->fx_addsy != NULL) \
+ && (FIXP->fx_subsy == NULL)) \
{ \
symbol_mark_used_in_reloc (FIXP->fx_addsy); \
goto SKIP; \
}
-/* BFD_RELOC_ARC_TLS_GD_LD may use fx_subsy to store a label that is
- later turned into fx_offset. */
-#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \
- ((FIX)->fx_r_type == BFD_RELOC_ARC_TLS_GD_LD)
-
-#define TC_VALIDATE_FIX_SUB(FIX, SEG) \
- ((md_register_arithmetic || (SEG) != reg_section) \
- && ((FIX)->fx_r_type == BFD_RELOC_GPREL32 \
- || (FIX)->fx_r_type == BFD_RELOC_GPREL16 \
- || (FIX)->fx_r_type == BFD_RELOC_ARC_TLS_DTPOFF \
- || (FIX)->fx_r_type == BFD_RELOC_ARC_TLS_DTPOFF_S9 \
- || TC_FORCE_RELOCATION_SUB_LOCAL (FIX, SEG)))
+/* The difference between same-section symbols may be affected by linker
+ relaxation, so do not resolve such expressions in the assembler. */
+#define md_allow_local_subtract(l,r,s) arc_allow_local_subtract(l, r, s)
+extern bfd_boolean arc_allow_local_subtract (expressionS *, expressionS *, segT);
/* We use this to mark the end-loop label. We use this mark for ZOL
validity checks. */
@@ -236,6 +229,11 @@ struct arc_flags
/* Pointer to arc flags. */
const struct arc_flag_operand *flgp;
+
+ /* Pointer to insert function. */
+ unsigned long long (*insert) (unsigned long long instruction,
+ long long int op,
+ const char **errmsg);
};
extern const relax_typeS md_relax_table[];
diff --git a/gas/configure b/gas/configure
index e59b58ef4ba..a9033957c99 100755
--- a/gas/configure
+++ b/gas/configure
@@ -13009,7 +13009,7 @@ $as_echo "#define NDS32_DEFAULT_ZOL_EXT 1" >>confdefs.h
$as_echo "$enable_zol_ext" >&6; }
;;
- aarch64 | i386 | s390 | sparc)
+ aarch64 | i386 | s390 | sparc | arc)
if test $this_target = $target ; then
cat >>confdefs.h <<_ACEOF
diff --git a/gas/configure.ac b/gas/configure.ac
index ae5d7003d35..183859183e1 100644
--- a/gas/configure.ac
+++ b/gas/configure.ac
@@ -569,7 +569,7 @@ changequote([,])dnl
AC_MSG_RESULT($enable_zol_ext)
;;
- aarch64 | i386 | s390 | sparc)
+ aarch64 | i386 | s390 | sparc | arc)
if test $this_target = $target ; then
AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
fi
diff --git a/gas/configure.tgt b/gas/configure.tgt
index 337249597c5..49f3bf0d4c9 100644
--- a/gas/configure.tgt
+++ b/gas/configure.tgt
@@ -50,7 +50,8 @@ case ${cpu} in
aarch64_be) cpu_type=aarch64 endian=big arch=aarch64;;
alpha*) cpu_type=alpha ;;
am33_2.0) cpu_type=mn10300 endian=little ;;
- arc*eb) cpu_type=arc endian=big ;;
+ arceb) cpu_type=arc endian=big ;;
+ arc64*) cpu_type=arc arch=arc64 endian=little ;;
arm*be|arm*b) cpu_type=arm endian=big ;;
arm*) cpu_type=arm endian=little ;;
bfin*) cpu_type=bfin endian=little ;;
@@ -135,6 +136,7 @@ case ${generic_target} in
alpha-*-netbsd* | alpha-*-openbsd*) fmt=elf em=nbsd ;;
arc-*-elf*) fmt=elf ;;
+ arc64-*-*) fmt=elf ;;
arc*-*-linux*) fmt=elf bfd_gas=yes ;;
arm-*-phoenix*) fmt=elf ;;
diff --git a/gas/testsuite/gas/arc/arc.exp b/gas/testsuite/gas/arc/arc.exp
index 74f3166c545..5e7ac2242ae 100644
--- a/gas/testsuite/gas/arc/arc.exp
+++ b/gas/testsuite/gas/arc/arc.exp
@@ -14,6 +14,10 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+if { [istarget arc64-*-*] } {
+ return
+}
+
# ARC base instruction set
# ARC library extensions
diff --git a/gas/testsuite/gas/arc64/arc64.exp b/gas/testsuite/gas/arc64/arc64.exp
new file mode 100644
index 00000000000..5aa98e87c81
--- /dev/null
+++ b/gas/testsuite/gas/arc64/arc64.exp
@@ -0,0 +1,24 @@
+# Copyright (C) 2021 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+if { ![istarget arc64-*-*] } {
+ return
+}
+
+# ARC base instruction set
+
+# ARC library extensions
+run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
diff --git a/gas/testsuite/gas/arc64/lddl.d b/gas/testsuite/gas/arc64/lddl.d
new file mode 100644
index 00000000000..f4f68def20e
--- /dev/null
+++ b/gas/testsuite/gas/arc64/lddl.d
@@ -0,0 +1,46 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format elf64-.*arc
+
+Disassembly of section .text:
+0x[0-9a-f]+ 21f2 0080 lddl r0r1,\[r1,r2\]
+0x[0-9a-f]+ 22f2 0f06 0000 0100 lddl r6r7,\[r2,256@s32\]
+0x[0-9a-f]+ 22f2 0f02 ffff feff lddl r2r3,\[r2,-257@s32\]
+0x[0-9a-f]+ 26f2 7144 8000 0000 lddl r4r5,\[0x80000000,r5\]
+0x[0-9a-f]+ 24f2 7144 ffff ff9c lddl r4r5,\[-100@s32,r5\]
+0x[0-9a-f]+ 1000 0682 lddl r2r3,\[r0\]
+0x[0-9a-f]+ 17ff 0686 lddl r6r7,\[r7,255\]
+0x[0-9a-f]+ 1700 8686 lddl r6r7,\[r7,-256\]
+0x[0-9a-f]+ 1400 7680 1337 1338 lddl r0r1,\[322376504@s32\]
+0x[0-9a-f]+ 1600 7682 8000 0000 lddl r2r3,\[0x80000000\]
+0x[0-9a-f]+ 1400 7682 8000 0000 lddl r2r3,\[-2147483648@s32\]
+0x[0-9a-f]+ 21f3 0080 lddl.aw r0r1,\[r1,r2\]
+0x[0-9a-f]+ 22f3 0f06 0000 0100 lddl.aw r6r7,\[r2,256@s32\]
+0x[0-9a-f]+ 22f3 0f02 ffff feff lddl.aw r2r3,\[r2,-257@s32\]
+0x[0-9a-f]+ 1000 06c2 lddl.aw r2r3,\[r0\]
+0x[0-9a-f]+ 17ff 06c6 lddl.aw r6r7,\[r7,255\]
+0x[0-9a-f]+ 1700 86c6 lddl.aw r6r7,\[r7,-256\]
+0x[0-9a-f]+ 21f3 0080 lddl.aw r0r1,\[r1,r2\]
+0x[0-9a-f]+ 22f3 0f06 0000 0100 lddl.aw r6r7,\[r2,256@s32\]
+0x[0-9a-f]+ 22f3 0f02 ffff feff lddl.aw r2r3,\[r2,-257@s32\]
+0x[0-9a-f]+ 1000 06c2 lddl.aw r2r3,\[r0\]
+0x[0-9a-f]+ 17ff 06c6 lddl.aw r6r7,\[r7,255\]
+0x[0-9a-f]+ 1700 86c6 lddl.aw r6r7,\[r7,-256\]
+0x[0-9a-f]+ 21f3 8080 lddl.ab r0r1,\[r1,r2\]
+0x[0-9a-f]+ 22f3 8f06 0000 0100 lddl.ab r6r7,\[r2,256@s32\]
+0x[0-9a-f]+ 22f3 8f02 ffff feff lddl.ab r2r3,\[r2,-257@s32\]
+0x[0-9a-f]+ 1000 0ec2 lddl.ab r2r3,\[r0\]
+0x[0-9a-f]+ 17ff 0ec6 lddl.ab r6r7,\[r7,255\]
+0x[0-9a-f]+ 1700 8ec6 lddl.ab r6r7,\[r7,-256\]
+0x[0-9a-f]+ 21f2 8080 lddl.as r0r1,\[r1,r2\]
+0x[0-9a-f]+ 22f2 8f06 0000 0100 lddl.as r6r7,\[r2,256@s32\]
+0x[0-9a-f]+ 22f2 8f02 ffff feff lddl.as r2r3,\[r2,-257@s32\]
+0x[0-9a-f]+ 26f2 f144 8000 0000 lddl.as r4r5,\[0x80000000,r5\]
+0x[0-9a-f]+ 24f2 f144 ffff ff9c lddl.as r4r5,\[-100@s32,r5\]
+0x[0-9a-f]+ 1000 0e82 lddl.as r2r3,\[r0\]
+0x[0-9a-f]+ 17ff 0e86 lddl.as r6r7,\[r7,255\]
+0x[0-9a-f]+ 1700 8e86 lddl.as r6r7,\[r7,-256\]
+0x[0-9a-f]+ 24f2 f144 ffff ff00 lddl.as r4r5,\[-256@s32,r5\]
+0x[0-9a-f]+ 1400 7e80 1337 1338 lddl.as r0r1,\[322376504@s32]
+0x[0-9a-f]+ 1600 7e82 8000 0000 lddl.as r2r3,\[0x80000000]
+0x[0-9a-f]+ 1400 7e82 8000 0000 lddl.as r2r3,\[-2147483648@s32]
diff --git a/gas/testsuite/gas/arc64/lddl.s b/gas/testsuite/gas/arc64/lddl.s
new file mode 100644
index 00000000000..b7412d57ca1
--- /dev/null
+++ b/gas/testsuite/gas/arc64/lddl.s
@@ -0,0 +1,54 @@
+# 128-bit loads
+
+ lddl r0, [r1,r2] ; lddl a, [b, c]
+ lddl r6, [r2,256] ; lddl a, [b, limm] (limm > s9)
+ lddl r2, [r2,-257] ; lddl a, [b, ximm]
+ lddl r4, [0x80000000,r5] ; lddl a, [limm, c]
+ lddl r4, [-100,r5] ; lddl a, [ximm, c]
+
+ lddl r2, [r0] ; lddl a, [b, s9=0]
+ lddl r6, [r7,255] ; lddl a, [b, s9] biggest s9
+ lddl r6, [r7,-256] ; lddl a, [b, s9] smallest s9
+ lddl r0, [0x13371338] ; lddl a, [limm,s9=0]
+ lddl r2, [0x80000000] ; lddl a, [limm,s9=0]
+ lddl r2, [-2147483648] ; lddl a, [ximm,s9=0]
+
+ ; Now, repetition of instructions above with suffices (*.a/aw/ab/as)
+
+ lddl.a r0, [r1,r2]
+ lddl.a r6, [r2,256]
+ lddl.a r2, [r2,-257]
+
+ lddl.a r2, [r0]
+ lddl.a r6, [r7,255]
+ lddl.a r6, [r7,-256]
+
+ lddl.aw r0, [r1,r2]
+ lddl.aw r6, [r2,256]
+ lddl.aw r2, [r2,-257]
+
+ lddl.aw r2, [r0]
+ lddl.aw r6, [r7,255]
+ lddl.aw r6, [r7,-256]
+
+ lddl.ab r0, [r1,r2]
+ lddl.ab r6, [r2,256]
+ lddl.ab r2, [r2,-257]
+
+ lddl.ab r2, [r0]
+ lddl.ab r6, [r7,255]
+ lddl.ab r6, [r7,-256]
+
+ lddl.as r0, [r1,r2]
+ lddl.as r6, [r2,256]
+ lddl.as r2, [r2,-257]
+ lddl.as r4, [0x80000000,r5]
+ lddl.as r4, [-100,r5]
+
+ lddl.as r2, [r0]
+ lddl.as r6, [r7,255]
+ lddl.as r6, [r7,-256]
+ lddl.as r4, [-256,r5]
+ lddl.as r0, [0x13371338]
+ lddl.as r2, [0x80000000]
+ lddl.as r2, [-2147483648]
diff --git a/gas/testsuite/gas/arc64/stdl.d b/gas/testsuite/gas/arc64/stdl.d
new file mode 100644
index 00000000000..90c39984c38
--- /dev/null
+++ b/gas/testsuite/gas/arc64/stdl.d
@@ -0,0 +1,32 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format elf64-.*arc
+
+Disassembly of section .text:
+0x[0-9a-f]+ 1900 0127 stdl r4r5,\[r1\]
+0x[0-9a-f]+ 19ff 0027 stdl r0r1,\[r1,255\]
+0x[0-9a-f]+ 1c00 80a7 stdl r2r3,\[r4,-256\]
+0x[0-9a-f]+ 1c00 7127 0000 1338 stdl r4r5,\[4920@s32\]
+0x[0-9a-f]+ 1e00 71a7 8000 0000 stdl r6r7,\[0x80000000\]
+0x[0-9a-f]+ 1c00 7227 ffff fc00 stdl r8r9,\[-1024@s32\]
+0x[0-9a-f]+ 1a00 8f27 1234 5678 stdl 305419896@s32,\[r2,-256\]
+0x[0-9a-f]+ 19ff 0f27 ffff 5bf0 stdl -42000@s32,\[r1,255\]
+0x[0-9a-f]+ 19ff 002f stdl.aw r0r1,\[r1,255\]
+0x[0-9a-f]+ 1c00 80af stdl.aw r2r3,\[r4,-256\]
+0x[0-9a-f]+ 1a00 8f2f 1234 5678 stdl.aw 305419896@s32,\[r2,-256\]
+0x[0-9a-f]+ 19ff 0f2f ffff 5bf0 stdl.aw -42000@s32,\[r1,255\]
+0x[0-9a-f]+ 19ff 002f stdl.aw r0r1,\[r1,255\]
+0x[0-9a-f]+ 1c00 80af stdl.aw r2r3,\[r4,-256\]
+0x[0-9a-f]+ 1a00 8f2f 1234 5678 stdl.aw 305419896@s32,\[r2,-256\]
+0x[0-9a-f]+ 19ff 0f2f ffff 5bf0 stdl.aw -42000@s32,\[r1,255\]
+0x[0-9a-f]+ 19ff 0037 stdl.ab r0r1,\[r1,255\]
+0x[0-9a-f]+ 1c00 80b7 stdl.ab r2r3,\[r4,-256\]
+0x[0-9a-f]+ 1a00 8f37 1234 5678 stdl.ab 305419896@s32,\[r2,-256\]
+0x[0-9a-f]+ 19ff 0f37 ffff 5bf0 stdl.ab -42000@s32,\[r1,255\]
+0x[0-9a-f]+ 19ff 003f stdl.as r0r1,\[r1,255\]
+0x[0-9a-f]+ 1c00 80bf stdl.as r2r3,\[r4,-256\]
+0x[0-9a-f]+ 1c00 713f 0000 1338 stdl.as r4r5,\[4920@s32\]
+0x[0-9a-f]+ 1e00 71bf 8000 0000 stdl.as r6r7,\[0x80000000\]
+0x[0-9a-f]+ 1c00 723f ffff fc00 stdl.as r8r9,\[-1024@s32\]
+0x[0-9a-f]+ 1a00 8f3f 1234 5678 stdl.as 305419896@s32,\[r2,-256\]
+0x[0-9a-f]+ 19ff 0f3f ffff 5bf0 stdl.as -42000@s32,\[r1,255\]
diff --git a/gas/testsuite/gas/arc64/stdl.s b/gas/testsuite/gas/arc64/stdl.s
new file mode 100644
index 00000000000..704b49857ac
--- /dev/null
+++ b/gas/testsuite/gas/arc64/stdl.s
@@ -0,0 +1,35 @@
+# 128-bit stores
+
+ stdl r4, [r1] ; stdl c, [b, s9=0]
+ stdl r0, [r1,255] ; stdl c, [b, s9] s9: biggest
+ stdl r2, [r4,-256] ; stdl c, [b, s9] s9: smallest
+ stdl r4, [0x1338] ; stdl c, [limm] limm: small positive
+ stdl r6, [0x80000000] ; stdl c, [limm] limm: positive
+ stdl r8, [-1024] ; stdl c, [ximm] ximm: negative
+ stdl 0x12345678, [r2, -256] ; stdl limm, [b, s9] limm: positive
+ stdl -42000, [r1, 255] ; stdl ximm, [b, s9] ximm: negative
+
+ ; Now, repetition of instructions above with suffices (*.a/aw/ab/as)
+
+ stdl.a r0, [r1,255]
+ stdl.a r2, [r4,-256]
+ stdl.a 0x12345678, [r2, -256]
+ stdl.a -42000, [r1, 255]
+
+ stdl.aw r0, [r1,255]
+ stdl.aw r2, [r4,-256]
+ stdl.aw 0x12345678, [r2, -256]
+ stdl.aw -42000, [r1, 255]
+
+ stdl.ab r0, [r1,255]
+ stdl.ab r2, [r4,-256]
+ stdl.ab 0x12345678, [r2, -256]
+ stdl.ab -42000, [r1, 255]
+
+ stdl.as r0, [r1,255]
+ stdl.as r2, [r4,-256]
+ stdl.as r4, [0x1338]
+ stdl.as r6, [0x80000000]
+ stdl.as r8, [-1024]
+ stdl.as 0x12345678, [r2, -256]
+ stdl.as -42000, [r1, 255]
diff --git a/gas/write.c b/gas/write.c
index 054f27987d5..171c5424ffb 100644
--- a/gas/write.c
+++ b/gas/write.c
@@ -2611,7 +2611,8 @@ relax_frag (segT segment, fragS *fragP, long stretch)
lowest order bits all 0s, return size of adjustment made. */
static relax_addressT
relax_align (relax_addressT address, /* Address now. */
- int alignment /* Alignment (binary). */)
+ int alignment, /* Alignment (binary). */
+ enum _relax_state fr_type)
{
relax_addressT mask;
relax_addressT new_address;
@@ -2619,7 +2620,7 @@ relax_align (relax_addressT address, /* Address now. */
mask = ~((relax_addressT) ~0 << alignment);
new_address = (address + mask) & (~mask);
#ifdef LINKER_RELAXING_SHRINKS_ONLY
- if (linkrelax)
+ if (linkrelax && fr_type == rs_align_code)
/* We must provide lots of padding, so the linker can discard it
when needed. The linker will not add extra space, ever. */
new_address += (1 << alignment);
@@ -2672,7 +2673,8 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
case rs_align_code:
case rs_align_test:
{
- addressT offset = relax_align (address, (int) fragP->fr_offset);
+ addressT offset = relax_align (address, (int) fragP->fr_offset,
+ fragP->fr_type);
if (fragP->fr_subtype != 0 && offset > fragP->fr_subtype)
offset = 0;
@@ -2889,9 +2891,9 @@ relax_segment (struct frag *segment_frag_root, segT segment, int pass)
addressT oldoff, newoff;
oldoff = relax_align (was_address + fragP->fr_fix,
- (int) offset);
+ (int) offset, fragP->fr_type);
newoff = relax_align (address + fragP->fr_fix,
- (int) offset);
+ (int) offset, fragP->fr_type);
if (fragP->fr_subtype != 0)
{
diff --git a/include/elf/arc-cpu.def b/include/elf/arc-cpu.def
index 48bbd9a3430..585b653a0fc 100644
--- a/include/elf/arc-cpu.def
+++ b/include/elf/arc-cpu.def
@@ -19,6 +19,8 @@
02110-1301, USA. */
+ARC_CPU_TYPE_A64x (arc64, CD | DIV),
+
ARC_CPU_TYPE_A7xx (arc700, 0x00),
ARC_CPU_TYPE_A7xx (nps400, NPS400),
diff --git a/include/elf/arc-reloc.def b/include/elf/arc-reloc.def
index 72776f94c38..c379cd4dea6 100644
--- a/include/elf/arc-reloc.def
+++ b/include/elf/arc-reloc.def
@@ -64,6 +64,13 @@ ARC_RELOC_HOWTO(ARC_32, 4, \
bitfield, \
( S + A ))
+ARC_RELOC_HOWTO(ARC_64, 5, \
+ 2, \
+ 64, \
+ replace_word64, \
+ bitfield, \
+ ( S + A ))
+
ARC_RELOC_HOWTO(ARC_N8, 8, \
0, \
8, \
@@ -90,7 +97,7 @@ ARC_RELOC_HOWTO(ARC_N32, 11, \
32, \
replace_word32, \
bitfield, \
- ( A - S ))
+ ( A - S))
ARC_RELOC_HOWTO(ARC_SDA, 12, \
2, \
@@ -201,14 +208,14 @@ ARC_RELOC_HOWTO(ARC_32_ME, 27, \
2, \
32, \
replace_limm, \
- signed, \
+ bitfield, \
( ME ( ( S + A ) ) ))
ARC_RELOC_HOWTO(ARC_32_ME_S, 105, \
2, \
32, \
replace_limms, \
- signed, \
+ bitfield, \
( ME ( ( S + A ) ) ))
ARC_RELOC_HOWTO(ARC_N32_ME, 28, \
@@ -511,3 +518,137 @@ ARC_RELOC_HOWTO(ARC_NPS_CMEM16, 78, \
replace_bits16, \
dont, \
( ME ( S + A )))
+
+ARC_RELOC_HOWTO(ARC_S9H_PCREL, 79, \
+ 2, \
+ 8, \
+ replace_disp8ls, \
+ signed, \
+ ( ME ( ( ( ( S + A ) - P ) >> 1 ) ) ) )
+
+ARC_RELOC_HOWTO(ARC_S7H_PCREL, 80, \
+ 1, \
+ 6, \
+ replace_disp6s, \
+ signed, \
+ ( ( ( ( S + A ) - P ) >> 1 ) ) )
+
+ARC_RELOC_HOWTO(ARC_S8H_PCREL, 81, \
+ 1, \
+ 7, \
+ replace_disp7s, \
+ signed, \
+ ( ( ( ( S + A ) - P ) >> 1 ) ) )
+
+ARC_RELOC_HOWTO(ARC_S10H_PCREL, 82, \
+ 1, \
+ 9, \
+ replace_disp9s, \
+ signed, \
+ ( ( ( ( S + A ) - P ) >> 1 ) ) )
+
+ARC_RELOC_HOWTO(ARC_S13H_PCREL, 83, \
+ 2, \
+ 12, \
+ replace_disp12s, \
+ signed, \
+ ( ME ( ( ( ( S + A ) - P ) >> 1 ) ) ) )
+
+ARC_RELOC_HOWTO(ARC_ALIGN, 84, \
+ 2, \
+ 0, \
+ replace_none, \
+ dont, \
+ 0 )
+
+ARC_RELOC_HOWTO(ARC_ADD8, 85, \
+ 0, \
+ 8, \
+ replace_bits8, \
+ dont, \
+ ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_ADD16, 86, \
+ 1, \
+ 16, \
+ replace_bits16, \
+ dont, \
+ ( S + A ))
+
+ARC_RELOC_HOWTO(ARC_SUB8, 87, \
+ 0, \
+ 8, \
+ replace_bits8, \
+ dont, \
+ ( A - S + ICARRY ))
+
+ARC_RELOC_HOWTO(ARC_SUB16, 88, \
+ 1, \
+ 16, \
+ replace_bits16, \
+ dont, \
+ ( A - S + ICARRY ))
+
+ARC_RELOC_HOWTO(ARC_SUB32, 89, \
+ 2, \
+ 32, \
+ replace_word32, \
+ dont, \
+ ( A - S + ICARRY))
+
+ARC_RELOC_HOWTO(ARC_LO32, 90, \
+ 2, \
+ 32, \
+ replace_word32, \
+ dont, \
+ ( ( S + A ) & 4294967295 ))
+
+ARC_RELOC_HOWTO(ARC_HI32, 91, \
+ 2, \
+ 32, \
+ replace_word32, \
+ dont, \
+ ( ( S + A ) >> 32 ))
+
+ARC_RELOC_HOWTO(ARC_LO32_ME, 92, \
+ 2, \
+ 32, \
+ replace_word32, \
+ dont, \
+ ( ME ( ( ( S + A ) & 4294967295 ) ) ))
+
+ARC_RELOC_HOWTO(ARC_HI32_ME, 93, \
+ 2, \
+ 32, \
+ replace_word32, \
+ dont, \
+ ( ME ( ( ( S + A ) >> 32 ) ) ))
+
+ARC_RELOC_HOWTO(ARC_N64, 94, \
+ 2, \
+ 32, \
+ replace_word32, \
+ dont, \
+ ( DEREFP - ( S + A ) ))
+
+ARC_RELOC_HOWTO(ARC_SDA_LDST3, 95, \
+ 2, \
+ 9, \
+ replace_disp9ls, \
+ signed, \
+ ( ( ( S + A ) - _SDA_BASE_ ) >> 3 ))
+
+ARC_RELOC_HOWTO(ARC_NLO32, 96, \
+ 2, \
+ 32, \
+ replace_word32, \
+ dont, \
+ ( DEREFP - ( ( S + A ) & 4294967295 ) ))
+
+ARC_RELOC_HOWTO(ARC_NLO32_ME, 97, \
+ 2, \
+ 32, \
+ replace_word32, \
+ dont, \
+ ( ME ( ( DEREFP - ( ( S + A ) & 4294967295 ) ) ) ))
+
diff --git a/include/elf/arc.h b/include/elf/arc.h
index a910c94ac20..4cfe7ad2060 100644
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -50,6 +50,7 @@ END_RELOC_NUMBERS (R_ARC_max)
#define E_ARC_MACH_ARC700 0x00000003
#define EF_ARC_CPU_ARCV2EM 0x00000005
#define EF_ARC_CPU_ARCV2HS 0x00000006
+#define EF_ARC_CPU_ARC64 0x00000007
/* ARC Linux specific ABIs. */
#define E_ARC_OSABI_ORIG 0x00000000 /* MUST be 0 for back-compat. */
diff --git a/include/elf/common.h b/include/elf/common.h
index 4d94c4fd5b3..c03b3aa77ed 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -343,6 +343,9 @@
#define EM_NFP 250 /* Netronome Flow Processor. */
#define EM_CSKY 252 /* C-SKY processor family. */
+#define EM_ARC_COMPACT3_64 253 /* ARCv3 64 bit machine. */
+#define EM_ARC_COMPACT3 255 /* ARCv3 32 bit machine. */
+
/* If it is necessary to assign new unofficial EM_* values, please pick large
random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
with official or non-GNU unofficial values.
diff --git a/include/opcode/arc-attrs.h b/include/opcode/arc-attrs.h
index 5162db01113..bb86bb6a541 100644
--- a/include/opcode/arc-attrs.h
+++ b/include/opcode/arc-attrs.h
@@ -37,8 +37,8 @@ const struct feature_type
} FEATURE_LIST_NAME [] =
{
{ BTSCN, ARC_OPCODE_ARCALL, "BITSCAN", "bit-scan" },
- { CD, ARC_OPCODE_ARCV2, "CD", "code-density" },
- { DIV, ARC_OPCODE_ARCV2, "DIV_REM", "div/rem" },
+ { CD, ARC_OPCODE_ARCVx, "CD", "code-density" },
+ { DIV, ARC_OPCODE_ARCVx, "DIV_REM", "div/rem" },
{ DP, ARC_OPCODE_ARCv2HS, "FPUD", "double-precision FPU" },
{ DPA, ARC_OPCODE_ARCv2EM, "FPUDA", "double assist FP" },
{ DPX, ARC_OPCODE_ARCFPX, "DPFP", "double-precision FPX" },
diff --git a/include/opcode/arc-func.h b/include/opcode/arc-func.h
index d0e84d8251f..972f5d6b733 100644
--- a/include/opcode/arc-func.h
+++ b/include/opcode/arc-func.h
@@ -100,9 +100,22 @@ replace_word32 (unsigned insn, int value ATTRIBUTE_UNUSED)
return insn;
}
-
#endif /* REPLACE_word32 */
+/* mask = 1111111111111111111111111111111111111111111111111111111111111111. */
+#ifndef REPLACE_word64
+#define REPLACE_word64
+ATTRIBUTE_UNUSED static unsigned
+replace_word64 (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+ insn = insn & ~0xffffffffffffffff;
+ insn |= ((value >> 0) & 0xffffffff) << 0;
+
+ return insn;
+}
+#endif /* REPLACE_word64 */
+
+
/* mask = 0000000000000000000000000000000011111111111111111111111111111111. */
#ifndef REPLACE_limm
#define REPLACE_limm
@@ -292,3 +305,75 @@ replace_jli (unsigned insn, int value)
}
#endif /* REPLACE_jli */
+
+#ifndef REPLACE_disp8ls
+#define REPLACE_disp8ls
+/* mask = 0000 0000 1111 1110 2000 0000 0000 0000. */
+ATTRIBUTE_UNUSED static unsigned
+replace_disp8ls (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+ insn = insn & ~0xfe8000;
+ insn |= ((value >> 0) & 0x007f) << 17;
+ insn |= ((value >> 7) & 0x0001) << 15;
+
+ return insn;
+}
+#endif /* REPLACE_disp8ls */
+
+#ifndef REPLACE_disp9s
+#define REPLACE_disp9s
+/* mask = 0000000111111111
+ insn = 1111001sssssssss. */
+static unsigned
+replace_disp9s (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+ insn = insn & ~0x1ff;
+ insn |= ((value >> 0) & 0x01ff) << 0;
+
+ return insn;
+}
+#endif /* REPLACE_disp9s */
+
+#ifndef REPLACE_disp6s
+#define REPLACE_disp6s
+/* mask = 0000000000111111
+ insn = 1111011000ssssss. */
+ATTRIBUTE_UNUSED static unsigned
+replace_disp6s (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+ insn = insn & ~0x3f;
+ insn |= ((value >> 0) & 0x003f) << 0;
+
+ return insn;
+}
+
+#endif /* REPLACE_disp6s */
+
+#ifndef REPLACE_disp7s
+#define REPLACE_disp7s
+/* mask = 0000000001111111
+ insn = 11101bbb1sssssss. */
+ATTRIBUTE_UNUSED static unsigned
+replace_disp7s (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+ insn = insn & ~0x7f;
+ insn |= ((value >> 0) & 0x007f) << 0;
+
+ return insn;
+}
+#endif /* REPLACE_disp7s */
+
+#ifndef REPLACE_disp12s
+#define REPLACE_disp12s
+/* mask = 00000000000000000000111111222222
+ insn = 00100RRR101010000RRRssssssSSSSSS. */
+ATTRIBUTE_UNUSED static unsigned
+replace_disp12s (unsigned insn, int value ATTRIBUTE_UNUSED)
+{
+ insn = insn & ~0xfff;
+ insn |= ((value >> 0) & 0x003f) << 6;
+ insn |= ((value >> 6) & 0x003f) << 0;
+
+ return insn;
+}
+#endif /* REPLACE_disp12s */
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 3a05cd89332..ec1e5a812b3 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -199,13 +199,17 @@ extern int arc_opcode_len (const struct arc_opcode *opcode);
#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
+#define ARC_OPCODE_ARC64 0x0010 /* ARC64 specific insns. */
/* CPU combi. */
#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
- | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS \
+ | ARC_OPCODE_ARC64)
#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
#define ARC_OPCODE_ARCV1 (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700)
#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
+#define ARC_OPCODE_ARCVx \
+ (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64)
#define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2)
/* The operands table is an array of struct arc_operand. */
@@ -326,6 +330,9 @@ extern const unsigned arc_NToperand;
/* Mark the colon position. */
#define ARC_OPERAND_COLON 0x4000
+/* Mark a floating point register. */
+#define ARC_OPERAND_FP 0x8000
+
/* Mask for selecting the type for typecheck purposes. */
#define ARC_OPERAND_TYPECHECK_MASK \
(ARC_OPERAND_IR \
@@ -370,6 +377,16 @@ struct arc_flag_class
/* List of valid flags (codes). */
unsigned flags[256];
+
+ /* Some special cases needs to use insert/extract functions for
+ flags as well. The function prototypes are identically like the
+ one used for insertion/extraction of an operand. The reason
+ beeing the ability of reusing these functions. */
+ unsigned long long (*insert) (unsigned long long instruction,
+ long long int op,
+ const char **errmsg);
+ long long int (*extract) (unsigned long long instruction,
+ bfd_boolean *invalid);
};
extern const struct arc_flag_class arc_flag_classes[];
@@ -442,6 +459,8 @@ struct arc_pseudo_insn
extern const struct arc_pseudo_insn arc_pseudo_insns[];
extern const unsigned arc_num_pseudo_insn;
+extern const struct arc_pseudo_insn arc64_pseudo_insns[];
+extern const unsigned arc64_num_pseudo_insn;
/* Structure for AUXILIARY registers. */
struct arc_aux_reg
@@ -479,8 +498,10 @@ extern const unsigned arc_num_relax_opcodes;
#define FIELDC(word) ((word & 0x3F) << 6)
#define FIELDF (0x01 << 15)
#define FIELDQ (0x1F)
+#define HARD_FIELDF (0x00)
-#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
+#define INSN3OP(MOP,SOP) \
+ (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16) | HARD_FIELDF)
#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
@@ -668,6 +689,105 @@ typedef enum
#define ARC_NUM_ADDRTYPES 16
+/*ARC64 floating point enums. */
+enum FP_SIZE {
+ P_HALF = 0,
+ P_SINGLE = 1,
+ P_DOUBLE = 2
+};
+
+enum TPOF {
+ TOPF_FMADD = 0,
+ TOPF_FMSUB = 1,
+ TOPF_FNMADD = 2,
+ TOPF_FNMSUB = 3,
+ TOPF_VFMADD = 4,
+ TOPF_VFMSUB = 5,
+ TOPF_VFNMADD = 6,
+ TOPF_VFNMSUB = 7,
+
+ TOPF_VFMADDS = 0xC,
+ TOPF_VFMSUBS = 0xD,
+ TOPF_VFNMADDS = 0xE,
+ TOPF_VFNMSUBS = 0xF
+};
+
+enum DPOF {
+ DOPF_FADD = 0,
+ DOPF_FSUB = 1,
+ DOPF_FMUL = 2,
+ DOPF_FDIV = 3,
+ DOPF_FCMP = 4,
+ DOPF_FCMPF = 5,
+ DOPF_FMIN = 6,
+ DOPF_FMAX = 7,
+ DOPF_FSGNJ = 8,
+ DOPF_FSGNJN = 10,
+ DOPF_FSGNJX = 11,
+
+ DOPF_VFADD = 0x10,
+ DOPF_VFSUB = 0x11,
+ DOPF_VFMUL = 0x12,
+ DOPF_VFDIV = 0x13,
+ DOPF_VFADDS = 0x14,
+ DOPF_VFSUBS = 0x15,
+ DOPF_VFMULS = 0x16,
+ DOPF_VFDIVS = 0x17
+};
+
+enum SOPF {
+ SOPF_FSQRT = 0,
+ SOPF_VFSQRT = 1,
+};
+
+enum COPF {
+ COPF_FMOV = 0,
+ COPF_VFMOV = 1,
+};
+
+enum CONVOPS {
+ FUINT2S = 0,
+ FS2UINT = 0,
+ FINT2S = 0,
+ FS2INT = 0,
+ FSRND = 0,
+ F2UINT_RZ = 0,
+ FSINT_RZ = 0,
+ FSRND_RZ = 0,
+ FMVI2S = 0,
+ FMVS2I = 0,
+ FS2H = 0,
+ FH2S = 0,
+ FS2H_RZ = 0,
+
+ FUINT2D = 1,
+ FS2UL = 1,
+ FINT2D = 1,
+ FS2L = 1,
+ FS2D = 1,
+ FS2UL_RZ = 1,
+ FS2L_RZ = 1,
+
+ FUL2S = 2,
+ FD2UINT = 2,
+ FL2S = 2,
+ FD2INT = 2,
+ FD2S = 2,
+ FD2UINT_RZ = 2,
+ FD2INT_RZ = 2,
+
+ FUL2D = 3,
+ FD2UL = 3,
+ FL2D = 3,
+ FD2L = 3,
+ FDRND = 3,
+ FD2UL_RZ = 3,
+ FD2L_RZ = 3,
+ FDRND_RZ = 3,
+ FMVL2D = 3,
+ FMVD2L = 3,
+};
+
#ifdef __cplusplus
}
#endif
diff --git a/ld/Makefile.am b/ld/Makefile.am
index 1a88965f7ca..29c70aa440b 100644
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -163,6 +163,7 @@ ALL_EMULATION_SOURCES = \
earcelf.c \
earclinux.c \
earclinux_nps.c \
+ earc64linux.c \
earm_wince_pe.c \
earmelf.c \
earmelf_fbsd.c \
@@ -425,6 +426,7 @@ ALL_64_EMULATION_SOURCES = \
eelf64_sparc.c \
eelf64_sparc_fbsd.c \
eelf64_sparc_sol2.c \
+ eelf64arc.c \
eelf64alpha.c \
eelf64alpha_fbsd.c \
eelf64alpha_nbsd.c \
@@ -649,6 +651,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcelf.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux_nps.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earc64linux.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earm_wince_pe.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_fbsd.Pc@am__quote@
@@ -907,6 +910,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_sparc.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_sparc_fbsd.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_sparc_sol2.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64arc.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_fbsd.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_nbsd.Pc@am__quote@
diff --git a/ld/Makefile.in b/ld/Makefile.in
index 20c3bc6a091..7c040820e5c 100644
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -646,6 +646,7 @@ ALL_EMULATION_SOURCES = \
earcelf.c \
earclinux.c \
earclinux_nps.c \
+ earc64linux.c \
earm_wince_pe.c \
earmelf.c \
earmelf_fbsd.c \
@@ -907,6 +908,7 @@ ALL_64_EMULATION_SOURCES = \
eelf64_sparc.c \
eelf64_sparc_fbsd.c \
eelf64_sparc_sol2.c \
+ eelf64arc.c \
eelf64alpha.c \
eelf64alpha_fbsd.c \
eelf64alpha_nbsd.c \
@@ -1194,6 +1196,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eaixrs6.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealpha.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ealphavms.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earc64linux.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcelf.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux_nps.Po@am__quote@
@@ -1349,6 +1352,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_fbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_nbsd.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64arc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bmip.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip.Po@am__quote@
@@ -2244,6 +2248,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earcelf.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earclinux_nps.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earc64linux.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earm_wince_pe.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/earmelf_fbsd.Pc@am__quote@
@@ -2502,6 +2507,7 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_sparc.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_sparc_fbsd.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_sparc_sol2.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64arc.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_fbsd.Pc@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_nbsd.Pc@am__quote@
diff --git a/ld/configure.tgt b/ld/configure.tgt
index 87c7d9a4cad..37a2c9537f6 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -104,8 +104,16 @@ alpha*-*-*vms*) targ_emul=alphavms
;;
am33_2.0-*-linux*) targ_emul=elf32am33lin # mn10300 variant
;;
-arc*-*-elf*) targ_emul=arcelf
- targ_extra_emuls="arclinux arclinux_nps arcv2elf arcv2elfx"
+arc-*-elf* | arc[be]*-*-elf*) targ_emul=arcelf
+ targ_extra_emuls=elf64arc
+ targ_extra_emuls="${targ_extra_emuls} arclinux arclinux_nps arcv2elf arcv2elfx"
+ ;;
+arc64-*elf*) targ_emul=elf64arc
+ targ_extra_emuls=arcelf
+ targ_extra_emuls="${targ_extra_emuls} arclinux arclinux_nps arcv2elf arcv2elfx"
+ ;;
+arc64-*-linux*) targ_emul=arc64linux
+ targ_extra_emuls="${targ_extra_emuls} elf64arc"
;;
arc*-*-linux*) case "${with_cpu}" in
nps400) targ_emul=arclinux_nps
@@ -115,7 +123,7 @@ arc*-*-linux*) case "${with_cpu}" in
targ_extra_emuls=arclinux_nps
;;
esac
- targ_extra_emuls="${targ_extra_emuls} arcelf arcv2elf arcv2elfx"
+ targ_extra_emuls="${targ_extra_emuls} arcelf arcv2elf arcv2elfx elf64arc"
;;
arm*-*-cegcc*) targ_emul=arm_wince_pe
targ_extra_ofiles="deffilep.o pe-dll.o"
diff --git a/ld/emulparams/arc64linux.sh b/ld/emulparams/arc64linux.sh
new file mode 100644
index 00000000000..3ffa535304b
--- /dev/null
+++ b/ld/emulparams/arc64linux.sh
@@ -0,0 +1,22 @@
+ARCH=arc
+
+SCRIPT_NAME=elf
+ELFSIZE=64
+OUTPUT_FORMAT="elf64-littlearc"
+
+TEMPLATE_NAME=elf
+
+GENERATE_SHLIB_SCRIPT=yes
+GENERATE_PIE_SCRIPT=yes
+
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
+
+TEXT_START_ADDR=0x10000
+
+ENTRY=__start
+
+# To support RELRO security feature.
+NO_SMALL_DATA=yes
+SEPARATE_GOTPLT=4 #FIXME! what is the true value here?
+GENERATE_COMBRELOC_SCRIPT=yes
diff --git a/ld/emulparams/arcelf.sh b/ld/emulparams/arcelf.sh
index 625ec397790..06c7e1a79d1 100644
--- a/ld/emulparams/arcelf.sh
+++ b/ld/emulparams/arcelf.sh
@@ -21,3 +21,4 @@ OTHER_SECTIONS="/DISCARD/ : { *(.__arc_profile_*) }"
EMBEDDED=yes
GENERATE_SHLIB_SCRIPT=yes
+EXTRA_EM_FILE=arcelf
diff --git a/ld/emulparams/arcv2elf.sh b/ld/emulparams/arcv2elf.sh
index 4824f3540c8..4a21daec759 100644
--- a/ld/emulparams/arcv2elf.sh
+++ b/ld/emulparams/arcv2elf.sh
@@ -24,4 +24,4 @@ TEXT_START_ADDR=0x100
ENTRY=__start
SDATA_START_SYMBOLS='__SDATA_BEGIN__ = . + 0x100;'
JLI_START_TABLE='__JLI_TABLE__ = .;'
-OTHER_SECTIONS="/DISCARD/ : { *(.__arc_profile_*) }"
+EXTRA_EM_FILE=arcelf
diff --git a/ld/emulparams/arcv2elfx.sh b/ld/emulparams/arcv2elfx.sh
index ad134441255..3477e74a604 100644
--- a/ld/emulparams/arcv2elfx.sh
+++ b/ld/emulparams/arcv2elfx.sh
@@ -20,5 +20,5 @@ TEXT_START_ADDR=0x100
ENTRY=__start
SDATA_START_SYMBOLS='__SDATA_BEGIN__ = . + 0x100;'
JLI_START_TABLE='__JLI_TABLE__ = .;'
-OTHER_SECTIONS="/DISCARD/ : { *(.__arc_profile_*) }"
EMBEDDED=yes
+EXTRA_EM_FILE=arcelf
diff --git a/ld/emulparams/elf64arc.sh b/ld/emulparams/elf64arc.sh
new file mode 100644
index 00000000000..56cf1b2a117
--- /dev/null
+++ b/ld/emulparams/elf64arc.sh
@@ -0,0 +1,15 @@
+SCRIPT_NAME=elf
+ELFSIZE=64
+SCRIPT_NAME=elfarc
+TEMPLATE_NAME=elf
+OUTPUT_FORMAT="elf64-littlearc"
+
+TEXT_START_ADDR=0x00
+
+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
+ARCH=arc
+ENTRY=__start
+EMBEDDED=yes
+
+GENERATE_SHLIB_SCRIPT=yes
+EXTRA_EM_FILE=arcelf
diff --git a/ld/emultempl/arcelf.em b/ld/emultempl/arcelf.em
new file mode 100644
index 00000000000..035d25d3cf5
--- /dev/null
+++ b/ld/emultempl/arcelf.em
@@ -0,0 +1,40 @@
+# This shell script emits a C file. -*- C -*-
+# Copyright (C) 2019 Free Software Foundation, Inc.
+#
+# Copyright 2019 Synopsys Inc.
+#
+# This file is part of GLD, the Gnu Linker.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# This file is sourced from elf32.em, and defines extra arcelf
+# specific routines.
+#
+fragment <<EOF
+
+static void
+arcelf_before_allocation (void)
+{
+ /* Call main function; we're just extending it. */
+ gld${EMULATION_NAME}_before_allocation ();
+
+ /* ARC needs two step relaxation. */
+ link_info.relax_pass = 2;
+}
+
+EOF
+
+LDEMUL_BEFORE_ALLOCATION=arcelf_before_allocation
diff --git a/ld/testsuite/ld-arc/arc.exp b/ld/testsuite/ld-arc/arc.exp
index a8886ca1910..b7635feef7d 100644
--- a/ld/testsuite/ld-arc/arc.exp
+++ b/ld/testsuite/ld-arc/arc.exp
@@ -18,7 +18,8 @@
# MA 02110-1301, USA.
#
-if { ![istarget arc*-*-*] } {
+if { ![istarget arc*-*-*]
+ || [istarget arc64-*-*] } {
return
}
diff --git a/ld/testsuite/ld-arc/hiddso.d b/ld/testsuite/ld-arc/hiddso.d
new file mode 100644
index 00000000000..a336bac2331
--- /dev/null
+++ b/ld/testsuite/ld-arc/hiddso.d
@@ -0,0 +1,6 @@
+#source: hiddsoA.s
+#source: hiddsoB.s
+#ld: --shared -marclinux
+#readelf: -r
+
+There are no relocations in this file.
\ No newline at end of file
diff --git a/ld/testsuite/ld-arc/hiddsoA.s b/ld/testsuite/ld-arc/hiddsoA.s
new file mode 100644
index 00000000000..eafda4d051a
--- /dev/null
+++ b/ld/testsuite/ld-arc/hiddsoA.s
@@ -0,0 +1,3 @@
+ .hidden hidobj
+ .section .text
+ add r2,pcl,@hidobj@pcl
diff --git a/ld/testsuite/ld-arc/hiddsoB.s b/ld/testsuite/ld-arc/hiddsoB.s
new file mode 100644
index 00000000000..635c2405877
--- /dev/null
+++ b/ld/testsuite/ld-arc/hiddsoB.s
@@ -0,0 +1,6 @@
+ .data
+ .hidden hidobj
+ .global hidobj
+ .type hidobj,@object
+hidobj:
+ .zero 4
diff --git a/ld/testsuite/ld-arc/nps-1a.d b/ld/testsuite/ld-arc/nps-1a.d
index 4eae02472a3..687191dae1d 100644
--- a/ld/testsuite/ld-arc/nps-1a.d
+++ b/ld/testsuite/ld-arc/nps-1a.d
@@ -1,6 +1,6 @@
#source: nps-1.s
#as: -mcpu=arc700 -mnps400
-#ld: -defsym=foo=0x57f03000
+#ld: -defsym=foo=0x57f03000 -T sda-relocs.ld
#objdump: -d
.*: +file format .*arc.*
diff --git a/ld/testsuite/ld-arc/nps-1b.d b/ld/testsuite/ld-arc/nps-1b.d
index a4848b8b7d8..4845d6b100a 100644
--- a/ld/testsuite/ld-arc/nps-1b.d
+++ b/ld/testsuite/ld-arc/nps-1b.d
@@ -1,4 +1,4 @@
#source: nps-1.s
#as: -mcpu=arc700 -mnps400
-#ld: -defsym=foo=0x56f03000
+#ld: -defsym=foo=0x56f03000 -T sda-relocs.ld
#error_output: nps-1b.err
diff --git a/ld/testsuite/ld-arc/relax-call-1.d b/ld/testsuite/ld-arc/relax-call-1.d
new file mode 100644
index 00000000000..e08475b9dd9
--- /dev/null
+++ b/ld/testsuite/ld-arc/relax-call-1.d
@@ -0,0 +1,20 @@
+#source: relax-call-1.s
+#as: -mlinker-relax
+#ld: -q -A elf32-arclittle -relax
+#objdump: -dr
+
+[^:]+: file format elf.*arc
+
+
+Disassembly of section \.text:
+
+[01]+ <__start>:
+\s+[0-9]+: f801 bl_s 4 ;[0-9]+ <foo>
+ [0-9]+: R_ARC_S13_PCREL foo
+ [0-9]+: R_ARC_NONE \*ABS\*\+0x4
+\s+[0-9]+: f801 bl_s 4 ;[0-9]+ <foo>
+ [0-9]+: R_ARC_S13_PCREL foo
+
+[0-9]+ <foo>:
+\s+[0-9]+: 2000 0000 add r0,r0,r0
+ [0-9]+: R_ARC_NONE \*ABS\*\+0x6
diff --git a/ld/testsuite/ld-arc/relax-call-1.s b/ld/testsuite/ld-arc/relax-call-1.s
new file mode 100644
index 00000000000..6993ae46f26
--- /dev/null
+++ b/ld/testsuite/ld-arc/relax-call-1.s
@@ -0,0 +1,14 @@
+ .arc_attribute Tag_ARC_PCS_config, 2
+ .section .text
+ .align 4
+ .global __start
+ .type __start, @function
+__start:
+ bl @foo
+ bl_s @foo
+ .size __start, .-__start
+
+ .align 4
+foo:
+ add r0,r0,r0
+ .size foo, .-foo
diff --git a/ld/testsuite/ld-arc/relax-call-2.d b/ld/testsuite/ld-arc/relax-call-2.d
new file mode 100644
index 00000000000..5dfcf0d055b
--- /dev/null
+++ b/ld/testsuite/ld-arc/relax-call-2.d
@@ -0,0 +1,27 @@
+#source: relax-call-2.s
+#as: -mlinker-relax
+#ld: -q -A elf32-arclittle -relax
+#objdump: -dr
+
+[^:]+: file format elf.*arc
+
+
+Disassembly of section \.text:
+
+[0-9]+ <__start>:
+\s+[0-9a-f]+:\s+2000 0000\s+add.*
+\s+[0-9]+: R_ARC_NONE\s+\*ABS\*\+0x4
+\s+[0-9a-f]+:\s+f801\s+bl_s\s+4\s+;[0-9a-f]+ <foo>
+\s+[0-9]+: R_ARC_S13_PCREL\s+foo
+\s+[0-9a-f]+:\s+78e0\s.*
+\s+[0-9]+: R_ARC_NONE\s+\*ABS\*\+0x4
+
+[0-9]+ <foo>:
+\s+[0-9a-f]+:\s+2000 0000\s+add.*
+\s+[0-9a-f]+:\s+fffd\s+bl_s\s+-12\s+;[0-9a-f]+ <__start>
+\s+[0-9c]+: R_ARC_S13_PCREL\s+__start
+\s+[0-9a-f]+:\s+78e0\s.*
+\s+[0-9e]+: R_ARC_NONE\s+\*ABS\*\+0x6
+
+[0-9]+ <goo>:
+\s+[0-9a-f]+:\s+2000 0000\s+add.*
diff --git a/ld/testsuite/ld-arc/relax-call-2.s b/ld/testsuite/ld-arc/relax-call-2.s
new file mode 100644
index 00000000000..8f5204e2c5a
--- /dev/null
+++ b/ld/testsuite/ld-arc/relax-call-2.s
@@ -0,0 +1,23 @@
+ .section .text
+ .align 4
+ .global __start
+ .type __start, @function
+__start:
+ add r0,r0,r0
+ bl @foo
+ .size __start, .-__start
+
+ .align 4
+ .global foo
+ .type foo, @function
+foo:
+ add r0,r0,r0
+ bl_s @__start
+ .size foo, .-foo
+
+ .align 4
+ .global goo
+ .type goo, @function
+goo:
+ add r0,r0,r0
+ .size goo, .-goo
diff --git a/ld/testsuite/ld-arc/relax-call-3.d b/ld/testsuite/ld-arc/relax-call-3.d
new file mode 100644
index 00000000000..a1abcb0d848
--- /dev/null
+++ b/ld/testsuite/ld-arc/relax-call-3.d
@@ -0,0 +1,36 @@
+#source: relax-call-3.s
+#as: -mlinker-relax
+#ld: -q -A elf32-arclittle -relax
+#objdump: -dr
+
+[^:]+: file format elf.*arc
+
+
+Disassembly of section \.text:
+
+[0-9]+ <__start>:
+\s+[01]+: f803 bl_s 12 ;[0-9a-f]+ <foo>
+\s+[0-9]+: R_ARC_S13_PCREL foo
+\s+[0-9]+: R_ARC_NONE \*ABS\*\+0x4
+
+[0-9]+ <.L1>:
+\s+[0-9]+: 0002 0000.*
+\s+[0-9]+: R_ARC_32 \.L1
+\s+[0-9]+: R_ARC_SUB32 \.L0
+\s+[0-9]+: 0002 0002.*
+\s+[0-9]+: R_ARC_ADD16 \.L1
+\s+[0-9]+: R_ARC_SUB16 \.L0
+\s+[0-9]+: R_ARC_ADD8 \.L1
+\s+[0-9]+: R_ARC_SUB8 \.L0
+\s+[0-9a-f]+: 78e0\s+nop_s
+\s+[0-9a-f]+: R_ARC_NONE \*ABS\*\+0x4
+
+[0-9c]+ <foo>:
+\s+[0-9a-f]+: 2000 0000 add r0,r0,r0
+\s+[0-9a-f]+: fffc bl_s -16 ;[0-9a-f]+ <__start>
+\s+[0-9a-f]+: R_ARC_S13_PCREL __start
+\s+[0-9a-f]+: 78e0\s+nop_s
+\s+[0-9a-f]+: R_ARC_NONE \*ABS\*\+0x6
+
+[0-9a-f]+ <goo>:
+\s+[0-9a-f]+: 2000 0000 add r0,r0,r0
diff --git a/ld/testsuite/ld-arc/relax-call-3.s b/ld/testsuite/ld-arc/relax-call-3.s
new file mode 100644
index 00000000000..371949ba6e1
--- /dev/null
+++ b/ld/testsuite/ld-arc/relax-call-3.s
@@ -0,0 +1,27 @@
+ .section .text
+ .align 4
+ .global __start
+ .type __start, @function
+__start:
+.L0:
+ bl @foo
+.L1:
+ .word @.L1 - @.L0
+ .hword @.L1 - @.L0
+ .byte @.L1 - @.L0
+ .size __start, .-__start
+
+ .align 4
+ .global foo
+ .type foo, @function
+foo:
+ add r0,r0,r0
+ bl_s @__start
+ .size foo, .-foo
+
+ .align 4
+ .global goo
+ .type goo, @function
+goo:
+ add r0,r0,r0
+ .size goo, .-goo
diff --git a/ld/testsuite/ld-arc/relax-local-pic.d b/ld/testsuite/ld-arc/relax-local-pic.d
index 181a963223a..1cb2cbf057f 100644
--- a/ld/testsuite/ld-arc/relax-local-pic.d
+++ b/ld/testsuite/ld-arc/relax-local-pic.d
@@ -3,12 +3,12 @@
#ld: -q -A elf32-arclittle -relax
#objdump: -dr
-[^:]+: file format elf32-.*arc
+[^:]+: file format elf.*arc
Disassembly of section \.text:
[0-9a-f]+ <__start>:
\s+[0-9a-f]+: 2700 7f84 0000 [0-9a-f]+\s+add\s+r4,pcl,.*
- [0-9a-f]+: R_ARC_PC32 a_in_other_thread
+\s+[0-9a-f]+: R_ARC_PC32 a_in_other_thread
\s+[0-9a-f]+: 1c00 [0-9a-f\s]+ st\s+.*
diff --git a/ld/testsuite/ld-arc/weakhid.s b/ld/testsuite/ld-arc/weakhid.s
new file mode 100644
index 00000000000..a8c87da1a2d
--- /dev/null
+++ b/ld/testsuite/ld-arc/weakhid.s
@@ -0,0 +1,13 @@
+ .weak xweakobj
+ .weak xweakhidobj
+ .hidden xweakhidobj
+
+ .data
+ .global x
+ .type x,@object
+x:
+ .word xweakhidobj
+ .word xweakobj
+ .word xregobj
+.Lfe1:
+ .size x,.Lfe1-x
diff --git a/ld/testsuite/ld-arc/weakhiddso.d b/ld/testsuite/ld-arc/weakhiddso.d
new file mode 100644
index 00000000000..f52f27fc048
--- /dev/null
+++ b/ld/testsuite/ld-arc/weakhiddso.d
@@ -0,0 +1,29 @@
+#source: weakhid.s
+#ld: --shared -m arclinux -z nocombreloc --hash-style=sysv
+#objdump: -s -R -T
+
+# Check that .weak and .weak .hidden object references are handled
+# correctly when generating a DSO. Copied from CRIS port.
+
+.*: +file format .*arc.*
+
+DYNAMIC SYMBOL TABLE:
+0+2208 l d \.data 0+ \.data
+0+2208 g DO \.data 0+c x
+0+ D \*UND\* 0+ xregobj
+0+2214 g D \.data 0+ __bss_start
+0+ w D \*UND\* 0+ xweakobj
+0+2214 g D \.data 0+ _edata
+0+2214 g D \.data 0+ _end
+
+
+DYNAMIC RELOCATION RECORDS
+OFFSET TYPE VALUE
+0+2210 R_ARC_32 +xregobj
+0+ R_ARC_NONE +\*ABS\*
+
+Contents of section \.hash:
+#...
+Contents of section \.data:
+ 2208 00000000 00000000 00000000 .*
+#...
\ No newline at end of file
diff --git a/ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd
new file mode 100644
index 00000000000..b40a5d77230
--- /dev/null
+++ b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-exe.dd
@@ -0,0 +1,29 @@
+# an exemplary output
+#
+# test_static.exe: file format elf64-littlearc
+#
+#
+# Disassembly of section .text:
+#
+# 0000000000001000 <__start>:
+# 1000: 78e0 nop_s
+# 1002: 2731 ff0e 0000 7000 ldl r14,[pcl,28672@s32] ;8000 <.got>
+# 1006: R_ARC_GOTPC32 foo
+# 100a: 2731 ff0f 0000 7000 ldl r15,[pcl,28672@s32] ;8008 <.got+0x8>
+# 100e: R_ARC_GOTPC32 bar
+# 1012: 78e0 nop_s
+# 1014: 0000 0000 b 0 ;1014 <__start+0x14>
+
+[^:]+:\s+file format elf.*-.*arc
+
+
+Disassembly of section .text:
+
+^[0-9a-f]+.*:
+\s*[0-9a-f]+:\s+[0-9a-f\s]+nop_s
+\s*[0-9a-f]+:\s+[0-9a-f\s]+ldl\s+r14,.*
+\s*[0-9a-f]+:\s+R_ARC_GOTPC32\s+foo
+\s*[0-9a-f]+:\s+[0-9a-f\s]+ldl\s+r15,.*
+\s*[0-9a-f]+:\s+R_ARC_GOTPC32\s+bar
+\s*[0-9a-f]+:\s+[0-9a-f\s]+nop_s
+\s*[0-9a-f]+:.*
diff --git a/ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd
new file mode 100644
index 00000000000..ee95fea7de0
--- /dev/null
+++ b/ld/testsuite/ld-arc64/arcv3_64-reloc-near-so.dd
@@ -0,0 +1,23 @@
+# an exemplary output
+#
+# test_dynamic.so: file format elf64-littlearc
+#
+#
+# Disassembly of section .got:
+#
+# 0000000000002440 <.got>:
+# 2440: 60 23 00 00 .word 0x00002360
+# ...
+# 2458: R_ARC_GLOB_DAT foo
+# 2460: R_ARC_GLOB_DAT bar
+
+[^:]+:\s+file format elf.*-.*arc
+
+
+Disassembly of section .got:
+
+^[0-9a-f]+.*:
+\s*[0-9a-f]+:.*
+\s*\.\.\.
+\s*[0-9a-f]+:\s+R_ARC_GLOB_DAT\s+foo
+\s*[0-9a-f]+:\s+R_ARC_GLOB_DAT\s+bar
diff --git a/ld/testsuite/ld-arc64/arcv3_64-reloc-near.s b/ld/testsuite/ld-arc64/arcv3_64-reloc-near.s
new file mode 100644
index 00000000000..1423f924414
--- /dev/null
+++ b/ld/testsuite/ld-arc64/arcv3_64-reloc-near.s
@@ -0,0 +1,11 @@
+ .comm foo,4
+ .comm bar,4
+
+ .text
+ .align 8
+
+ .global __start
+__start:
+ nop_s # messing with the alignment a bit
+ ldl r14, [pcl, @foo@gotpc]
+ ldl r15, [pcl, @bar@gotpc]
diff --git a/ld/testsuite/ld-arc64/arcv3_64.exp b/ld/testsuite/ld-arc64/arcv3_64.exp
new file mode 100644
index 00000000000..372dec01176
--- /dev/null
+++ b/ld/testsuite/ld-arc64/arcv3_64.exp
@@ -0,0 +1,36 @@
+# Copyright (C) 2020 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if { ![istarget arc64-*-*] } {
+ return
+}
+
+set arcv3_64_tests {
+ { "Near relocations (executable)"
+ "-q" "" "" {arcv3_64-reloc-near.s}
+ { { objdump { -Dr -j .text } arcv3_64-reloc-near-exe.dd } }
+ "arcv3_64-reloc.exe" }
+ { "Near relocations (shared object)"
+ "-shared -q" "" "" {arcv3_64-reloc-near.s}
+ { { objdump -DRj.got arcv3_64-reloc-near-so.dd } }
+ "arcv3_64-reloc-near.so" }
+}
+
+run_ld_link_tests $arcv3_64_tests
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index dc9e490ce8a..0c2923ce763 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -85,7 +85,7 @@ static const char * const regnames[64] =
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
- "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
+ "r24", "r25", "r26", "fp", "sp", "ilink", "r30", "blink",
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
@@ -93,6 +93,14 @@ static const char * const regnames[64] =
"r56", "r57", "r58", "r59", "lp_count", "reserved", "LIMM", "pcl"
};
+static const char * const fpnames[32] =
+{
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
+};
+
static const char * const addrtypenames[ARC_NUM_ADDRTYPES] =
{
"bd", "jid", "lbd", "mbd", "sd", "sm", "xa", "xd",
@@ -126,7 +134,6 @@ static unsigned enforced_isa_mask = ARC_OPCODE_NONE;
static bfd_boolean print_hex = FALSE;
/* Macros section. */
-
#ifdef DEBUG
# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
#else
@@ -140,6 +147,12 @@ static bfd_boolean print_hex = FALSE;
#define BITS(word,s,e) (((word) >> (s)) & ((1ull << ((e) - (s)) << 1) - 1))
#define OPCODE_32BIT_INSN(word) (BITS ((word), 27, 31))
+#define REG_PCL 63
+#define REG_LIMM 62
+#define REG_LIMM_S 30
+#define REG_U32 62
+#define REG_S32 60
+
/* Functions implementation. */
/* Initialize private data. */
@@ -277,7 +290,7 @@ find_format_from_table (struct disassemble_info *info,
if (arc_opcode_len (opcode) != (int) insn_len)
continue;
- if ((insn & opcode->mask) != opcode->opcode)
+ if ((insn & opcode->mask) != (opcode->mask & opcode->opcode))
continue;
*has_limm = FALSE;
@@ -285,7 +298,7 @@ find_format_from_table (struct disassemble_info *info,
/* Possible candidate, check the operands. */
for (opidx = opcode->operands; *opidx; opidx++)
{
- int value, limmind;
+ int value, slimmind;
const struct arc_operand *operand = &arc_operands[*opidx];
if (operand->flags & ARC_OPERAND_FAKE)
@@ -296,19 +309,20 @@ find_format_from_table (struct disassemble_info *info,
else
value = (insn >> operand->shift) & ((1ull << operand->bits) - 1);
- /* Check for LIMM indicator. If it is there, then make sure
- we pick the right format. */
- limmind = (isa_mask & ARC_OPCODE_ARCV2) ? 0x1E : 0x3E;
+ /* Check for (short) LIMM indicator. If it is there, then
+ make sure we pick the right format. */
+ slimmind = (isa_mask & (ARC_OPCODE_ARCV2 | ARC_OPCODE_ARC64)) ?
+ REG_LIMM_S : REG_LIMM;
if (operand->flags & ARC_OPERAND_IR
&& !(operand->flags & ARC_OPERAND_LIMM))
- {
- if ((value == 0x3E && insn_len == 4)
- || (value == limmind && insn_len == 2))
- {
- invalid = TRUE;
- break;
- }
- }
+ if ((value == REG_LIMM && insn_len == 4)
+ || (value == slimmind && insn_len == 2)
+ || (isa_mask & ARC_OPCODE_ARC64
+ && (value == REG_S32) && (insn_len == 4)))
+ {
+ invalid = TRUE;
+ break;
+ }
if (operand->flags & ARC_OPERAND_LIMM
&& !(operand->flags & ARC_OPERAND_DUPLICATE))
@@ -338,11 +352,15 @@ find_format_from_table (struct disassemble_info *info,
for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
{
+ bfd_boolean tmp = FALSE;
const struct arc_flag_operand *flg_operand =
&arc_flag_operands[*flgopridx];
- value = (insn >> flg_operand->shift)
- & ((1 << flg_operand->bits) - 1);
+ if (cl_flags->extract)
+ value = (*cl_flags->extract)(insn, &tmp);
+ else
+ value = (insn >> flg_operand->shift)
+ & ((1 << flg_operand->bits) - 1);
if (value == flg_operand->code)
foundA = 1;
if (value)
@@ -539,8 +557,14 @@ print_flags (const struct arc_opcode *opcode,
if (!flg_operand->favail)
continue;
- value = (insn[0] >> flg_operand->shift)
- & ((1 << flg_operand->bits) - 1);
+ if (cl_flags->extract)
+ {
+ bfd_boolean tmp = FALSE;
+ value = (*cl_flags->extract)(insn[0], &tmp);
+ }
+ else
+ value = (insn[0] >> flg_operand->shift)
+ & ((1 << flg_operand->bits) - 1);
if (value == flg_operand->code)
{
/* FIXME!: print correctly nt/t flag. */
@@ -667,6 +691,11 @@ arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
return (major_opcode > 0xb) ? 2 : 4;
break;
+ case bfd_mach_arcv3_64:
+ if (major_opcode == 0x0b
+ || major_opcode == 0x1c)
+ return 4;
+ /* Fall through. */
case bfd_mach_arc_arcv2:
return (major_opcode > 0x7) ? 2 : 4;
break;
@@ -810,7 +839,9 @@ parse_option (const char *option)
{ #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" }
#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
{ #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" }
-#define ARC_CPU_TYPE_NONE \
+#define ARC_CPU_TYPE_A64x(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARC64, "ARC64" }
+#define ARC_CPU_TYPE_NONE \
{ 0, 0, 0 }
/* A table of CPU names and opcode sets. */
@@ -983,6 +1014,10 @@ print_insn_arc (bfd_vma memaddr,
isa_mask = ARC_OPCODE_ARC600;
break;
+ case bfd_mach_arcv3_64:
+ isa_mask = ARC_OPCODE_ARC64;
+ break;
+
case bfd_mach_arc_arcv2:
default:
isa_mask = ARC_OPCODE_ARCv2EM;
@@ -1264,19 +1299,32 @@ print_insn_arc (bfd_vma memaddr,
{
const char *rname;
- assert (value >=0 && value < 64);
+ assert (value >= 0 && value < 64);
rname = arcExtMap_coreRegName (value);
if (!rname)
- rname = regnames[value];
+ {
+ if (operand->flags & ARC_OPERAND_FP)
+ rname = fpnames[value & 0x1f];
+ else
+ rname = regnames[value];
+ }
(*info->fprintf_func) (info->stream, "%s", rname);
if (operand->flags & ARC_OPERAND_TRUNCATE)
{
- rname = arcExtMap_coreRegName (value + 1);
- if (!rname)
- rname = regnames[value + 1];
+ if ((value & 0x01) == 0)
+ {
+ rname = arcExtMap_coreRegName (value + 1);
+ if (operand->flags & ARC_OPERAND_FP)
+ rname = fpnames[(value + 1) & 0x1f];
+ else
+ rname = regnames[value + 1];
+ }
+ else
+ rname = _("\nWarning: illegal use of double register "
+ "pair.\n");
(*info->fprintf_func) (info->stream, "%s", rname);
}
- if (value == 63)
+ if (value == REG_PCL)
rpcl = TRUE;
else
rpcl = FALSE;
@@ -1289,7 +1337,10 @@ print_insn_arc (bfd_vma memaddr,
(*info->fprintf_func) (info->stream, "%s", rname);
else
{
- (*info->fprintf_func) (info->stream, "%#x", value);
+ if (operand->flags & ARC_OPERAND_SIGNED)
+ (*info->fprintf_func) (info->stream, "%d@s32", value);
+ else
+ (*info->fprintf_func) (info->stream, "%#x", value);
if (info->insn_type == dis_branch
|| info->insn_type == dis_jsr)
info->target = (bfd_vma) value;
@@ -1355,7 +1406,7 @@ print_insn_arc (bfd_vma memaddr,
= ARC_OPERAND_KIND_LIMM;
/* It is not important to have exactly the LIMM indicator
here. */
- arc_infop->operands[arc_infop->operands_count].value = 63;
+ arc_infop->operands[arc_infop->operands_count].value = REG_PCL;
}
else
{
diff --git a/opcodes/arc-ext-tbl.h b/opcodes/arc-ext-tbl.h
index 47f45e33ffc..585d19bb638 100644
--- a/opcodes/arc-ext-tbl.h
+++ b/opcodes/arc-ext-tbl.h
@@ -122,3 +122,18 @@ EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45)
EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42)
EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
+
+#undef FLAGS_F
+#define FLAGS_F { 0 }
+
+#undef FLAGS_CCF
+#define FLAGS_CCF { C_CC }
+
+#undef FIELDF
+#define FIELDF 0x0
+
+#undef HARD_FIELDF
+#define HARD_FIELDF (0x01 << 15)
+
+EXTINSN3OP ("vpack2wl", ARC_OPCODE_ARC64, MOVE, NONE, 5, 0x38)
+EXTINSN3OP ("vpack2wm", ARC_OPCODE_ARC64, MOVE, NONE, 5, 0x39)
diff --git a/opcodes/arc-fxi.h b/opcodes/arc-fxi.h
index 31330cfedc3..0449f614a0f 100644
--- a/opcodes/arc-fxi.h
+++ b/opcodes/arc-fxi.h
@@ -1315,3 +1315,63 @@ extract_uimm6_axx_ (unsigned long long insn ATTRIBUTE_UNUSED,
return value;
}
#endif /* EXTRACT_UIMM6_AXX_ */
+
+/* mask = 0000022000011111. */
+#ifndef INSERT_UIMM9_A32_11_S
+#define INSERT_UIMM9_A32_11_S
+ATTRIBUTE_UNUSED static unsigned long long
+insert_uimm9_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ long long int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value & 0x03)
+ *errmsg = "Target address is not 32bit aligned.";
+
+ insn |= ((value >> 2) & 0x001f) << 0;
+ insn |= ((value >> 7) & 0x0003) << 9;
+ return insn;
+}
+#endif /* INSERT_UIMM9_A32_11_S */
+
+#ifndef EXTRACT_UIMM9_A32_11_S
+#define EXTRACT_UIMM9_A32_11_S
+ATTRIBUTE_UNUSED static long long int
+extract_uimm9_a32_11_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ bfd_boolean *invalid ATTRIBUTE_UNUSED)
+{
+ unsigned value = 0;
+ value |= ((insn >> 0) & 0x001f) << 2;
+ value |= ((insn >> 9) & 0x0003) << 7;
+
+ return value;
+}
+#endif /* EXTRACT_UIMM9_A32_11_S */
+
+/* mask = 0000022222220111. */
+#ifndef INSERT_UIMM10_13_S
+#define INSERT_UIMM10_13_S
+ATTRIBUTE_UNUSED static unsigned long long
+insert_uimm10_13_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ long long int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 0) & 0x0007) << 0;
+ insn |= ((value >> 3) & 0x007f) << 4;
+
+ return insn;
+}
+#endif /* INSERT_UIMM10_13_S */
+
+#ifndef EXTRACT_UIMM10_13_S
+#define EXTRACT_UIMM10_13_S
+ATTRIBUTE_UNUSED static long long int
+extract_uimm10_13_s (unsigned long long insn ATTRIBUTE_UNUSED,
+ bfd_boolean *invalid ATTRIBUTE_UNUSED)
+{
+ unsigned value = 0;
+ value |= ((insn >> 0) & 0x0007) << 0;
+ value |= ((insn >> 4) & 0x007f) << 3;
+
+ return value;
+}
+#endif /* EXTRACT_UIMM10_13_S */
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 675738aa6be..17b69425d84 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -53,6 +53,16 @@ insert_rb (unsigned long long insn,
return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
}
+/* Insert RB register into a push(d)l/pop(d)l instruction. */
+
+static unsigned long long
+insert_rbb (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x07) << 8) | (((value >> 3) & 0x07) << 1);
+}
+
/* Insert RB register with checks. */
static unsigned long long
@@ -66,6 +76,26 @@ insert_rb_chk (unsigned long long insn,
return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
}
+/* Insert a floating point register into fs2 slot. */
+
+static unsigned long long
+insert_fs2 (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x03) << 12);
+}
+
+/* Insert address writeback mode for 128-bit loads. */
+
+static unsigned long long
+insert_qq (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x01) << 11) | ((value & 0x02) << (6-1));
+}
+
static long long
extract_rb (unsigned long long insn,
bfd_boolean * invalid)
@@ -79,6 +109,41 @@ extract_rb (unsigned long long insn,
return value;
}
+static long long
+extract_rbb (unsigned long long insn,
+ bfd_boolean * invalid)
+{
+ int value = (((insn >> 1) & 0x07) << 3) | ((insn >> 8) & 0x07);
+
+ if (value == 0x3e && invalid)
+ *invalid = TRUE; /* A limm operand, it should be extracted in a
+ different way. */
+
+ return value;
+}
+
+/* Extract the floating point register number from fs2 slot. */
+
+static long long
+extract_fs2 (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ long long value;
+ value = (((insn >> 12) & 0x03) << 3) | ((insn >> 24) & 0x07);
+ return value;
+}
+
+/* Extract address writeback mode for 128-bit loads. */
+
+static long long
+extract_qq (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ long long value;
+ value = ((insn & 0x800) >> 11) | ((insn & 0x40) >> (6-1));
+ return value;
+}
+
static unsigned long long
insert_rad (unsigned long long insn,
long long value,
@@ -276,7 +341,8 @@ insert_gp (unsigned long long insn,
long long value,
const char ** errmsg)
{
- if (value != 26)
+ if (value != 26
+ && value != 30)
*errmsg = _("register must be GP");
return insn;
}
@@ -1364,11 +1430,33 @@ const struct arc_flag_operand arc_flag_operands[] =
/* FLAG. */
#define F_FLAG (F_NO_T + 1)
{ "f", 1, 1, 15, 1 },
-#define F_FFAKE (F_FLAG + 1)
+#define F_FFAKE (F_FLAG + 1)
{ "f", 0, 0, 0, 1 },
+#define F_AQ (F_FFAKE + 1)
+ { "aq", 1, 1, 15, 1 },
+#define F_RL (F_AQ + 1)
+ { "rl", 1, 1, 15, 1 },
+
+ /* Atomic operations. */
+#define F_ATO_ADD (F_RL + 1)
+ { "add", 0, 3, 0, 1 },
+#define F_ATO_OR (F_ATO_ADD + 1)
+ { "or", 1, 3, 0, 1 },
+#define F_ATO_AND (F_ATO_OR + 1)
+ { "and", 2, 3, 0, 1 },
+#define F_ATO_XOR (F_ATO_AND + 1)
+ { "xor", 3, 3, 0, 1 },
+#define F_ATO_MINU (F_ATO_XOR + 1)
+ { "minu", 4, 3, 0, 1 },
+#define F_ATO_MAXU (F_ATO_MINU + 1)
+ { "maxu", 5, 3, 0, 1 },
+#define F_ATO_MIN (F_ATO_MAXU + 1)
+ { "min", 6, 3, 0, 1 },
+#define F_ATO_MAX (F_ATO_MIN + 1)
+ { "max", 7, 3, 0, 1 },
/* Delay slot. */
-#define F_ND (F_FFAKE + 1)
+#define F_ND (F_ATO_MAX + 1)
{ "nd", 0, 1, 5, 0 },
#define F_D (F_ND + 1)
{ "d", 1, 1, 5, 1 },
@@ -1428,9 +1516,26 @@ const struct arc_flag_operand arc_flag_operands[] =
{ "as", 3, 2, 22, 1 },
#define F_ASFAKE (F_AS22 + 1)
{ "as", 0, 0, 0, 1 },
+/* address writebacks for 128-bit loads.
+ ,---.---.----------.
+ | X | D | mnemonic |
+ |---+---+----------|
+ | 0 | 0 | none |
+ | 0 | 1 | as |
+ | 1 | 0 | a/aw |
+ | 1 | 1 | ab |
+ `---^---^----------' */
+#define F_AA128 (F_ASFAKE + 1)
+ { "a", 2, 2, 15, 0 },
+#define F_AA128W (F_AA128 + 1)
+ { "aw", 2, 2, 15, 1 },
+#define F_AA128B (F_AA128W + 1)
+ { "ab", 3, 2, 15, 1 },
+#define F_AA128S (F_AA128B + 1)
+ { "as", 1, 2, 15, 1 },
/* Cache bypass. */
-#define F_DI5 (F_ASFAKE + 1)
+#define F_DI5 (F_AA128S + 1)
{ "di", 1, 1, 5, 1 },
#define F_DI11 (F_DI5 + 1)
{ "di", 1, 1, 11, 1 },
@@ -1452,9 +1557,13 @@ const struct arc_flag_operand arc_flag_operands[] =
{ "h", 2, 2, 17, 1 },
#define F_SIZED (F_H17 + 1)
{ "dd", 8, 0, 0, 0 }, /* Fake. */
+#define F_SIZEL (F_SIZED + 1)
+ { "dl", 8, 0, 0, 0 }, /* Fake. */
+#define F_SIZEW (F_SIZEL + 1)
+ { "xx", 4, 0, 0, 0 }, /* Fake. */
/* Fake Flags. */
-#define F_NE (F_SIZED + 1)
+#define F_NE (F_SIZEW + 1)
{ "ne", 0, 0, 0, 1 },
/* ARC NPS400 Support: See comment near head of file. */
@@ -1582,52 +1691,58 @@ const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
const struct arc_flag_class arc_flag_classes[] =
{
#define C_EMPTY 0
- { F_CLASS_NONE, { F_NULL } },
+ { F_CLASS_NONE, { F_NULL }, 0, 0 },
#define C_CC_EQ (C_EMPTY + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL}, 0, 0 },
#define C_CC_GE (C_CC_EQ + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL}, 0, 0 },
#define C_CC_GT (C_CC_GE + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL}, 0, 0},
#define C_CC_HI (C_CC_GT + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL}, 0, 0},
#define C_CC_HS (C_CC_HI + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL}, 0, 0},
#define C_CC_LE (C_CC_HS + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL}, 0, 0},
#define C_CC_LO (C_CC_LE + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL}, 0, 0},
#define C_CC_LS (C_CC_LO + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL}, 0, 0},
#define C_CC_LT (C_CC_LS + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL}, 0, 0},
#define C_CC_NE (C_CC_LT + 1)
- {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL}, 0, 0},
#define C_AA_AB (C_CC_NE + 1)
- {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL}, 0, 0},
#define C_AA_AW (C_AA_AB + 1)
- {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL}, 0, 0},
#define C_ZZ_D (C_AA_AW + 1)
- {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL}, 0, 0},
+
+#define C_ZZ_L (C_ZZ_D + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEL, F_NULL}, 0, 0},
-#define C_ZZ_H (C_ZZ_D + 1)
- {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
+#define C_ZZ_W (C_ZZ_L + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEW, F_NULL}, 0, 0},
+
+#define C_ZZ_H (C_ZZ_W + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL}, 0, 0},
#define C_ZZ_B (C_ZZ_H + 1)
- {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL}, 0, 0},
#define C_CC (C_ZZ_B + 1)
{ F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
@@ -1636,153 +1751,197 @@ const struct arc_flag_class arc_flag_classes[] =
F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
- F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } },
+ F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL }, 0, 0},
#define C_AA_ADDR3 (C_CC + 1)
#define C_AA27 (C_CC + 1)
- { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
-#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
-#define C_AA21 (C_AA_ADDR3 + 1)
- { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
-#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
-#define C_AA8 (C_AA_ADDR9 + 1)
- { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
-
-#define C_F (C_AA_ADDR22 + 1)
- { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL }, 0, 0},
+#define C_AS27 (C_AA_ADDR3 + 1)
+ { F_CLASS_OPTIONAL, { F_AS3, F_NULL }, 0, 0},
+#define C_AA_ADDR9 (C_AS27 + 1)
+#define C_AA21 (C_AS27 + 1)
+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL }, 0, 0},
+#define C_AAB21 (C_AA21 + 1)
+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_NULL }, 0, 0},
+#define C_AA_ADDR22 (C_AAB21 + 1)
+#define C_AA8 (C_AAB21 + 1)
+ { F_CLASS_OPTIONAL | F_CLASS_WB,
+ { F_A22, F_AW22, F_AB22, F_AS22, F_NULL }, 0, 0},
+#define C_AAB8 (C_AA8 + 1)
+ { F_CLASS_OPTIONAL | F_CLASS_WB,
+ { F_A22, F_AW22, F_AB22, F_NULL }, 0, 0},
+
+#define C_F (C_AAB8 + 1)
+ { F_CLASS_OPTIONAL, { F_FLAG, F_NULL }, 0, 0},
#define C_FHARD (C_F + 1)
- { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL }, 0, 0},
+#define C_AQ (C_FHARD + 1)
+ { F_CLASS_OPTIONAL, { F_AQ, F_RL, F_NULL }, 0, 0},
+
+#define C_ATOP (C_AQ + 1)
+ { F_CLASS_REQUIRED, {F_ATO_ADD, F_ATO_OR, F_ATO_AND, F_ATO_XOR, F_ATO_MINU,
+ F_ATO_MAXU, F_ATO_MIN, F_ATO_MAX, F_NULL}, 0, 0},
-#define C_T (C_FHARD + 1)
- { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
+#define C_T (C_ATOP + 1)
+ { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL }, 0, 0},
#define C_D (C_T + 1)
- { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL }, 0, 0},
#define C_DNZ_D (C_D + 1)
- { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL }, 0, 0},
#define C_DHARD (C_DNZ_D + 1)
- { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
+ { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL }, 0, 0},
#define C_DI20 (C_DHARD + 1)
- { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_DI11, F_NULL }, 0, 0},
#define C_DI14 (C_DI20 + 1)
- { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_DI14, F_NULL }, 0, 0},
#define C_DI16 (C_DI14 + 1)
- { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_DI15, F_NULL }, 0, 0},
#define C_DI26 (C_DI16 + 1)
- { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_DI5, F_NULL }, 0, 0},
#define C_X25 (C_DI26 + 1)
- { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }, 0, 0},
#define C_X15 (C_X25 + 1)
- { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }, 0, 0},
#define C_XHARD (C_X15 + 1)
#define C_X (C_X15 + 1)
- { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }, 0, 0},
#define C_ZZ13 (C_X + 1)
- { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}, 0, 0},
#define C_ZZ23 (C_ZZ13 + 1)
- { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}, 0, 0},
#define C_ZZ29 (C_ZZ23 + 1)
- { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}, 0, 0},
#define C_AS (C_ZZ29 + 1)
- { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
+#define C_AAHARD13 (C_ZZ29 + 1)
+ { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}, 0, 0},
#define C_NE (C_AS + 1)
- { F_CLASS_REQUIRED, { F_NE, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NE, F_NULL}, 0, 0},
/* ARC NPS400 Support: See comment near head of file. */
#define C_NPS_CL (C_NE + 1)
- { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}, 0, 0},
#define C_NPS_NA (C_NPS_CL + 1)
- { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}, 0, 0},
#define C_NPS_SR (C_NPS_NA + 1)
- { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}, 0, 0},
#define C_NPS_M (C_NPS_SR + 1)
- { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}, 0, 0},
#define C_NPS_F (C_NPS_M + 1)
- { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}, 0, 0},
#define C_NPS_R (C_NPS_F + 1)
- { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}, 0, 0},
#define C_NPS_SCHD_RW (C_NPS_R + 1)
- { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}, 0, 0},
#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
- { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}, 0, 0},
#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
- { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}, 0, 0},
#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
- { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}, 0, 0},
#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
- { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}, 0, 0},
#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
- { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}, 0, 0},
#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
- { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
+ { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}, 0, 0},
#define C_NPS_AR_AL (C_NPS_SX + 1)
- { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}, 0, 0},
#define C_NPS_S (C_NPS_AR_AL + 1)
- { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}, 0, 0},
#define C_NPS_ZNCV (C_NPS_S + 1)
- { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}, 0, 0},
#define C_NPS_P0 (C_NPS_ZNCV + 1)
- { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
+ { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }, 0, 0},
#define C_NPS_P1 (C_NPS_P0 + 1)
- { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
+ { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }, 0, 0},
#define C_NPS_P2 (C_NPS_P1 + 1)
- { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
+ { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }, 0, 0},
#define C_NPS_P3 (C_NPS_P2 + 1)
- { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
+ { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }, 0, 0},
#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
- { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
+ { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }, 0, 0},
#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }, 0, 0},
#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }, 0, 0},
#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }, 0, 0},
#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
- { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
+ { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }, 0, 0},
#define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1)
- { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}, 0, 0},
#define C_NPS_CLSR (C_NPS_CORE + 1)
- { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}, 0, 0},
#define C_NPS_ALL (C_NPS_CLSR + 1)
- { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}, 0, 0},
#define C_NPS_GIC (C_NPS_ALL + 1)
- { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}, 0, 0},
#define C_NPS_RSPI_GIC (C_NPS_GIC + 1)
- { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}, 0, 0},
+
+ /* Conditinal Flags used by floating point conditional move
+ instruction. */
+#define C_FPCC (C_NPS_RSPI_GIC + 1)
+ { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
+ { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
+ F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
+ F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
+ F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
+ F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL },
+ insert_fs2, extract_fs2},
+
+/* The address writeback for 128-bit loads. */
+#define C_AA_128 (C_FPCC + 1)
+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_AA128, F_AA128W, F_AA128B, F_AA128S, F_NULL }, 0, 0},
+
+ /* The address scaling for 128-bit loads. */
+#define C_AS_128 (C_AA_128 + 1)
+ { F_CLASS_OPTIONAL, { F_AA128S, F_NULL }, 0, 0},
+
+/* The scattered version of address writeback for 128-bit loads. */
+#define C_AA_128S (C_AS_128 + 1)
+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_AA128, F_AA128W, F_AA128B, F_AA128S, F_NULL }, insert_qq, extract_qq},
+
+/* The scattered version of address sacling for 128-bit loads. */
+#define C_AS_128S (C_AA_128S + 1)
+ { F_CLASS_OPTIONAL, { F_AA128S, F_NULL }, insert_qq, extract_qq},
+
};
const unsigned char flags_none[] = { 0 };
@@ -1815,7 +1974,10 @@ const struct arc_operand arc_operands[] =
{ 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
#define RB_CHK (RB + 1)
{ 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
-#define RC (RB_CHK + 1)
+#define RBB_S (RB_CHK + 1)
+ { 6, 12, 0, ARC_OPERAND_IR, insert_rbb, extract_rbb },
+#define RC (RBB_S + 1)
+#define RC_CHK (RBB_S + 1)
{ 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
#define RBdup (RC + 1)
{ 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
@@ -1897,15 +2059,26 @@ const struct arc_operand arc_operands[] =
#define LIMM (ILINK2 + 1)
#define LIMM_S (ILINK2 + 1)
{ 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
-#define LIMMdup (LIMM + 1)
+#define LO32 (LIMM + 1)
+ { 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
+#define HI32 (LO32 + 1)
+ { 32, 0, BFD_RELOC_ARC_HI32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
+#define XIMM_S (HI32 + 1)
+#define XIMM (HI32 + 1)
+ { 32, 0, BFD_RELOC_ARC_LO32_ME, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED,
+ insert_limm, 0 },
+#define LIMMdup (XIMM + 1)
{ 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
+#define XIMMdup (LIMMdup + 1)
+ { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE | ARC_OPERAND_SIGNED,
+ insert_limm, 0 },
/* Special operands. */
-#define ZA (LIMMdup + 1)
-#define ZB (LIMMdup + 1)
-#define ZA_S (LIMMdup + 1)
-#define ZB_S (LIMMdup + 1)
-#define ZC_S (LIMMdup + 1)
+#define ZA (XIMMdup + 1)
+#define ZB (XIMMdup + 1)
+#define ZA_S (XIMMdup + 1)
+#define ZB_S (XIMMdup + 1)
+#define ZC_S (XIMMdup + 1)
{ 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
#define RRANGE_EL (ZA + 1)
@@ -1975,8 +2148,13 @@ const struct arc_operand arc_operands[] =
| ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
+#define UIMM9_A32_11_S (UIMM7_A32_11R_S + 1)
+ {9, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm9_a32_11_s,
+ extract_uimm9_a32_11_s},
+
/* UIMM7_9_S mask = 0000000001111111. */
-#define UIMM7_9_S (UIMM7_A32_11R_S + 1)
+#define UIMM7_9_S (UIMM9_A32_11_S + 1)
{7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
/* UIMM3_13_S mask = 0000000000000111. */
@@ -2003,7 +2181,7 @@ const struct arc_operand arc_operands[] =
/* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
#define SIMM9_A16_8 (UIMM5_11_S + 1)
- {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ {9, 0, BFD_RELOC_ARC_S9H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
| ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
extract_simm9_a16_8},
@@ -2025,7 +2203,7 @@ const struct arc_operand arc_operands[] =
/* SIMM10_A16_7_S mask = 0000000111111111. */
#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
- {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ {10, 0, BFD_RELOC_ARC_S10H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
| ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
extract_simm10_a16_7_s},
@@ -2035,7 +2213,7 @@ const struct arc_operand arc_operands[] =
/* SIMM7_A16_10_S mask = 0000000000111111. */
#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
- {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ {7, 0, BFD_RELOC_ARC_S7H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
| ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
extract_simm7_a16_10_s},
@@ -2059,7 +2237,7 @@ const struct arc_operand arc_operands[] =
/* SIMM8_A16_9_S mask = 0000000001111111. */
#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
- {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ {8, 0, BFD_RELOC_ARC_S8H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
| ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
extract_simm8_a16_9_s},
@@ -2077,8 +2255,11 @@ const struct arc_operand arc_operands[] =
#define UIMM10_6_S (UIMM3_23 + 1)
{10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
+#define UIMM10_13_S (UIMM10_6_S+ 1)
+ {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_13_s, extract_uimm10_13_s},
+
/* UIMM6_11_S mask = 0000002200011110. */
-#define UIMM6_11_S (UIMM10_6_S + 1)
+#define UIMM6_11_S (UIMM10_13_S + 1)
{6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
/* SIMM9_8 mask = 00000000111111112000000000000000. */
@@ -2140,7 +2321,7 @@ const struct arc_operand arc_operands[] =
/* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
- {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ {13, 0, BFD_RELOC_ARC_S13H_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
| ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
extract_simm13_a16_20},
@@ -2547,7 +2728,40 @@ const struct arc_operand arc_operands[] =
#define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
{ 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
- insert_nps_proto_size, extract_nps_proto_size }
+ insert_nps_proto_size, extract_nps_proto_size },
+
+ /* ARC64's floating point registers. */
+#define FA (NPS_PROTO_SIZE + 1)
+ { 5, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0 },
+#define FB (FA + 1)
+ { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0 },
+#define FC (FB + 1)
+ { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, insert_fs2, extract_fs2 },
+#define FD (FC + 1)
+ { 5, 19, 0, ARC_OPERAND_IR | ARC_OPERAND_FP, 0, 0},
+
+ /* Double 128 registers, the same like above but only the odd ones
+ allowed. */
+#define FDA (FD + 1)
+ { 5, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0 },
+#define FDB (FDA + 1)
+ { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0 },
+#define FDC (FDB + 1)
+ { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE,
+ insert_fs2, extract_fs2 },
+#define FDD (FDC + 1)
+ { 5, 19, 0, ARC_OPERAND_IR | ARC_OPERAND_FP | ARC_OPERAND_TRUNCATE, 0, 0},
+
+ /* 5bit integer registers used by fp instructions. */
+#define FRD (FDD + 1)
+ { 5, 6, 0, ARC_OPERAND_IR, 0, 0 },
+#define FRB (FRD + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_fs2, extract_fs2 },
+
+ /* 5bit unsigned immediate used by vfext and vfins. */
+#define UIMM5_FP (FRB + 1)
+ {5, 0, 0, ARC_OPERAND_UNSIGNED, insert_fs2, extract_fs2 }
+
};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
@@ -2628,9 +2842,13 @@ const unsigned char arg_32bit_limm[] = { LIMM };
nps extension instructions. */
const struct arc_opcode arc_opcodes[] =
{
+ /* ARC64 needs to be included first as there are new instructions
+ which can be interpreted as ARCv2 insns. */
+#include "arc64-tbl.h"
#include "arc-tbl.h"
#include "arc-nps400-tbl.h"
#include "arc-ext-tbl.h"
+#include "arc64-fp-tbl.h"
{ NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
};
@@ -2781,6 +2999,20 @@ const struct arc_pseudo_insn arc_pseudo_insns[] =
const unsigned arc_num_pseudo_insn =
sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
+/* ARC64 pseudo instructions. */
+const struct arc_pseudo_insn arc64_pseudo_insns[] =
+{
+ { "pushl", "stl", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, -8, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+ { "popl", "ldl", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, 8, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+};
+
+const unsigned arc64_num_pseudo_insn =
+ sizeof (arc64_pseudo_insns) / sizeof (*arc64_pseudo_insns);
+
const struct arc_aux_reg arc_aux_regs[] =
{
#undef DEF
diff --git a/opcodes/arc64-fp-tbl.h b/opcodes/arc64-fp-tbl.h
new file mode 100644
index 00000000000..79673336862
--- /dev/null
+++ b/opcodes/arc64-fp-tbl.h
@@ -0,0 +1,479 @@
+/* ARC instruction defintions.
+ Copyright (C) 2021 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+/* Flags. */
+#define FL_NONE { 0 }
+#define FL_CC { C_FPCC }
+
+/* Arguments. */
+#define ARG_NONE { 0 }
+#define ARG_64FP_3OP { FA, FB, FC, FD }
+#define ARG_128FP_3OP { FDA, FDB, FDC, FDD }
+#define ARG_64FP_2OP { FA, FB, FC }
+#define ARG_64FP_CMP { FB, FC }
+#define ARG_128FP_2OP { FDA, FDB, FDC }
+#define ARG_64FP_1OP { FA, FC }
+#define ARG_64FP_SOP { FA, FB }
+#define ARG_128FP_SOP { FDA, FDB }
+
+#define ARG_64FP_CVI2F { FA, FRB }
+#define ARG_64FP_CVF2I { FRD, FC }
+
+/* Macros to help generating floating point pattern instructions. */
+/* Define FP_TOP */
+#define FIELDS1(word) (word & 0x1F)
+#define FIELDS2(word) (((word & 0x07) << 24) | (((word >> 3) & 0x03) << 12))
+#define FIELDS3(word) ((word & 0x1F) << 19)
+#define FIELDD(word) ((word & 0x1F) << 6)
+#define FIELDTOP(word) (((word & 0x01) << 5) | ((word >> 1) & 0x07) << 16)
+#define FIELDP(word) ((word & 0x03) << 14)
+#define MASK_32BIT(VAL) (0xffffffff & (VAL))
+
+#define INSNFP3OP(TOPF, P) \
+ ((0x1C << 27) | FIELDTOP (TOPF) | FIELDP (P) | (1 << 11))
+#define MINSNFP3OP \
+ (MASK_32BIT (~(FIELDS1 (31) | FIELDS2 (31) | FIELDS3 (31) | FIELDD (31))))
+
+/* Define FP_DOP */
+#define FIELDDOP(ops) ((ops & 0x1f) << 16)
+
+#define INSNFP2OP(DOPF, P) \
+ ((0x1C << 27) | FIELDDOP (DOPF) | FIELDP (P) | (1 << 5))
+#define MINSNFP2OP \
+ (MASK_32BIT (~(FIELDS2 (31) | FIELDS1 (31) | FIELDD (31))))
+
+/* Define FP_CVF2F */
+/* 0x1c | fs2[2:0] | 0 1 1 0 - - | cvtf[1:0] | - - | fs2[4:3] | 0 | fd | 1 | u4 u3 1 0 u0 */
+#define FIELDCVTF(WORD) ((WORD & 0x03) << 16)
+#define FIELDU0(BIT) (BIT & 0x01)
+#define FIELDU1(BIT) (BIT & 0x02)
+#define FIELDU3(BIT) (BIT & 0x08)
+#define FIELDU4(BIT) (BIT & 0x10)
+
+#define FP_CVF2F_MACHINE(CVTF, BIT) \
+ ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | (1 << 2) | FIELDU0(BIT) | FIELDU3(BIT) | FIELDU4(BIT))
+#define MFP_CVF2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_RND */
+#define FP_RND_MACHINE(CVTF, BIT) \
+((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) | (1 << 5) | (0x03 << 1) \
+ | FIELDU3(BIT))
+#define MFP_RND (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_CVF2I */
+#define FP_CVF2I_MACHINE(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | 1 | FIELDU3(BIT) | FIELDU1(BIT))
+#define MFP_CVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FMVVF2I */
+#define FM_VVF2I(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | 1 << 4 | 1)
+#define MFM_VVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_SOP */
+#define FP_SOP_MACHINE(SOPF, P) \
+ ((0x1C << 27) | (0x02 << 21) | FIELDCVTF (SOPF) | FIELDP (P) | (1 << 5))
+#define MFP_SOP_MACHINE (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31))))
+
+/* Define FP_COP */
+#define FP_COP_MACHINE(COPF, P) \
+ ((0x1C << 27) | (0x09 << 19) | FIELDCVTF (COPF) | FIELDP (P) | (1 << 5))
+#define MFP_COP_MACHINE \
+ (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2(31))))
+
+/* Define FP_ZOP */
+#define INSNFPZOP(COPF) \
+ ((0x1C << 27) | (0x07 << 20) | FIELDCVTF (COPF) | (1 << 5))
+
+/* Define FP_VMVI */
+#define INSNFPVMVI(WMVF, P) \
+ ((0x1C << 27) | (0x05 << 20) | FIELDCVTF (WMVF) | FIELDP (P) | (1 << 5))
+#define MINSNFPCOP (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2(31))))
+#define MINSNFPVMVIZ (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31))))
+
+/* Define FP_VMVR */
+#define INSNFPVMVR(WMVF, P) \
+ ((0x1C << 27) | (0x01 << 23) | FIELDCVTF (WMVF) | FIELDP (P) | (1 << 5))
+#define MINSNFPVMVR (MASK_32BIT (~(FIELDS1 (31) | FIELDD (31) | FIELDS2(31))))
+
+/* Define FP_CVI2F */
+#define INSNFPCVI2F(CVTF, BIT) ((0x1C << 27) | (0x07 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | FIELDU3(BIT) | FIELDU1(BIT))
+#define MINSNFPCVI2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FMVI2F */
+#define INSNFMVI2F(CVTF, BIT) ((0x1C << 27) | (0x07 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | (1 << 4))
+#define MINSNFMVI2F (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FMVF2I */
+#define INSNFMVF2I(CVTF, BIT) ((0x1C << 27) | (0x03 << 21) | FIELDCVTF (CVTF) \
+ | (1 << 5) | (1 << 4) | (1))
+#define MINSNFMVF2I (MASK_32BIT (~(FIELDS2 (31) | FIELDD (31))))
+
+/* Define FP_LOAD */
+#define FP_LOAD_ENCODING(SIZE) (0x1C << 27 | ((SIZE & 0x03) << 1))
+#define MSK_FP_LOAD (MASK_32BIT (~(FIELDB (63) | FIELDD (31) | (0x03 << 3) \
+ | (0x1FF << 15))))
+
+#define FP_LSYM_ENCODING(SIZE) (0x1C << 27 | ((SIZE & 0x03) << 1) | FIELDB(62))
+#define MSK_FP_SYM (MASK_32BIT (~(FIELDD (31))))
+
+/* Define FP_STORE */
+#define FP_STORE_ENCODING(SIZE) ((0x1C << 27) | ((SIZE & 0x03) << 1) | (1))
+#define MSK_FP_STORE (MASK_32BIT (~(FIELDB (63) | FIELDD (31) | (0x03 << 3) \
+ | (0x1FF << 15))))
+#define FP_SSYM_ENCODING(SIZE) (0x1C << 27 | ((SIZE & 0x03) << 1) \
+ | FIELDB(62) | (1))
+
+/* FP Load/Store. */
+#define FP_LOAD(NAME,SIZE) \
+ { #NAME, FP_LOAD_ENCODING(SIZE), MSK_FP_LOAD, ARC_OPCODE_ARC64, LOAD, \
+ NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }, \
+ { #NAME, FP_LSYM_ENCODING(SIZE), MSK_FP_SYM, ARC_OPCODE_ARC64, LOAD, \
+ NONE, { FA, BRAKET, LIMM, BRAKETdup }, FL_NONE },
+
+#define FP_STORE(NAME,SIZE) \
+ { #NAME, FP_STORE_ENCODING(SIZE), MSK_FP_STORE, ARC_OPCODE_ARC64, STORE, \
+ NONE, { FA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 } }, \
+ { #NAME, FP_SSYM_ENCODING(SIZE), MSK_FP_SYM, ARC_OPCODE_ARC64, LOAD, \
+ NONE, { FA, BRAKET, LIMM, BRAKETdup }, FL_NONE },
+
+/* Macros used to generate conversion instructions. */
+#define FMVF2I_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, INSNFMVF2I (OPS, BIT), MINSNFMVF2I, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FMVF2I(NAME, OPS, BIT) \
+ FMVF2I_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVF2I)
+
+#define FMVI2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, INSNFMVI2F (OPS, BIT), MINSNFMVI2F, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FMVI2F(NAME, OPS, BIT) \
+ FMVI2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVI2F)
+
+#define FP_RND_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, FP_RND_MACHINE (OPS, BIT), MFP_RND, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_RND(NAME, OPS, BIT) \
+ FP_RND_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_1OP)
+
+#define FP_CVF2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, FP_CVF2F_MACHINE (OPS, BIT), MFP_CVF2F, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_CVF2F(NAME, OPS, BIT) \
+ FP_CVF2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_1OP)
+
+#define FP_CVF2I_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, FP_CVF2I_MACHINE (OPS, BIT), MFP_CVF2I, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_CVF2I(NAME, OPS, BIT) \
+ FP_CVF2I_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVF2I)
+
+#define FP_CVI2F_INSN(NAME, CPU, CLASS, SCLASS, OPS, BIT, ARG) \
+ { NAME, INSNFPCVI2F (OPS, BIT), MINSNFPCVI2F, CPU, CLASS, \
+ SCLASS, ARG, FL_NONE },
+
+#define FP_CVI2F(NAME, OPS, BIT) \
+ FP_CVI2F_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, OPS, \
+ BIT, ARG_64FP_CVI2F)
+
+/* Macro to generate 1 operand extension instruction. */
+#define FP_SOP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, FP_SOP_MACHINE (OPS, PRC), MFP_SOP_MACHINE, CPU, CLASS, SCLASS, \
+ ARG, FL_NONE },
+
+#define FP_SOP(NAME, OPS, PRECISION) \
+ FP_SOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, SOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_SOP)
+
+#define FP_SOP_D(NAME, OPS, PRECISION) \
+ FP_SOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, SOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_128FP_SOP)
+
+/* Macro to generate 2 operand extension instruction. */
+#define FP_DOP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, INSNFP2OP (OPS, PRC), MINSNFP2OP, CPU, CLASS, SCLASS, \
+ ARG, FL_NONE },
+
+#define FP_DOP(NAME, OPS, PRECISION) \
+ FP_DOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_2OP)
+
+#define FP_DOPC_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, INSNFP2OP (OPS, PRC) | FIELDD (0), MINSNFP2OP, CPU, \
+ CLASS, SCLASS, ARG, FL_NONE },
+
+#define FP_DOP_C(NAME, OPS, PRECISION) \
+ FP_DOPC_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_CMP)
+
+#define FP_DOP_D(NAME, OPS, PRECISION) \
+ FP_DOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, DOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_128FP_2OP)
+
+/* Macro to generate 3 operand generic instruction. */
+#define FP_TOP_INSN(NAME, CPU, CLASS, SCLASS, TOPF, P, ARG) \
+ { NAME, INSNFP3OP (TOPF, P), MINSNFP3OP, CPU, CLASS, SCLASS, \
+ ARG, FL_NONE },
+
+#define FP_TOP(NAME, OPS, PRECISION) \
+ FP_TOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, TOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_3OP)
+
+#define FP_TOP_D(NAME, OPS, PRECISION) \
+ FP_TOP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, TOPF_ ## OPS, \
+ P_ ## PRECISION, ARG_128FP_3OP)
+
+/* Conditional mov instructions. */
+#define FP_COP_INSN(NAME, CPU, CLASS, SCLASS, OPS, PRC, ARG) \
+ { NAME, FP_COP_MACHINE (OPS, PRC), MFP_COP_MACHINE, CPU, CLASS, SCLASS, \
+ ARG, FL_CC },
+
+#define FP_COP(NAME, OPS, PRECISION) \
+ FP_COP_INSN (#NAME, ARC_OPCODE_ARC64, FLOAT, NONE, COPF_ ## OPS, \
+ P_ ## PRECISION, ARG_64FP_SOP)
+
+#define FP_EXT(NAME, PRECISION) \
+ {#NAME, INSNFPVMVI (0x00, P_ ## PRECISION), MINSNFPCOP, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, UIMM5_FP, \
+ BRAKETdup }, FL_NONE }, \
+ {#NAME, INSNFPVMVR (0x00, P_ ## PRECISION), MINSNFPVMVR, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB, BRAKET, FRB, BRAKETdup}, \
+ FL_NONE },
+
+#define FP_INS(NAME, PRECISION) \
+ {#NAME, INSNFPVMVI (0x01, P_ ## PRECISION), MINSNFPCOP, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, UIMM5_FP, BRAKETdup, \
+ FB }, FL_NONE }, \
+ {#NAME, INSNFPVMVR (0x01, P_ ## PRECISION), MINSNFPVMVR, \
+ ARC_OPCODE_ARC64, FLOAT, NONE, { FA, BRAKET, FRB, BRAKETdup, \
+ FB }, FL_NONE },
+
+#define FP_REP(NAME, PRECISION) \
+ {#NAME, INSNFPVMVI (0x02, P_ ## PRECISION) | FIELDS2 (0x00), \
+ MINSNFPVMVIZ, ARC_OPCODE_ARC64, FLOAT, NONE, { FA, FB }, FL_NONE },
+
+FP_TOP (fhmadd , FMADD , HALF)
+FP_TOP (fhmsub , FMSUB , HALF)
+FP_TOP (fhnmadd, FNMADD, HALF)
+FP_TOP (fhnmsub, FNMSUB, HALF)
+
+FP_TOP (fsmadd , FMADD , SINGLE)
+FP_TOP (fsmsub , FMSUB , SINGLE)
+FP_TOP (fsnmadd, FNMADD, SINGLE)
+FP_TOP (fsnmsub, FNMSUB, SINGLE)
+
+FP_TOP (fdmadd , FMADD , DOUBLE)
+FP_TOP (fdmsub , FMSUB , DOUBLE)
+FP_TOP (fdnmadd, FNMADD, DOUBLE)
+FP_TOP (fdnmsub, FNMSUB, DOUBLE)
+
+
+/* Vectors*/
+FP_TOP (vfhmadd , VFMADD , HALF)
+FP_TOP (vfhmsub , VFMSUB , HALF)
+FP_TOP (vfhnmadd, VFNMADD, HALF)
+FP_TOP (vfhnmsub, VFNMSUB, HALF)
+FP_TOP (vfhmadds , VFMADDS , HALF)
+FP_TOP (vfhmsubs , VFMSUBS , HALF)
+FP_TOP (vfhnmadds, VFNMADDS, HALF)
+FP_TOP (vfhnmsubs, VFNMSUBS, HALF)
+
+FP_TOP (vfsmadd , VFMADD , SINGLE)
+FP_TOP (vfsmsub , VFMSUB , SINGLE)
+FP_TOP (vfsnmadd, VFNMADD, SINGLE)
+FP_TOP (vfsnmsub, VFNMSUB, SINGLE)
+FP_TOP (vfsmadds , VFMADDS , SINGLE)
+FP_TOP (vfsmsubs , VFMSUBS , SINGLE)
+FP_TOP (vfsnmadds, VFNMADDS, SINGLE)
+FP_TOP (vfsnmsubs, VFNMSUBS, SINGLE)
+
+FP_TOP_D (vfdmadd , VFMADD , DOUBLE)
+FP_TOP_D (vfdmsub , VFMSUB , DOUBLE)
+FP_TOP_D (vfdnmadd, VFNMADD, DOUBLE)
+FP_TOP_D (vfdnmsub, VFNMSUB, DOUBLE)
+FP_TOP_D (vfdmadds , VFMADDS , DOUBLE)
+FP_TOP_D (vfdmsubs , VFMSUBS , DOUBLE)
+FP_TOP_D (vfdnmadds, VFNMADDS, DOUBLE)
+FP_TOP_D (vfdnmsubs, VFNMSUBS, DOUBLE)
+
+/* 2OPS */
+FP_DOP (fhadd , FADD , HALF)
+FP_DOP (fhsub , FSUB , HALF)
+FP_DOP (fhmul , FMUL , HALF)
+FP_DOP (fhdiv , FDIV , HALF)
+FP_DOP (fhmin , FMIN , HALF)
+FP_DOP (fhmax , FMAX , HALF)
+FP_DOP (fhsgnj , FSGNJ , HALF)
+FP_DOP (fhsgnjn, FSGNJN, HALF)
+FP_DOP (fhsgnjx, FSGNJX, HALF)
+
+FP_DOP (fsadd , FADD , SINGLE)
+FP_DOP (fssub , FSUB , SINGLE)
+FP_DOP (fsmul , FMUL , SINGLE)
+FP_DOP (fsdiv , FDIV , SINGLE)
+FP_DOP (fsmin , FMIN , SINGLE)
+FP_DOP (fsmax , FMAX , SINGLE)
+FP_DOP (fssgnj , FSGNJ , SINGLE)
+FP_DOP (fssgnjn, FSGNJN, SINGLE)
+FP_DOP (fssgnjx, FSGNJX, SINGLE)
+
+FP_DOP (fdadd , FADD , DOUBLE)
+FP_DOP (fdsub , FSUB , DOUBLE)
+FP_DOP (fdmul , FMUL , DOUBLE)
+FP_DOP (fddiv , FDIV , DOUBLE)
+FP_DOP (fdmin , FMIN , DOUBLE)
+FP_DOP (fdmax , FMAX , DOUBLE)
+FP_DOP (fdsgnj , FSGNJ , DOUBLE)
+FP_DOP (fdsgnjn, FSGNJN, DOUBLE)
+FP_DOP (fdsgnjx, FSGNJX, DOUBLE)
+
+FP_DOP_C (fhcmp , FCMP , HALF)
+FP_DOP_C (fhcmpf, FCMPF, HALF)
+FP_DOP_C (fscmp , FCMP , SINGLE)
+FP_DOP_C (fscmpf, FCMPF, SINGLE)
+FP_DOP_C (fdcmp , FCMP , DOUBLE)
+FP_DOP_C (fdcmpf, FCMPF, DOUBLE)
+
+/* Vectors */
+FP_DOP (vfhadd , VFADD , HALF)
+FP_DOP (vfhsub , VFSUB , HALF)
+FP_DOP (vfhmul , VFMUL , HALF)
+FP_DOP (vfhdiv , VFDIV , HALF)
+FP_DOP (vfhadds, VFADDS, HALF)
+FP_DOP (vfhsubs, VFSUBS, HALF)
+FP_DOP (vfhmuls, VFMULS, HALF)
+FP_DOP (vfhdivs, VFDIVS, HALF)
+
+FP_DOP (vfsadd , VFADD , SINGLE)
+FP_DOP (vfssub , VFSUB , SINGLE)
+FP_DOP (vfsmul , VFMUL , SINGLE)
+FP_DOP (vfsdiv , VFDIV , SINGLE)
+FP_DOP (vfsadds, VFADDS, SINGLE)
+FP_DOP (vfssubs, VFSUBS, SINGLE)
+FP_DOP (vfsmuls, VFMULS, SINGLE)
+FP_DOP (vfsdivs, VFDIVS, SINGLE)
+
+FP_DOP_D (vfdadd , VFADD , DOUBLE)
+FP_DOP_D (vfdsub , VFSUB , DOUBLE)
+FP_DOP_D (vfdmul , VFMUL , DOUBLE)
+FP_DOP_D (vfddiv , VFDIV , DOUBLE)
+FP_DOP_D (vfdadds, VFADDS, DOUBLE)
+FP_DOP_D (vfdsubs, VFSUBS, DOUBLE)
+FP_DOP_D (vfdmuls, VFMULS, DOUBLE)
+FP_DOP_D (vfddivs, VFDIVS, DOUBLE)
+
+FP_SOP (fhsqrt, FSQRT, HALF)
+FP_SOP (fssqrt, FSQRT, SINGLE)
+FP_SOP (fdsqrt, FSQRT, DOUBLE)
+FP_SOP (vfhsqrt, VFSQRT, HALF)
+FP_SOP (vfssqrt, VFSQRT, SINGLE)
+FP_SOP_D (vfdsqrt, VFSQRT,DOUBLE)
+
+FP_COP (fhmov, FMOV, HALF)
+FP_COP (fsmov, FMOV, SINGLE)
+FP_COP (fdmov, FMOV, DOUBLE)
+FP_COP (vfhmov, VFMOV, HALF)
+FP_COP (vfsmov, VFMOV, SINGLE)
+FP_COP (vfdmov, VFMOV, DOUBLE)
+
+FP_CVI2F (fuint2s, FUINT2S, 0x00)
+FP_CVI2F (fuint2d, FUINT2D, 0x00)
+FP_CVI2F (ful2s, FUL2S, 0x00)
+FP_CVI2F (ful2d, FUL2D, 0x00)
+
+FP_CVF2I (fs2uint, FS2UINT, 0x01)
+FP_CVF2I (fs2ul, FS2UL, 0x01)
+FP_CVF2I (fd2uint, FD2UINT, 0x01)
+FP_CVF2I (fd2ul, FD2UL, 0x01)
+
+FP_CVI2F (fint2s, FINT2S, 0x02)
+FP_CVI2F (fint2d, FINT2D, 0x02)
+FP_CVI2F (fl2s, FL2S, 0x02)
+FP_CVI2F (fl2d, FL2D, 0x02)
+
+FP_CVF2I (fs2int, FS2INT, 0x03)
+FP_CVF2I (fs2l, FS2L, 0x03)
+FP_CVF2I (fd2int, FD2INT, 0x03)
+FP_CVF2I (fd2l, FD2L, 0x03)
+
+FP_CVF2F (fs2d, FS2D, 0x04)
+FP_CVF2F (fd2s, FD2S, 0x04)
+
+FP_RND (fsrnd, FSRND, 0x06)
+FP_RND (fdrnd, FDRND, 0x06)
+
+FP_CVF2I (fs2uint_rz, F2UINT_RZ, 0x09)
+FP_CVF2I (fs2ul_rz, FS2UL_RZ, 0x09)
+FP_CVF2I (fd2uint_rz, FD2UINT_RZ, 0x09)
+FP_CVF2I (fd2ul_rz, FD2UL_RZ, 0x09)
+
+FP_CVF2I (fs2int_rz, FSINT_RZ, 0x0B)
+FP_CVF2I (fs2l_rz, FS2L_RZ, 0x0B)
+FP_CVF2I (fd2int_rz, FD2INT_RZ, 0x0B)
+FP_CVF2I (fd2l_rz, FD2L_RZ, 0x0B)
+
+FP_RND (fsrnd_rz, FSRND_RZ, 0x0E)
+FP_RND (fdrnd_rz, FDRND_RZ, 0x0E)
+
+FMVI2F (fmvi2s, FMVI2S, 0x10)
+FMVI2F (fmvl2d, FMVL2D, 0x10)
+
+FMVF2I (fmvs2i, FMVS2I, 0x11)
+FMVF2I (fmvd2l, FMVD2L, 0x11)
+
+FP_CVF2F (fs2h, FS2H, 0x14)
+FP_CVF2F (fh2s, FH2S, 0x15)
+FP_CVF2F (fs2h_rz, FS2H_RZ, 0x1C)
+
+FP_LOAD (fld16, 0x02)
+FP_LOAD (fld32, 0x00)
+FP_LOAD (fld64, 0x01)
+FP_LOAD (fld128, 0x03)
+
+FP_STORE (fst16, 0x02)
+FP_STORE (fst32, 0x00)
+FP_STORE (fst64, 0x01)
+FP_STORE (fst128, 0x03)
+
+FP_EXT (vfhext, HALF)
+FP_EXT (vfsext, SINGLE)
+FP_EXT (vfdext, DOUBLE)
+
+FP_INS (vfhins, HALF)
+FP_INS (vfsins, SINGLE)
+FP_INS (vfdins, DOUBLE)
+
+FP_REP (vfhrep, HALF)
+FP_REP (vfsrep, SINGLE)
+FP_REP (vfdrep, DOUBLE)
diff --git a/opcodes/arc64-tbl.h b/opcodes/arc64-tbl.h
new file mode 100644
index 00000000000..fd7377988cd
--- /dev/null
+++ b/opcodes/arc64-tbl.h
@@ -0,0 +1,18828 @@
+
+/* abs<.f> b,c 00100bbb00101111FBBBCCCCCC001001. */
+{ "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* abs<.f> 0,c 0010011000101111F111CCCCCC001001. */
+{ "abs", 0x262F7009, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* abs<.f> b,u6 00100bbb01101111FBBBuuuuuu001001. */
+{ "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* abs<.f> 0,u6 0010011001101111F111uuuuuu001001. */
+{ "abs", 0x266F7009, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* abs<.f> b,limm 00100bbb00101111FBBB111110001001. */
+{ "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* abs<.f> 0,limm 0010011000101111F111111110001001. */
+{ "abs", 0x262F7F89, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* absl<.f> RB,RC 01011bbb00101111FBBBcccccc001001. */
+{ "absl", 0x582F0009, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* absl<.f> 0,RC 0101111000101111F111cccccc001001. */
+{ "absl", 0x5E2F7009, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* absl<.f> RB,u6 01011bbb01101111FBBBuuuuuu001001. */
+{ "absl", 0x586F0009, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* absl<.f> 0,u6 0101111001101111F111uuuuuu001001. */
+{ "absl", 0x5E6F7009, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* absl<.f> RB,ximm 01011bbb00101111FBBB111100001001. */
+{ "absl", 0x582F0F09, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* absl<.f> 0,ximm 0101111000101111F111111100001001. */
+{ "absl", 0x5E2F7F09, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* absl<.f> RB,limm 01011bbb00101111FBBB111110001001. */
+{ "absl", 0x582F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* absl<.f> 0,limm 0101111000101111F111111110001001. */
+{ "absl", 0x5E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* abss<.f> b,c 00101bbb00101111FBBBCCCCCC000101. */
+{ "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* abss<.f> 0,c 0010111000101111F111CCCCCC000101. */
+{ "abss", 0x2E2F7005, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* abss<.f> b,u6 00101bbb01101111FBBBuuuuuu000101. */
+{ "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* abss<.f> 0,u6 0010111001101111F111uuuuuu000101. */
+{ "abss", 0x2E6F7005, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* abss<.f> b,limm 00101bbb00101111FBBB111110000101. */
+{ "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* abss<.f> 0,limm 0010111000101111F111111110000101. */
+{ "abss", 0x2E2F7F85, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* abssh<.f> b,c 00101bbb00101111FBBBCCCCCC000100. */
+{ "abssh", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { C_F }},
+
+/* abssh<.f> 0,c 0010111000101111F111CCCCCC000100. */
+{ "abssh", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* abssh<.f> b,u6 00101bbb01101111FBBBuuuuuu000100. */
+{ "abssh", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { C_F }},
+
+/* abssh<.f> 0,u6 0010111001101111F111uuuuuu000100. */
+{ "abssh", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* abssh<.f> b,limm 00101bbb00101111FBBB111110000100. */
+{ "abssh", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { C_F }},
+
+/* abssh<.f> 0,limm 0010111000101111F111111110000100. */
+{ "abssh", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* abs_s b,c 01111bbbccc10001. */
+{ "abs_s", 0x00007811, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* adc<.f> a,b,c 00100bbb00000001FBBBCCCCCCAAAAAA. */
+{ "adc", 0x20010000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* adc<.f> 0,b,c 00100bbb00000001FBBBCCCCCC111110. */
+{ "adc", 0x2001003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* adc<.f><.cc> b,b,c 00100bbb11000001FBBBCCCCCC0QQQQQ. */
+{ "adc", 0x20C10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* adc<.f> a,b,u6 00100bbb01000001FBBBuuuuuuAAAAAA. */
+{ "adc", 0x20410000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* adc<.f> 0,b,u6 00100bbb01000001FBBBuuuuuu111110. */
+{ "adc", 0x2041003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* adc<.f><.cc> b,b,u6 00100bbb11000001FBBBuuuuuu1QQQQQ. */
+{ "adc", 0x20C10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* adc<.f> b,b,s12 00100bbb10000001FBBBssssssSSSSSS. */
+{ "adc", 0x20810000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* adc<.f> a,limm,c 0010011000000001F111CCCCCCAAAAAA. */
+{ "adc", 0x26017000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* adc<.f> a,b,limm 00100bbb00000001FBBB111110AAAAAA. */
+{ "adc", 0x20010F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* adc<.f> 0,limm,c 0010011000000001F111CCCCCC111110. */
+{ "adc", 0x2601703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* adc<.f> 0,b,limm 00100bbb00000001FBBB111110111110. */
+{ "adc", 0x20010FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* adc<.f><.cc> b,b,limm 00100bbb11000001FBBB1111100QQQQQ. */
+{ "adc", 0x20C10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* adc<.f><.cc> 0,limm,c 0010011011000001F111CCCCCC0QQQQQ. */
+{ "adc", 0x26C17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* adc<.f> a,limm,u6 0010011001000001F111uuuuuuAAAAAA. */
+{ "adc", 0x26417000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adc<.f> 0,limm,u6 0010011001000001F111uuuuuu111110. */
+{ "adc", 0x2641703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adc<.f><.cc> 0,limm,u6 0010011011000001F111uuuuuu1QQQQQ. */
+{ "adc", 0x26C17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* adc<.f> 0,limm,s12 0010011010000001F111ssssssSSSSSS. */
+{ "adc", 0x26817000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* adc<.f> a,limm,limm 0010011000000001F111111110AAAAAA. */
+{ "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* adc<.f> 0,limm,limm 0010011000000001F111111110111110. */
+{ "adc", 0x26017FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* adc<.f><.cc> 0,limm,limm 0010011011000001F1111111100QQQQQ. */
+{ "adc", 0x26C17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* adcl<.f> RA,RB,RC 01011bbb00000001FBBBccccccaaaaaa. */
+{ "adcl", 0x58010000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* adcl<.f> 0,RB,RC 01011bbb00000001FBBBcccccc111110. */
+{ "adcl", 0x5801003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* adcl<.f><.cc> RB,RB,RC 01011bbb11000001FBBBcccccc0QQQQQ. */
+{ "adcl", 0x58C10000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* adcl<.f> RA,RB,u6 01011bbb01000001FBBBuuuuuuaaaaaa. */
+{ "adcl", 0x58410000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* adcl<.f> 0,RB,u6 01011bbb01000001FBBBuuuuuu111110. */
+{ "adcl", 0x5841003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* adcl<.f><.cc> RB,RB,u6 01011bbb11000001FBBBuuuuuu1QQQQQ. */
+{ "adcl", 0x58C10020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* adcl<.f> RB,RB,s12 01011bbb10000001FBBBssssssSSSSSS. */
+{ "adcl", 0x58810000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* adcl<.f> RA,ximm,RC 0101110000000001F111ccccccaaaaaa. */
+{ "adcl", 0x5C017000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* adcl<.f> RA,RB,ximm 01011bbb00000001FBBB111100aaaaaa. */
+{ "adcl", 0x58010F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* adcl<.f> 0,ximm,RC 0101110000000001F111cccccc111110. */
+{ "adcl", 0x5C01703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* adcl<.f> 0,RB,ximm 01011bbb00000001FBBB111100111110. */
+{ "adcl", 0x58010F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* adcl<.f><.cc> 0,ximm,RC 0101110011000001F111cccccc0QQQQQ. */
+{ "adcl", 0x5CC17000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* adcl<.f><.cc> RB,RB,ximm 01011bbb11000001FBBB1111000QQQQQ. */
+{ "adcl", 0x58C10F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* adcl<.f> RA,ximm,u6 0101110001000001F111uuuuuuaaaaaa. */
+{ "adcl", 0x5C417000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* adcl<.f> 0,ximm,u6 0101110001000001F111uuuuuu111110. */
+{ "adcl", 0x5C41703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* adcl<.f><.cc> 0,ximm,u6 0101110011000001F111uuuuuu1QQQQQ. */
+{ "adcl", 0x5CC17020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* adcl<.f> RA,limm,RC 0101111000000001F111ccccccaaaaaa. */
+{ "adcl", 0x5E017000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* adcl<.f> RA,RB,limm 01011bbb00000001FBBB111110aaaaaa. */
+{ "adcl", 0x58010F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* adcl<.f> 0,limm,RC 0101111000000001F111cccccc111110. */
+{ "adcl", 0x5E01703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* adcl<.f> 0,RB,limm 01011bbb00000001FBBB111110111110. */
+{ "adcl", 0x58010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* adcl<.f><.cc> 0,limm,RC 0101111011000001F111cccccc0QQQQQ. */
+{ "adcl", 0x5EC17000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* adcl<.f><.cc> RB,RB,limm 01011bbb11000001FBBB1111100QQQQQ. */
+{ "adcl", 0x58C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* adcl<.f> RA,limm,u6 0101111001000001F111uuuuuuaaaaaa. */
+{ "adcl", 0x5E417000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adcl<.f> 0,limm,u6 0101111001000001F111uuuuuu111110. */
+{ "adcl", 0x5E41703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adcl<.f><.cc> 0,limm,u6 0101111011000001F111uuuuuu1QQQQQ. */
+{ "adcl", 0x5EC17020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* adcl<.f> 0,ximm,s12 0101110010000001F111ssssssSSSSSS. */
+{ "adcl", 0x5C817000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* adcl<.f> 0,limm,s12 0101111010000001F111ssssssSSSSSS. */
+{ "adcl", 0x5E817000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* adcl<.f> RA,ximm,ximm 0101110000000001F111111100aaaaaa. */
+{ "adcl", 0x5C017F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* adcl<.f> 0,ximm,ximm 0101110000000001F111111100111110. */
+{ "adcl", 0x5C017F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* adcl<.f><.cc> 0,ximm,ximm 0101110011000001F1111111000QQQQQ. */
+{ "adcl", 0x5CC17F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* adcl<.f> RA,limm,limm 0101111000000001F111111110aaaaaa. */
+{ "adcl", 0x5E017F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* adcl<.f> 0,limm,limm 0101111000000001F111111110111110. */
+{ "adcl", 0x5E017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* adcl<.f><.cc> 0,limm,limm 0101111011000001F1111111100QQQQQ. */
+{ "adcl", 0x5EC17F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* adcs<.f> a,b,c 00101bbb00100110FBBBCCCCCCAAAAAA. */
+{ "adcs", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* adcs<.f> 0,b,c 00101bbb00100110FBBBCCCCCC111110. */
+{ "adcs", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* adcs<.f><.cc> b,b,c 00101bbb11100110FBBBCCCCCC0QQQQQ. */
+{ "adcs", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* adcs<.f> a,b,u6 00101bbb01100110FBBBuuuuuuAAAAAA. */
+{ "adcs", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* adcs<.f> 0,b,u6 00101bbb01100110FBBBuuuuuu111110. */
+{ "adcs", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* adcs<.f><.cc> b,b,u6 00101bbb11100110FBBBuuuuuu1QQQQQ. */
+{ "adcs", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* adcs<.f> b,b,s12 00101bbb10100110FBBBssssssSSSSSS. */
+{ "adcs", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* adcs<.f> a,limm,c 0010111000100110F111CCCCCCAAAAAA. */
+{ "adcs", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* adcs<.f> a,b,limm 00101bbb00100110FBBB111110AAAAAA. */
+{ "adcs", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* adcs<.f> 0,limm,c 0010111001100110F111CCCCCC111110. */
+{ "adcs", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* adcs<.f> 0,b,limm 00101bbb00100110FBBB111110111110. */
+{ "adcs", 0x28260FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* adcs<.f><.cc> b,b,limm 00101bbb11100110FBBB1111100QQQQQ. */
+{ "adcs", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* adcs<.f><.cc> 0,limm,c 0010111011100110F111CCCCCC0QQQQQ. */
+{ "adcs", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* adcs<.f> a,limm,u6 0010111001100110F111uuuuuuAAAAAA. */
+{ "adcs", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adcs<.f> 0,limm,u6 0010111001100110F111uuuuuu111110. */
+{ "adcs", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adcs<.f><.cc> 0,limm,u6 0010111011100110F111uuuuuu1QQQQQ. */
+{ "adcs", 0x2EE67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* adcs<.f> 0,limm,s12 0010111010100110F111ssssssSSSSSS. */
+{ "adcs", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* adcs<.f> a,limm,limm 0010111000100110F111111110AAAAAA. */
+{ "adcs", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* adcs<.f> 0,limm,limm 0010111000100110F111111110111110. */
+{ "adcs", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* adcs<.f><.cc> 0,limm,limm 0010111011100110F1111111100QQQQQ. */
+{ "adcs", 0x2EE67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add<.f> a,b,c 00100bbb00000000FBBBCCCCCCAAAAAA. */
+{ "add", 0x20000000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add<.f> 0,b,c 00100bbb00000000FBBBCCCCCC111110. */
+{ "add", 0x2000003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add<.f><.cc> b,b,c 00100bbb11000000FBBBCCCCCC0QQQQQ. */
+{ "add", 0x20C00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
+{ "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add<.f> 0,b,u6 00100bbb01000000FBBBuuuuuu111110. */
+{ "add", 0x2040003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
+{ "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add<.f> b,b,s12 00100bbb10000000FBBBssssssSSSSSS. */
+{ "add", 0x20800000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add<.f> a,limm,c 0010011000000000F111CCCCCCAAAAAA. */
+{ "add", 0x26007000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
+{ "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add<.f> 0,limm,c 0010011000000000F111CCCCCC111110. */
+{ "add", 0x2600703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add<.f> 0,b,limm 00100bbb00000000FBBB111110111110. */
+{ "add", 0x20000FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
+{ "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add<.f><.cc> 0,limm,c 0010011011000000F111CCCCCC0QQQQQ. */
+{ "add", 0x26C07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add<.f> a,limm,u6 0010011001000000F111uuuuuuAAAAAA. */
+{ "add", 0x26407000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add<.f> 0,limm,u6 0010011001000000F111uuuuuu111110. */
+{ "add", 0x2640703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add<.f><.cc> 0,limm,u6 0010011011000000F111uuuuuu1QQQQQ. */
+{ "add", 0x26C07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add<.f> 0,limm,s12 0010011010000000F111ssssssSSSSSS. */
+{ "add", 0x26807000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add<.f> a,limm,limm 0010011000000000F111111110AAAAAA. */
+{ "add", 0x26007F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add<.f> 0,limm,limm 0010011000000000F111111110111110. */
+{ "add", 0x26007FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add<.f><.cc> 0,limm,limm 0010011011000000F1111111100QQQQQ. */
+{ "add", 0x26C07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add1<.f> a,b,c 00100bbb00010100FBBBCCCCCCAAAAAA. */
+{ "add1", 0x20140000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add1<.f> 0,b,c 00100bbb00010100FBBBCCCCCC111110. */
+{ "add1", 0x2014003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add1<.f><.cc> b,b,c 00100bbb11010100FBBBCCCCCC0QQQQQ. */
+{ "add1", 0x20D40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add1<.f> a,b,u6 00100bbb01010100FBBBuuuuuuAAAAAA. */
+{ "add1", 0x20540000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add1<.f> 0,b,u6 00100bbb01010100FBBBuuuuuu111110. */
+{ "add1", 0x2054003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add1<.f><.cc> b,b,u6 00100bbb11010100FBBBuuuuuu1QQQQQ. */
+{ "add1", 0x20D40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1<.f> b,b,s12 00100bbb10010100FBBBssssssSSSSSS. */
+{ "add1", 0x20940000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add1<.f> a,limm,c 0010011000010100F111CCCCCCAAAAAA. */
+{ "add1", 0x26147000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add1<.f> a,b,limm 00100bbb00010100FBBB111110AAAAAA. */
+{ "add1", 0x20140F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add1<.f> 0,limm,c 0010011000010100F111CCCCCC111110. */
+{ "add1", 0x2614703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add1<.f> 0,b,limm 00100bbb00010100FBBB111110111110. */
+{ "add1", 0x20140FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add1<.f><.cc> b,b,limm 00100bbb11010100FBBB1111100QQQQQ. */
+{ "add1", 0x20D40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add1<.f><.cc> 0,limm,c 0010011011010100F111CCCCCC0QQQQQ. */
+{ "add1", 0x26D47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add1<.f> a,limm,u6 0010011001010100F111uuuuuuAAAAAA. */
+{ "add1", 0x26547000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add1<.f> 0,limm,u6 0010011001010100F111uuuuuu111110. */
+{ "add1", 0x2654703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add1<.f><.cc> 0,limm,u6 0010011011010100F111uuuuuu1QQQQQ. */
+{ "add1", 0x26D47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1<.f> 0,limm,s12 0010011010010100F111ssssssSSSSSS. */
+{ "add1", 0x26947000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add1<.f> a,limm,limm 0010011000010100F111111110AAAAAA. */
+{ "add1", 0x26147F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add1<.f> 0,limm,limm 0010011000010100F111111110111110. */
+{ "add1", 0x26147FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add1<.f><.cc> 0,limm,limm 0010011011010100F1111111100QQQQQ. */
+{ "add1", 0x26D47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add1l<.f> RA,RB,RC 01011bbb00010100FBBBccccccaaaaaa. */
+{ "add1l", 0x58140000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add1l<.f> 0,RB,RC 01011bbb00010100FBBBcccccc111110. */
+{ "add1l", 0x5814003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add1l<.f><.cc> RB,RB,RC 01011bbb11010100FBBBcccccc0QQQQQ. */
+{ "add1l", 0x58D40000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add1l<.f> RA,RB,u6 01011bbb01010100FBBBuuuuuuaaaaaa. */
+{ "add1l", 0x58540000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add1l<.f> 0,RB,u6 01011bbb01010100FBBBuuuuuu111110. */
+{ "add1l", 0x5854003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add1l<.f><.cc> RB,RB,u6 01011bbb11010100FBBBuuuuuu1QQQQQ. */
+{ "add1l", 0x58D40020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1l<.f> RB,RB,s12 01011bbb10010100FBBBssssssSSSSSS. */
+{ "add1l", 0x58940000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add1l<.f> RA,ximm,RC 0101110000010100F111ccccccaaaaaa. */
+{ "add1l", 0x5C147000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* add1l<.f> RA,RB,ximm 01011bbb00010100FBBB111100aaaaaa. */
+{ "add1l", 0x58140F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* add1l<.f> 0,ximm,RC 0101110000010100F111cccccc111110. */
+{ "add1l", 0x5C14703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* add1l<.f> 0,RB,ximm 01011bbb00010100FBBB111100111110. */
+{ "add1l", 0x58140F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* add1l<.f><.cc> 0,ximm,RC 0101110011010100F111cccccc0QQQQQ. */
+{ "add1l", 0x5CD47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* add1l<.f><.cc> RB,RB,ximm 01011bbb11010100FBBB1111000QQQQQ. */
+{ "add1l", 0x58D40F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* add1l<.f> RA,ximm,u6 0101110001010100F111uuuuuuaaaaaa. */
+{ "add1l", 0x5C547000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add1l<.f> 0,ximm,u6 0101110001010100F111uuuuuu111110. */
+{ "add1l", 0x5C54703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add1l<.f><.cc> 0,ximm,u6 0101110011010100F111uuuuuu1QQQQQ. */
+{ "add1l", 0x5CD47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1l<.f> RA,limm,RC 0101111000010100F111ccccccaaaaaa. */
+{ "add1l", 0x5E147000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add1l<.f> RA,RB,limm 01011bbb00010100FBBB111110aaaaaa. */
+{ "add1l", 0x58140F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add1l<.f> 0,limm,RC 0101111000010100F111cccccc111110. */
+{ "add1l", 0x5E14703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add1l<.f> 0,RB,limm 01011bbb00010100FBBB111110111110. */
+{ "add1l", 0x58140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add1l<.f><.cc> 0,limm,RC 0101111011010100F111cccccc0QQQQQ. */
+{ "add1l", 0x5ED47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add1l<.f><.cc> RB,RB,limm 01011bbb11010100FBBB1111100QQQQQ. */
+{ "add1l", 0x58D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add1l<.f> RA,limm,u6 0101111001010100F111uuuuuuaaaaaa. */
+{ "add1l", 0x5E547000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add1l<.f> 0,limm,u6 0101111001010100F111uuuuuu111110. */
+{ "add1l", 0x5E54703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add1l<.f><.cc> 0,limm,u6 0101111011010100F111uuuuuu1QQQQQ. */
+{ "add1l", 0x5ED47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add1l<.f> 0,ximm,s12 0101110010010100F111ssssssSSSSSS. */
+{ "add1l", 0x5C947000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* add1l<.f> 0,limm,s12 0101111010010100F111ssssssSSSSSS. */
+{ "add1l", 0x5E947000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add1l<.f> RA,ximm,ximm 0101110000010100F111111100aaaaaa. */
+{ "add1l", 0x5C147F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* add1l<.f> 0,ximm,ximm 0101110000010100F111111100111110. */
+{ "add1l", 0x5C147F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* add1l<.f><.cc> 0,ximm,ximm 0101110011010100F1111111000QQQQQ. */
+{ "add1l", 0x5CD47F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* add1l<.f> RA,limm,limm 0101111000010100F111111110aaaaaa. */
+{ "add1l", 0x5E147F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add1l<.f> 0,limm,limm 0101111000010100F111111110111110. */
+{ "add1l", 0x5E147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add1l<.f><.cc> 0,limm,limm 0101111011010100F1111111100QQQQQ. */
+{ "add1l", 0x5ED47F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add1_s b,b,c 01111bbbccc10100. */
+{ "add1_s", 0x00007814, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* add2<.f> a,b,c 00100bbb00010101FBBBCCCCCCAAAAAA. */
+{ "add2", 0x20150000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add2<.f> 0,b,c 00100bbb00010101FBBBCCCCCC111110. */
+{ "add2", 0x2015003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add2<.f><.cc> b,b,c 00100bbb11010101FBBBCCCCCC0QQQQQ. */
+{ "add2", 0x20D50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add2<.f> a,b,u6 00100bbb01010101FBBBuuuuuuAAAAAA. */
+{ "add2", 0x20550000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add2<.f> 0,b,u6 00100bbb01010101FBBBuuuuuu111110. */
+{ "add2", 0x2055003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add2<.f><.cc> b,b,u6 00100bbb11010101FBBBuuuuuu1QQQQQ. */
+{ "add2", 0x20D50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2<.f> b,b,s12 00100bbb10010101FBBBssssssSSSSSS. */
+{ "add2", 0x20950000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add2<.f> a,limm,c 0010011000010101F111CCCCCCAAAAAA. */
+{ "add2", 0x26157000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add2<.f> a,b,limm 00100bbb00010101FBBB111110AAAAAA. */
+{ "add2", 0x20150F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add2<.f> 0,limm,c 0010011000010101F111CCCCCC111110. */
+{ "add2", 0x2615703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add2<.f> 0,b,limm 00100bbb00010101FBBB111110111110. */
+{ "add2", 0x20150FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add2<.f><.cc> b,b,limm 00100bbb11010101FBBB1111100QQQQQ. */
+{ "add2", 0x20D50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add2<.f><.cc> 0,limm,c 0010011011010101F111CCCCCC0QQQQQ. */
+{ "add2", 0x26D57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add2<.f> a,limm,u6 0010011001010101F111uuuuuuAAAAAA. */
+{ "add2", 0x26557000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add2<.f> 0,limm,u6 0010011001010101F111uuuuuu111110. */
+{ "add2", 0x2655703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add2<.f><.cc> 0,limm,u6 0010011011010101F111uuuuuu1QQQQQ. */
+{ "add2", 0x26D57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2<.f> 0,limm,s12 0010011010010101F111ssssssSSSSSS. */
+{ "add2", 0x26957000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add2<.f> a,limm,limm 0010011000010101F111111110AAAAAA. */
+{ "add2", 0x26157F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add2<.f> 0,limm,limm 0010011000010101F111111110111110. */
+{ "add2", 0x26157FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add2<.f><.cc> 0,limm,limm 0010011011010101F1111111100QQQQQ. */
+{ "add2", 0x26D57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add2l<.f> RA,RB,RC 01011bbb00010101FBBBccccccaaaaaa. */
+{ "add2l", 0x58150000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add2l<.f> 0,RB,RC 01011bbb00010101FBBBcccccc111110. */
+{ "add2l", 0x5815003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add2l<.f><.cc> RB,RB,RC 01011bbb11010101FBBBcccccc0QQQQQ. */
+{ "add2l", 0x58D50000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add2l<.f> RA,RB,u6 01011bbb01010101FBBBuuuuuuaaaaaa. */
+{ "add2l", 0x58550000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add2l<.f> 0,RB,u6 01011bbb01010101FBBBuuuuuu111110. */
+{ "add2l", 0x5855003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add2l<.f><.cc> RB,RB,u6 01011bbb11010101FBBBuuuuuu1QQQQQ. */
+{ "add2l", 0x58D50020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2l<.f> RB,RB,s12 01011bbb10010101FBBBssssssSSSSSS. */
+{ "add2l", 0x58950000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add2l<.f> RA,ximm,RC 0101110000010101F111ccccccaaaaaa. */
+{ "add2l", 0x5C157000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* add2l<.f> RA,RB,ximm 01011bbb00010101FBBB111100aaaaaa. */
+{ "add2l", 0x58150F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* add2l<.f> 0,ximm,RC 0101110000010101F111cccccc111110. */
+{ "add2l", 0x5C15703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* add2l<.f> 0,RB,ximm 01011bbb00010101FBBB111100111110. */
+{ "add2l", 0x58150F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* add2l<.f><.cc> 0,ximm,RC 0101110011010101F111cccccc0QQQQQ. */
+{ "add2l", 0x5CD57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* add2l<.f><.cc> RB,RB,ximm 01011bbb11010101FBBB1111000QQQQQ. */
+{ "add2l", 0x58D50F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* add2l<.f> RA,ximm,u6 0101110001010101F111uuuuuuaaaaaa. */
+{ "add2l", 0x5C557000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add2l<.f> 0,ximm,u6 0101110001010101F111uuuuuu111110. */
+{ "add2l", 0x5C55703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add2l<.f><.cc> 0,ximm,u6 0101110011010101F111uuuuuu1QQQQQ. */
+{ "add2l", 0x5CD57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2l<.f> RA,limm,RC 0101111000010101F111ccccccaaaaaa. */
+{ "add2l", 0x5E157000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add2l<.f> RA,RB,limm 01011bbb00010101FBBB111110aaaaaa. */
+{ "add2l", 0x58150F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add2l<.f> 0,limm,RC 0101111000010101F111cccccc111110. */
+{ "add2l", 0x5E15703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add2l<.f> 0,RB,limm 01011bbb00010101FBBB111110111110. */
+{ "add2l", 0x58150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add2l<.f><.cc> 0,limm,RC 0101111011010101F111cccccc0QQQQQ. */
+{ "add2l", 0x5ED57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add2l<.f><.cc> RB,RB,limm 01011bbb11010101FBBB1111100QQQQQ. */
+{ "add2l", 0x58D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add2l<.f> RA,limm,u6 0101111001010101F111uuuuuuaaaaaa. */
+{ "add2l", 0x5E557000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add2l<.f> 0,limm,u6 0101111001010101F111uuuuuu111110. */
+{ "add2l", 0x5E55703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add2l<.f><.cc> 0,limm,u6 0101111011010101F111uuuuuu1QQQQQ. */
+{ "add2l", 0x5ED57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add2l<.f> 0,ximm,s12 0101110010010101F111ssssssSSSSSS. */
+{ "add2l", 0x5C957000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* add2l<.f> 0,limm,s12 0101111010010101F111ssssssSSSSSS. */
+{ "add2l", 0x5E957000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add2l<.f> RA,ximm,ximm 0101110000010101F111111100aaaaaa. */
+{ "add2l", 0x5C157F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* add2l<.f> 0,ximm,ximm 0101110000010101F111111100111110. */
+{ "add2l", 0x5C157F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* add2l<.f><.cc> 0,ximm,ximm 0101110011010101F1111111000QQQQQ. */
+{ "add2l", 0x5CD57F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* add2l<.f> RA,limm,limm 0101111000010101F111111110aaaaaa. */
+{ "add2l", 0x5E157F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add2l<.f> 0,limm,limm 0101111000010101F111111110111110. */
+{ "add2l", 0x5E157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add2l<.f><.cc> 0,limm,limm 0101111011010101F1111111100QQQQQ. */
+{ "add2l", 0x5ED57F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add2_s b,b,c 01111bbbccc10101. */
+{ "add2_s", 0x00007815, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* add3<.f> a,b,c 00100bbb00010110FBBBCCCCCCAAAAAA. */
+{ "add3", 0x20160000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add3<.f> 0,b,c 00100bbb00010110FBBBCCCCCC111110. */
+{ "add3", 0x2016003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add3<.f><.cc> b,b,c 00100bbb11010110FBBBCCCCCC0QQQQQ. */
+{ "add3", 0x20D60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add3<.f> a,b,u6 00100bbb01010110FBBBuuuuuuAAAAAA. */
+{ "add3", 0x20560000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add3<.f> 0,b,u6 00100bbb01010110FBBBuuuuuu111110. */
+{ "add3", 0x2056003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add3<.f><.cc> b,b,u6 00100bbb11010110FBBBuuuuuu1QQQQQ. */
+{ "add3", 0x20D60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3<.f> b,b,s12 00100bbb10010110FBBBssssssSSSSSS. */
+{ "add3", 0x20960000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add3<.f> a,limm,c 0010011000010110F111CCCCCCAAAAAA. */
+{ "add3", 0x26167000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add3<.f> a,b,limm 00100bbb00010110FBBB111110AAAAAA. */
+{ "add3", 0x20160F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add3<.f> 0,limm,c 0010011000010110F111CCCCCC111110. */
+{ "add3", 0x2616703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add3<.f> 0,b,limm 00100bbb00010110FBBB111110111110. */
+{ "add3", 0x20160FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add3<.f><.cc> b,b,limm 00100bbb11010110FBBB1111100QQQQQ. */
+{ "add3", 0x20D60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add3<.f><.cc> 0,limm,c 0010011011010110F111CCCCCC0QQQQQ. */
+{ "add3", 0x26D67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add3<.f> a,limm,u6 0010011001010110F111uuuuuuAAAAAA. */
+{ "add3", 0x26567000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add3<.f> 0,limm,u6 0010011001010110F111uuuuuu111110. */
+{ "add3", 0x2656703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add3<.f><.cc> 0,limm,u6 0010011011010110F111uuuuuu1QQQQQ. */
+{ "add3", 0x26D67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3<.f> 0,limm,s12 0010011010010110F111ssssssSSSSSS. */
+{ "add3", 0x26967000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add3<.f> a,limm,limm 0010011000010110F111111110AAAAAA. */
+{ "add3", 0x26167F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add3<.f> 0,limm,limm 0010011000010110F111111110111110. */
+{ "add3", 0x26167FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add3<.f><.cc> 0,limm,limm 0010011011010110F1111111100QQQQQ. */
+{ "add3", 0x26D67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add3l<.f> RA,RB,RC 01011bbb00010110FBBBccccccaaaaaa. */
+{ "add3l", 0x58160000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* add3l<.f> 0,RB,RC 01011bbb00010110FBBBcccccc111110. */
+{ "add3l", 0x5816003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* add3l<.f><.cc> RB,RB,RC 01011bbb11010110FBBBcccccc0QQQQQ. */
+{ "add3l", 0x58D60000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* add3l<.f> RA,RB,u6 01011bbb01010110FBBBuuuuuuaaaaaa. */
+{ "add3l", 0x58560000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* add3l<.f> 0,RB,u6 01011bbb01010110FBBBuuuuuu111110. */
+{ "add3l", 0x5856003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* add3l<.f><.cc> RB,RB,u6 01011bbb11010110FBBBuuuuuu1QQQQQ. */
+{ "add3l", 0x58D60020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3l<.f> RB,RB,s12 01011bbb10010110FBBBssssssSSSSSS. */
+{ "add3l", 0x58960000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* add3l<.f> RA,ximm,RC 0101110000010110F111ccccccaaaaaa. */
+{ "add3l", 0x5C167000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* add3l<.f> RA,RB,ximm 01011bbb00010110FBBB111100aaaaaa. */
+{ "add3l", 0x58160F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* add3l<.f> 0,ximm,RC 0101110000010110F111cccccc111110. */
+{ "add3l", 0x5C16703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* add3l<.f> 0,RB,ximm 01011bbb00010110FBBB111100111110. */
+{ "add3l", 0x58160F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* add3l<.f><.cc> 0,ximm,RC 0101110011010110F111cccccc0QQQQQ. */
+{ "add3l", 0x5CD67000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* add3l<.f><.cc> RB,RB,ximm 01011bbb11010110FBBB1111000QQQQQ. */
+{ "add3l", 0x58D60F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* add3l<.f> RA,ximm,u6 0101110001010110F111uuuuuuaaaaaa. */
+{ "add3l", 0x5C567000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add3l<.f> 0,ximm,u6 0101110001010110F111uuuuuu111110. */
+{ "add3l", 0x5C56703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* add3l<.f><.cc> 0,ximm,u6 0101110011010110F111uuuuuu1QQQQQ. */
+{ "add3l", 0x5CD67020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3l<.f> RA,limm,RC 0101111000010110F111ccccccaaaaaa. */
+{ "add3l", 0x5E167000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* add3l<.f> RA,RB,limm 01011bbb00010110FBBB111110aaaaaa. */
+{ "add3l", 0x58160F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* add3l<.f> 0,limm,RC 0101111000010110F111cccccc111110. */
+{ "add3l", 0x5E16703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* add3l<.f> 0,RB,limm 01011bbb00010110FBBB111110111110. */
+{ "add3l", 0x58160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* add3l<.f><.cc> 0,limm,RC 0101111011010110F111cccccc0QQQQQ. */
+{ "add3l", 0x5ED67000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* add3l<.f><.cc> RB,RB,limm 01011bbb11010110FBBB1111100QQQQQ. */
+{ "add3l", 0x58D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* add3l<.f> RA,limm,u6 0101111001010110F111uuuuuuaaaaaa. */
+{ "add3l", 0x5E567000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add3l<.f> 0,limm,u6 0101111001010110F111uuuuuu111110. */
+{ "add3l", 0x5E56703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* add3l<.f><.cc> 0,limm,u6 0101111011010110F111uuuuuu1QQQQQ. */
+{ "add3l", 0x5ED67020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* add3l<.f> 0,ximm,s12 0101110010010110F111ssssssSSSSSS. */
+{ "add3l", 0x5C967000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* add3l<.f> 0,limm,s12 0101111010010110F111ssssssSSSSSS. */
+{ "add3l", 0x5E967000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* add3l<.f> RA,ximm,ximm 0101110000010110F111111100aaaaaa. */
+{ "add3l", 0x5C167F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* add3l<.f> 0,ximm,ximm 0101110000010110F111111100111110. */
+{ "add3l", 0x5C167F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* add3l<.f><.cc> 0,ximm,ximm 0101110011010110F1111111000QQQQQ. */
+{ "add3l", 0x5CD67F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* add3l<.f> RA,limm,limm 0101111000010110F111111110aaaaaa. */
+{ "add3l", 0x5E167F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* add3l<.f> 0,limm,limm 0101111000010110F111111110111110. */
+{ "add3l", 0x5E167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* add3l<.f><.cc> 0,limm,limm 0101111011010110F1111111100QQQQQ. */
+{ "add3l", 0x5ED67F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add3_s b,b,c 01111bbbccc10110. */
+{ "add3_s", 0x00007816, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* addhl RA,RB,RC 01011bbb001011100BBBccccccaaaaaa. */
+{ "addhl", 0x582E0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { 0 }},
+
+/* addhl 0,RB,RC 01011bbb001011100BBBcccccc111110. */
+{ "addhl", 0x582E003E, 0xF8FF803F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* addhl<.cc> RB,RB,RC 01011bbb111011100BBBcccccc0QQQQQ. */
+{ "addhl", 0x58EE0000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* addhl RA,RB,u6 01011bbb011011100BBBuuuuuuaaaaaa. */
+{ "addhl", 0x586E0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* addhl 0,RB,u6 01011bbb011011100BBBuuuuuu111110. */
+{ "addhl", 0x586E003E, 0xF8FF803F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* addhl<.cc> RB,RB,u6 01011bbb111011100BBBuuuuuu1QQQQQ. */
+{ "addhl", 0x58EE0020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* addhl RB,RB,s12 01011bbb101011100BBBssssssSSSSSS. */
+{ "addhl", 0x58AE0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* addhl RA,ximm,RC 01011100001011100111ccccccaaaaaa. */
+{ "addhl", 0x5C2E7000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { 0 }},
+
+/* addhl RA,RB,ximm 01011bbb001011100BBB111100aaaaaa. */
+{ "addhl", 0x582E0F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { 0 }},
+
+/* addhl 0,ximm,RC 01011100001011100111cccccc111110. */
+{ "addhl", 0x5C2E703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { 0 }},
+
+/* addhl 0,RB,ximm 01011bbb001011100BBB111100111110. */
+{ "addhl", 0x582E0F3E, 0xF8FF8FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { 0 }},
+
+/* addhl<.cc> 0,ximm,RC 01011100111011100111cccccc0QQQQQ. */
+{ "addhl", 0x5CEE7000, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_CC }},
+
+/* addhl<.cc> RB,RB,ximm 01011bbb111011100BBB1111000QQQQQ. */
+{ "addhl", 0x58EE0F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_CC }},
+
+/* addhl RA,ximm,u6 01011100011011100111uuuuuuaaaaaa. */
+{ "addhl", 0x5C6E7000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { 0 }},
+
+/* addhl 0,ximm,u6 01011100011011100111uuuuuu111110. */
+{ "addhl", 0x5C6E703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { 0 }},
+
+/* addhl<.cc> 0,ximm,u6 01011100111011100111uuuuuu1QQQQQ. */
+{ "addhl", 0x5CEE7020, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_CC }},
+
+/* addhl RA,limm,RC 01011110001011100111ccccccaaaaaa. */
+{ "addhl", 0x5E2E7000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* addhl RA,RB,limm 01011bbb001011100BBB111110aaaaaa. */
+{ "addhl", 0x582E0F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* addhl 0,limm,RC 01011110001011100111cccccc111110. */
+{ "addhl", 0x5E2E703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* addhl 0,RB,limm 01011bbb001011100BBB111110111110. */
+{ "addhl", 0x582E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* addhl<.cc> 0,limm,RC 01011110111011100111cccccc0QQQQQ. */
+{ "addhl", 0x5EEE7000, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* addhl<.cc> RB,RB,limm 01011bbb111011100BBB1111100QQQQQ. */
+{ "addhl", 0x58EE0F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* addhl RA,limm,u6 01011110011011100111uuuuuuaaaaaa. */
+{ "addhl", 0x5E6E7000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* addhl 0,limm,u6 01011110011011100111uuuuuu111110. */
+{ "addhl", 0x5E6E703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* addhl<.cc> 0,limm,u6 01011110111011100111uuuuuu1QQQQQ. */
+{ "addhl", 0x5EEE7020, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* addhl 0,ximm,s12 01011100101011100111ssssssSSSSSS. */
+{ "addhl", 0x5CAE7000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { 0 }},
+
+/* addhl 0,limm,s12 01011110101011100111ssssssSSSSSS. */
+{ "addhl", 0x5EAE7000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* addhl RA,ximm,ximm 01011100001011100111111100aaaaaa. */
+{ "addhl", 0x5C2E7F00, 0xFFFFFFC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { 0 }},
+
+/* addhl 0,ximm,ximm 01011100001011100111111100111110. */
+{ "addhl", 0x5C2E7F3E, 0xFFFFFFFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { 0 }},
+
+/* addhl<.cc> 0,ximm,ximm 010111001110111001111111000QQQQQ. */
+{ "addhl", 0x5CEE7F00, 0xFFFFFFE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_CC }},
+
+/* addhl RA,limm,limm 01011110001011100111111110aaaaaa. */
+{ "addhl", 0x5E2E7F80, 0xFFFFFFC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* addhl 0,limm,limm 01011110001011100111111110111110. */
+{ "addhl", 0x5E2E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* addhl<.cc> 0,limm,limm 010111101110111001111111100QQQQQ. */
+{ "addhl", 0x5EEE7F80, 0xFFFFFFE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* addhl_s h,PCL,ximm 01110011hhh010HH. */
+{ "addhl_s", 0x00007308, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, PCL_S, XIMM_S }, { 0 }},
+
+/* addhl_s h,h,limm 01110001hhh010HH. */
+{ "addhl_s", 0x00007108, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, HI32 }, { 0 }},
+
+/* addl<.f> RA,RB,RC 01011bbb00000000FBBBccccccaaaaaa. */
+{ "addl", 0x58000000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* addl<.f> 0,RB,RC 01011bbb00000000FBBBcccccc111110. */
+{ "addl", 0x5800003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* addl<.f><.cc> RB,RB,RC 01011bbb11000000FBBBcccccc0QQQQQ. */
+{ "addl", 0x58C00000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* addl<.f> RA,RB,u6 01011bbb01000000FBBBuuuuuuaaaaaa. */
+{ "addl", 0x58400000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* addl<.f> 0,RB,u6 01011bbb01000000FBBBuuuuuu111110. */
+{ "addl", 0x5840003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* addl<.f><.cc> RB,RB,u6 01011bbb11000000FBBBuuuuuu1QQQQQ. */
+{ "addl", 0x58C00020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* addl<.f> RB,RB,s12 01011bbb10000000FBBBssssssSSSSSS. */
+{ "addl", 0x58800000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* addl<.f> RA,ximm,RC 0101110000000000F111ccccccaaaaaa. */
+{ "addl", 0x5C007000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* addl<.f> RA,RB,ximm 01011bbb00000000FBBB111100aaaaaa. */
+{ "addl", 0x58000F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* addl<.f> 0,ximm,RC 0101110000000000F111cccccc111110. */
+{ "addl", 0x5C00703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* addl<.f> 0,RB,ximm 01011bbb00000000FBBB111100111110. */
+{ "addl", 0x58000F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* addl<.f><.cc> 0,ximm,RC 0101110011000000F111cccccc0QQQQQ. */
+{ "addl", 0x5CC07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* addl<.f><.cc> RB,RB,ximm 01011bbb11000000FBBB1111000QQQQQ. */
+{ "addl", 0x58C00F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* addl<.f> RA,ximm,u6 0101110001000000F111uuuuuuaaaaaa. */
+{ "addl", 0x5C407000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* addl<.f> 0,ximm,u6 0101110001000000F111uuuuuu111110. */
+{ "addl", 0x5C40703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* addl<.f><.cc> 0,ximm,u6 0101110011000000F111uuuuuu1QQQQQ. */
+{ "addl", 0x5CC07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* addl<.f> RA,limm,RC 0101111000000000F111ccccccaaaaaa. */
+{ "addl", 0x5E007000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* addl<.f> RA,RB,limm 01011bbb00000000FBBB111110aaaaaa. */
+{ "addl", 0x58000F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* addl<.f> 0,limm,RC 0101111000000000F111cccccc111110. */
+{ "addl", 0x5E00703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* addl<.f> 0,RB,limm 01011bbb00000000FBBB111110111110. */
+{ "addl", 0x58000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* addl<.f><.cc> 0,limm,RC 0101111011000000F111cccccc0QQQQQ. */
+{ "addl", 0x5EC07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* addl<.f><.cc> RB,RB,limm 01011bbb11000000FBBB1111100QQQQQ. */
+{ "addl", 0x58C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* addl<.f> RA,limm,u6 0101111001000000F111uuuuuuaaaaaa. */
+{ "addl", 0x5E407000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* addl<.f> 0,limm,u6 0101111001000000F111uuuuuu111110. */
+{ "addl", 0x5E40703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* addl<.f><.cc> 0,limm,u6 0101111011000000F111uuuuuu1QQQQQ. */
+{ "addl", 0x5EC07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* addl<.f> 0,ximm,s12 0101110010000000F111ssssssSSSSSS. */
+{ "addl", 0x5C807000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* addl<.f> 0,limm,s12 0101111010000000F111ssssssSSSSSS. */
+{ "addl", 0x5E807000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* addl<.f> RA,ximm,ximm 0101110000000000F111111100aaaaaa. */
+{ "addl", 0x5C007F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* addl<.f> 0,ximm,ximm 0101110000000000F111111100111110. */
+{ "addl", 0x5C007F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* addl<.f><.cc> 0,ximm,ximm 0101110011000000F1111111000QQQQQ. */
+{ "addl", 0x5CC07F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* addl<.f> RA,limm,limm 0101111000000000F111111110aaaaaa. */
+{ "addl", 0x5E007F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* addl<.f> 0,limm,limm 0101111000000000F111111110111110. */
+{ "addl", 0x5E007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* addl<.f><.cc> 0,limm,limm 0101111011000000F1111111100QQQQQ. */
+{ "addl", 0x5EC07F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* addl_s SP,SP,u9 11000UU0101uuuuu. */
+{ "addl_s", 0x0000C0A0, 0x0000F9E0, ARC_OPCODE_ARC64, ARITH, NONE, { SP_S, SP_Sdup, UIMM9_A32_11_S }, { 0 }},
+
+/* addl_s b,b,c 01111bbbccc00001. */
+{ "addl_s", 0x00007801, 0x0000F81F, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* addl_s b,SP,u7 11000bbb100uuuuu. */
+{ "addl_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, SP_S, UIMM7_A32_11_S }, { 0 }},
+
+/* addl_s R0,GP,s11 1100111sssssssss. */
+{ "addl_s", 0x0000CE00, 0x0000FE00, ARC_OPCODE_ARC64, ARITH, NONE, { R0_S, GP_S, SIMM11_A32_7_S }, { 0 }},
+
+/* addl_s h,h,LO32 01110001hhh110HH. */
+{ "addl_s", 0x00007118, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, LO32 }, { 0 }},
+
+/* addl_s h,PCL,LO32 01110011hhh110HH. */
+{ "addl_s", 0x00007318, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, PCL_S, LO32 }, { 0 }},
+
+/* adds<.f> a,b,c 00101bbb00000110FBBBCCCCCCAAAAAA. */
+{ "adds", 0x28060000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* adds<.f> 0,b,c 00101bbb00000110FBBBCCCCCC111110. */
+{ "adds", 0x2806003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* adds<.f><.cc> b,b,c 00101bbb11000110FBBBCCCCCC0QQQQQ. */
+{ "adds", 0x28C60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* adds<.f> a,b,u6 00101bbb01000110FBBBuuuuuuAAAAAA. */
+{ "adds", 0x28460000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* adds<.f> 0,b,u6 00101bbb01000110FBBBuuuuuu111110. */
+{ "adds", 0x2846003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* adds<.f><.cc> b,b,u6 00101bbb11000110FBBBuuuuuu1QQQQQ. */
+{ "adds", 0x28C60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* adds<.f> b,b,s12 00101bbb10000110FBBBssssssSSSSSS. */
+{ "adds", 0x28860000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* adds<.f> a,limm,c 0010111000000110F111CCCCCCAAAAAA. */
+{ "adds", 0x2E067000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* adds<.f> a,b,limm 00101bbb00000110FBBB111110AAAAAA. */
+{ "adds", 0x28060F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* adds<.f> 0,limm,c 0010111000000110F111CCCCCC111110. */
+{ "adds", 0x2E06703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* adds<.f> 0,b,limm 00101bbb00000110FBBB111110111110. */
+{ "adds", 0x28060FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* adds<.f><.cc> b,b,limm 00101bbb11000110FBBB1111100QQQQQ. */
+{ "adds", 0x28C60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* adds<.f><.cc> 0,limm,c 0010111011000110F111CCCCCC0QQQQQ. */
+{ "adds", 0x2EC67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* adds<.f> a,limm,u6 0010111001000110F111uuuuuuAAAAAA. */
+{ "adds", 0x2E467000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adds<.f> 0,limm,u6 0010111001000110F111uuuuuu111110. */
+{ "adds", 0x2E46703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* adds<.f><.cc> 0,limm,u6 0010111011000110F111uuuuuu1QQQQQ. */
+{ "adds", 0x2EC67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* adds<.f> 0,limm,s12 0010111010000110F111ssssssSSSSSS. */
+{ "adds", 0x2E867000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* adds<.f> a,limm,limm 0010111000000110F111111110AAAAAA. */
+{ "adds", 0x2E067F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* adds<.f> 0,limm,limm 0010111000000110F111111110111110. */
+{ "adds", 0x2E067FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* adds<.f><.cc> 0,limm,limm 0010111011000110F1111111100QQQQQ. */
+{ "adds", 0x2EC67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* add_s a,b,c 01100bbbccc11aaa. */
+{ "add_s", 0x00006018, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA_S, RB_S, RC_S }, { 0 }},
+
+/* add_s b,b,h 01110bbbhhh000HH. */
+{ "add_s", 0x00007000, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RH_S }, { 0 }},
+
+/* add_s h,h,s3 01110ssshhh001HH. */
+{ "add_s", 0x00007004, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, SIMM3_5_S }, { 0 }},
+
+/* add_s c,b,u3 01101bbbccc00uuu. */
+{ "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+
+/* add_s R0,b,u6 01001bbb0UUU1uuu. */
+{ "add_s", 0x00004808, 0x0000F888, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, CD2, { R0_S, RB_S, UIMM6_13_S }, { 0 }},
+
+/* add_s R1,b,u6 01001bbb1UUU1uuu. */
+{ "add_s", 0x00004888, 0x0000F888, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, CD2, { R1_S, RB_S, UIMM6_13_S }, { 0 }},
+
+/* add_s b,b,limm 01110bbb11000011. */
+{ "add_s", 0x000070C3, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, LIMM_S }, { 0 }},
+
+/* add_s 0,limm,s3 01110sss11000111. */
+{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA_S, LIMM_S, SIMM3_5_S }, { 0 }},
+
+/* aex b,c 00100bbb00100111RBBBCCCCCCRRRRRR. */
+{ "aex", 0x20270000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* aex<.cc> b,c 00100bbb11100111RBBBCCCCCC0QQQQQ. */
+{ "aex", 0x20E70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* aex b,u6 00100bbb01100111RBBBuuuuuuRRRRRR. */
+{ "aex", 0x20670000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* aex<.cc> b,u6 00100bbb11100111RBBBuuuuuu1QQQQQ. */
+{ "aex", 0x20E70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+
+/* aex b,s12 00100bbb10100111RBBBssssssSSSSSS. */
+{ "aex", 0x20A70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* aex limm,c 0010011000100111R111CCCCCCRRRRRR. */
+{ "aex", 0x26277000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* aex b,limm 00100bbb00100111RBBB111110RRRRRR. */
+{ "aex", 0x20270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* aex<.cc> limm,c 0010011011100111R111CCCCCC0QQQQQ. */
+{ "aex", 0x26E77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* aex<.cc> b,limm 00100bbb11100111RBBB1111100QQQQQ. */
+{ "aex", 0x20E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { C_CC }},
+
+/* aex limm,u6 0010011001100111R111uuuuuuRRRRRR. */
+{ "aex", 0x26677000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* aex<.cc> limm,u6 0010011011100111R111uuuuuu1QQQQQ. */
+{ "aex", 0x26E77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+
+/* aex limm,s12 0010011010100111R111ssssssSSSSSS. */
+{ "aex", 0x26A77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* aex limm,limm 0010011000100111R111111110RRRRRR. */
+{ "aex", 0x26277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 }},
+
+/* aex<.cc> limm,limm 0010011011100111R1111111100QQQQQ. */
+{ "aex", 0x26E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_CC }},
+
+/* aexl RB,RC 01011bbb001001110BBBccccccRRRRRR. */
+{ "aexl", 0x58270000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* aexl<.cc> RB,RC 01011bbb111001110BBBcccccc0QQQQQ. */
+{ "aexl", 0x58E70000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* aexl RB,u6 01011bbb011001110BBBuuuuuuRRRRRR. */
+{ "aexl", 0x58670000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* aexl<.cc> RB,u6 01011bbb111001110BBBuuuuuu1QQQQQ. */
+{ "aexl", 0x58E70020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }},
+
+/* aexl RB,s12 01011bbb101001110BBBssssssSSSSSS. */
+{ "aexl", 0x58A70000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* aexl RB,ximm 01011bbb001001110BBB111100RRRRRR. */
+{ "aexl", 0x58270F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, XIMM, BRAKETdup }, { 0 }},
+
+/* aexl<.cc> RB,ximm 01011bbb111001110BBB1111000QQQQQ. */
+{ "aexl", 0x58E70F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, XIMM, BRAKETdup }, { C_CC }},
+
+/* aexl RB,limm 01011bbb001001110BBB111110RRRRRR. */
+{ "aexl", 0x58270F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* aexl<.cc> RB,limm 01011bbb111001110BBB1111100QQQQQ. */
+{ "aexl", 0x58E70F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_CC }},
+
+/* and<.f> a,b,c 00100bbb00000100FBBBCCCCCCAAAAAA. */
+{ "and", 0x20040000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* and<.f> 0,b,c 00100bbb00000100FBBBCCCCCC111110. */
+{ "and", 0x2004003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* and<.f><.cc> b,b,c 00100bbb11000100FBBBCCCCCC0QQQQQ. */
+{ "and", 0x20C40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* and<.f> a,b,u6 00100bbb01000100FBBBuuuuuuAAAAAA. */
+{ "and", 0x20440000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* and<.f> 0,b,u6 00100bbb01000100FBBBuuuuuu111110. */
+{ "and", 0x2044003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* and<.f><.cc> b,b,u6 00100bbb11000100FBBBuuuuuu1QQQQQ. */
+{ "and", 0x20C40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* and<.f> b,b,s12 00100bbb10000100FBBBssssssSSSSSS. */
+{ "and", 0x20840000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* and<.f> a,limm,c 0010011000000100F111CCCCCCAAAAAA. */
+{ "and", 0x26047000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* and<.f> a,b,limm 00100bbb00000100FBBB111110AAAAAA. */
+{ "and", 0x20040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* and<.f> 0,limm,c 0010011000000100F111CCCCCC111110. */
+{ "and", 0x2604703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* and<.f> 0,b,limm 00100bbb00000100FBBB111110111110. */
+{ "and", 0x20040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* and<.f><.cc> b,b,limm 00100bbb11000100FBBB1111100QQQQQ. */
+{ "and", 0x20C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* and<.f><.cc> 0,limm,c 0010011011000100F111CCCCCC0QQQQQ. */
+{ "and", 0x26C47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* and<.f> a,limm,u6 0010011001000100F111uuuuuuAAAAAA. */
+{ "and", 0x26447000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* and<.f> 0,limm,u6 0010011001000100F111uuuuuu111110. */
+{ "and", 0x2644703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* and<.f><.cc> 0,limm,u6 0010011011000100F111uuuuuu1QQQQQ. */
+{ "and", 0x26C47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* and<.f> 0,limm,s12 0010011010000100F111ssssssSSSSSS. */
+{ "and", 0x26847000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* and<.f> a,limm,limm 0010011000000100F111111110AAAAAA. */
+{ "and", 0x26047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* and<.f> 0,limm,limm 0010011000000100F111111110111110. */
+{ "and", 0x26047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* and<.f><.cc> 0,limm,limm 0010011011000100F1111111100QQQQQ. */
+{ "and", 0x26C47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* andl<.f> RA,RB,RC 01011bbb00000100FBBBccccccaaaaaa. */
+{ "andl", 0x58040000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* andl<.f> 0,RB,RC 01011bbb00000100FBBBcccccc111110. */
+{ "andl", 0x5804003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* andl<.f><.cc> RB,RB,RC 01011bbb11000100FBBBcccccc0QQQQQ. */
+{ "andl", 0x58C40000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* andl<.f> RA,RB,u6 01011bbb01000100FBBBuuuuuuaaaaaa. */
+{ "andl", 0x58440000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* andl<.f> 0,RB,u6 01011bbb01000100FBBBuuuuuu111110. */
+{ "andl", 0x5844003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* andl<.f><.cc> RB,RB,u6 01011bbb11000100FBBBuuuuuu1QQQQQ. */
+{ "andl", 0x58C40020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* andl<.f> RB,RB,s12 01011bbb10000100FBBBssssssSSSSSS. */
+{ "andl", 0x58840000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* andl<.f> RA,ximm,RC 0101110000000100F111ccccccaaaaaa. */
+{ "andl", 0x5C047000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* andl<.f> RA,RB,ximm 01011bbb00000100FBBB111100aaaaaa. */
+{ "andl", 0x58040F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* andl<.f> 0,ximm,RC 0101110000000100F111cccccc111110. */
+{ "andl", 0x5C04703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* andl<.f> 0,RB,ximm 01011bbb00000100FBBB111100111110. */
+{ "andl", 0x58040F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* andl<.f><.cc> 0,ximm,RC 0101110011000100F111cccccc0QQQQQ. */
+{ "andl", 0x5CC47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* andl<.f><.cc> RB,RB,ximm 01011bbb11000100FBBB1111000QQQQQ. */
+{ "andl", 0x58C40F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* andl<.f> RA,ximm,u6 0101110001000100F111uuuuuuaaaaaa. */
+{ "andl", 0x5C447000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* andl<.f> 0,ximm,u6 0101110001000100F111uuuuuu111110. */
+{ "andl", 0x5C44703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* andl<.f><.cc> 0,ximm,u6 0101110011000100F111uuuuuu1QQQQQ. */
+{ "andl", 0x5CC47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* andl<.f> RA,limm,RC 0101111000000100F111ccccccaaaaaa. */
+{ "andl", 0x5E047000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* andl<.f> RA,RB,limm 01011bbb00000100FBBB111110aaaaaa. */
+{ "andl", 0x58040F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* andl<.f> 0,limm,RC 0101111000000100F111cccccc111110. */
+{ "andl", 0x5E04703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* andl<.f> 0,RB,limm 01011bbb00000100FBBB111110111110. */
+{ "andl", 0x58040FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* andl<.f><.cc> 0,limm,RC 0101111011000100F111cccccc0QQQQQ. */
+{ "andl", 0x5EC47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* andl<.f><.cc> RB,RB,limm 01011bbb11000100FBBB1111100QQQQQ. */
+{ "andl", 0x58C40F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* andl<.f> RA,limm,u6 0101111001000100F111uuuuuuaaaaaa. */
+{ "andl", 0x5E447000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* andl<.f> 0,limm,u6 0101111001000100F111uuuuuu111110. */
+{ "andl", 0x5E44703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* andl<.f><.cc> 0,limm,u6 0101111011000100F111uuuuuu1QQQQQ. */
+{ "andl", 0x5EC47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* andl<.f> 0,ximm,s12 0101110010000100F111ssssssSSSSSS. */
+{ "andl", 0x5C847000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* andl<.f> 0,limm,s12 0101111010000100F111ssssssSSSSSS. */
+{ "andl", 0x5E847000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* andl<.f> RA,ximm,ximm 0101110000000100F111111100aaaaaa. */
+{ "andl", 0x5C047F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* andl<.f> 0,ximm,ximm 0101110000000100F111111100111110. */
+{ "andl", 0x5C047F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* andl<.f><.cc> 0,ximm,ximm 0101110011000100F1111111000QQQQQ. */
+{ "andl", 0x5CC47F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* andl<.f> RA,limm,limm 0101111000000100F111111110aaaaaa. */
+{ "andl", 0x5E047F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* andl<.f> 0,limm,limm 0101111000000100F111111110111110. */
+{ "andl", 0x5E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* andl<.f><.cc> 0,limm,limm 0101111011000100F1111111100QQQQQ. */
+{ "andl", 0x5EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* andl_s b,b,c 01111bbbccc01000. */
+{ "andl_s", 0x00007808, 0x0000F81F, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* and_s b,b,c 01111bbbccc00100. */
+{ "and_s", 0x00007804, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* asl<.f> b,c 00100bbb00101111FBBBCCCCCC000000. */
+{ "asl", 0x202F0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* asl<.f> 0,c 0010011000101111F111CCCCCC000000. */
+{ "asl", 0x262F7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* asl<.f> a,b,c 00101bbb00000000FBBBCCCCCCAAAAAA. */
+{ "asl", 0x28000000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* asl<.f> 0,b,c 00101bbb00000000FBBBCCCCCC111110. */
+{ "asl", 0x2800003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* asl<.f><.cc> b,b,c 00101bbb11000000FBBBCCCCCC0QQQQQ. */
+{ "asl", 0x28C00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asl<.f> b,u6 00100bbb01101111FBBBuuuuuu000000. */
+{ "asl", 0x206F0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* asl<.f> 0,u6 0010011001101111F111uuuuuu000000. */
+{ "asl", 0x266F7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* asl<.f> a,b,u6 00101bbb01000000FBBBuuuuuuAAAAAA. */
+{ "asl", 0x28400000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asl<.f> 0,b,u6 00101bbb01000000FBBBuuuuuu111110. */
+{ "asl", 0x2840003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asl<.f><.cc> b,b,u6 00101bbb11000000FBBBuuuuuu1QQQQQ. */
+{ "asl", 0x28C00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asl<.f> b,b,s12 00101bbb10000000FBBBssssssSSSSSS. */
+{ "asl", 0x28800000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asl<.f> b,limm 00100bbb00101111FBBB111110000000. */
+{ "asl", 0x202F0F80, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* asl<.f> 0,limm 0010011000101111F111111110000000. */
+{ "asl", 0x262F7F80, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* asl<.f> a,limm,c 0010111000000000F111CCCCCCAAAAAA. */
+{ "asl", 0x2E007000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* asl<.f> a,b,limm 00101bbb00000000FBBB111110AAAAAA. */
+{ "asl", 0x28000F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* asl<.f> 0,limm,c 0010111000000000F111CCCCCC111110. */
+{ "asl", 0x2E00703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* asl<.f> 0,b,limm 00101bbb00000000FBBB111110111110. */
+{ "asl", 0x28000FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* asl<.f><.cc> b,b,limm 00101bbb11000000FBBB1111100QQQQQ. */
+{ "asl", 0x28C00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asl<.f><.cc> 0,limm,c 0010111011000000F111CCCCCC0QQQQQ. */
+{ "asl", 0x2EC07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asl<.f> a,limm,u6 0010111001000000F111uuuuuuAAAAAA. */
+{ "asl", 0x2E407000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asl<.f> 0,limm,u6 0010111001000000F111uuuuuu111110. */
+{ "asl", 0x2E40703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asl<.f><.cc> 0,limm,u6 0010111011000000F111uuuuuu1QQQQQ. */
+{ "asl", 0x2EC07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asl<.f> 0,limm,s12 0010111010000000F111ssssssSSSSSS. */
+{ "asl", 0x2E807000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asl<.f> a,limm,limm 0010111000000000F111111110AAAAAA. */
+{ "asl", 0x2E007F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asl<.f> 0,limm,limm 0010111000000000F111111110111110. */
+{ "asl", 0x2E007FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asl<.f><.cc> 0,limm,limm 0010111011000000F1111111100QQQQQ. */
+{ "asl", 0x2EC07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* aslacc c 00101000001011110000CCCCCC111111. */
+{ "aslacc", 0x282F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RC_CHK }, { 0 }},
+
+/* aslacc u6 00101000011011110000uuuuuu111111. */
+{ "aslacc", 0x286F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { UIMM6_20 }, { 0 }},
+
+/* asll<.f> RA,RB,RC 01011bbb00100000FBBBccccccaaaaaa. */
+{ "asll", 0x58200000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* asll<.f> 0,RB,RC 01011bbb00100000FBBBcccccc111110. */
+{ "asll", 0x5820003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asll<.f><.cc> RB,RB,RC 01011bbb11100000FBBBcccccc0QQQQQ. */
+{ "asll", 0x58E00000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asll<.f> RB,RC 01011bbb00101111FBBBcccccc000000. */
+{ "asll", 0x582F0000, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* asll<.f> 0,RC 0101111000101111F111cccccc000000. */
+{ "asll", 0x5E2F7000, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* asll<.f> RA,RB,u6 01011bbb01100000FBBBuuuuuuaaaaaa. */
+{ "asll", 0x58600000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asll<.f> 0,RB,u6 01011bbb01100000FBBBuuuuuu111110. */
+{ "asll", 0x5860003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asll<.f><.cc> RB,RB,u6 01011bbb11100000FBBBuuuuuu1QQQQQ. */
+{ "asll", 0x58E00020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asll<.f> RB,u6 01011bbb01101111FBBBuuuuuu000000. */
+{ "asll", 0x586F0000, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* asll<.f> 0,u6 0101111001101111F111uuuuuu000000. */
+{ "asll", 0x5E6F7000, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* asll<.f> RB,RB,s12 01011bbb10100000FBBBssssssSSSSSS. */
+{ "asll", 0x58A00000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asll<.f> RA,ximm,RC 0101110000100000F111ccccccaaaaaa. */
+{ "asll", 0x5C207000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* asll<.f> RA,RB,ximm 01011bbb00100000FBBB111100aaaaaa. */
+{ "asll", 0x58200F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* asll<.f> 0,ximm,RC 0101110000100000F111cccccc111110. */
+{ "asll", 0x5C20703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* asll<.f> 0,RB,ximm 01011bbb00100000FBBB111100111110. */
+{ "asll", 0x58200F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* asll<.f><.cc> 0,ximm,RC 0101110011100000F111cccccc0QQQQQ. */
+{ "asll", 0x5CE07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* asll<.f><.cc> RB,RB,ximm 01011bbb11100000FBBB1111000QQQQQ. */
+{ "asll", 0x58E00F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* asll<.f> RB,ximm 01011bbb00101111FBBB111100000000. */
+{ "asll", 0x582F0F00, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* asll<.f> 0,ximm 0101111000101111F111111100000000. */
+{ "asll", 0x5E2F7F00, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* asll<.f> RA,ximm,u6 0101110001100000F111uuuuuuaaaaaa. */
+{ "asll", 0x5C607000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* asll<.f> 0,ximm,u6 0101110001100000F111uuuuuu111110. */
+{ "asll", 0x5C60703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* asll<.f><.cc> 0,ximm,u6 0101110011100000F111uuuuuu1QQQQQ. */
+{ "asll", 0x5CE07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asll<.f> RA,limm,RC 0101111000100000F111ccccccaaaaaa. */
+{ "asll", 0x5E207000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asll<.f> RA,RB,limm 01011bbb00100000FBBB111110aaaaaa. */
+{ "asll", 0x58200F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asll<.f> 0,limm,RC 0101111000100000F111cccccc111110. */
+{ "asll", 0x5E20703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asll<.f> 0,RB,limm 01011bbb00100000FBBB111110111110. */
+{ "asll", 0x58200FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asll<.f><.cc> 0,limm,RC 0101111011100000F111cccccc0QQQQQ. */
+{ "asll", 0x5EE07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asll<.f><.cc> RB,RB,limm 01011bbb11100000FBBB1111100QQQQQ. */
+{ "asll", 0x58E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asll<.f> RB,limm 01011bbb00101111FBBB111110000000. */
+{ "asll", 0x582F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* asll<.f> 0,limm 0101111000101111F111111110000000. */
+{ "asll", 0x5E2F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* asll<.f> RA,limm,u6 0101111001100000F111uuuuuuaaaaaa. */
+{ "asll", 0x5E607000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asll<.f> 0,limm,u6 0101111001100000F111uuuuuu111110. */
+{ "asll", 0x5E60703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asll<.f><.cc> 0,limm,u6 0101111011100000F111uuuuuu1QQQQQ. */
+{ "asll", 0x5EE07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asll<.f> 0,ximm,s12 0101110010100000F111ssssssSSSSSS. */
+{ "asll", 0x5CA07000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* asll<.f> 0,limm,s12 0101111010100000F111ssssssSSSSSS. */
+{ "asll", 0x5EA07000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asll<.f> RA,ximm,ximm 0101110000100000F111111100aaaaaa. */
+{ "asll", 0x5C207F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* asll<.f> 0,ximm,ximm 0101110000100000F111111100111110. */
+{ "asll", 0x5C207F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* asll<.f><.cc> 0,ximm,ximm 0101110011100000F1111111000QQQQQ. */
+{ "asll", 0x5CE07F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* asll<.f> RA,limm,limm 0101111000100000F111111110aaaaaa. */
+{ "asll", 0x5E207F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asll<.f> 0,limm,limm 0101111000100000F111111110111110. */
+{ "asll", 0x5E207FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asll<.f><.cc> 0,limm,limm 0101111011100000F1111111100QQQQQ. */
+{ "asll", 0x5EE07F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asls<.f> a,b,c 00101bbb00001010FBBBCCCCCCAAAAAA. */
+{ "asls", 0x280A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* asls<.f> 0,b,c 00101bbb00001010FBBBCCCCCC111110. */
+{ "asls", 0x280A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asls<.f><.cc> b,b,c 00101bbb11001010FBBBCCCCCC0QQQQQ. */
+{ "asls", 0x28CA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asls<.f> a,b,u6 00101bbb01001010FBBBuuuuuuAAAAAA. */
+{ "asls", 0x284A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asls<.f> 0,b,u6 00101bbb01001010FBBBuuuuuu111110. */
+{ "asls", 0x284A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asls<.f><.cc> b,b,u6 00101bbb11001010FBBBuuuuuu1QQQQQ. */
+{ "asls", 0x28CA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asls<.f> b,b,s12 00101bbb10001010FBBBssssssSSSSSS. */
+{ "asls", 0x288A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asls<.f> a,limm,c 0010111000001010F111CCCCCCAAAAAA. */
+{ "asls", 0x2E0A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asls<.f> a,b,limm 00101bbb00001010FBBB111110AAAAAA. */
+{ "asls", 0x280A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asls<.f> 0,limm,c 0010111000001010F111CCCCCC111110. */
+{ "asls", 0x2E0A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asls<.f> 0,b,limm 00101bbb00001010FBBB111110111110. */
+{ "asls", 0x280A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asls<.f><.cc> b,b,limm 00101bbb11001010FBBB1111100QQQQQ. */
+{ "asls", 0x28CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asls<.f><.cc> 0,limm,c 0010111011001010F111CCCCCC0QQQQQ. */
+{ "asls", 0x2ECA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asls<.f> a,limm,u6 0010111001001010F111uuuuuuAAAAAA. */
+{ "asls", 0x2E4A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asls<.f> 0,limm,u6 0010111001001010F111uuuuuu111110. */
+{ "asls", 0x2E4A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asls<.f><.cc> 0,limm,u6 0010111011001010F111uuuuuu1QQQQQ. */
+{ "asls", 0x2ECA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asls<.f> 0,limm,s12 0010111010001010F111ssssssSSSSSS. */
+{ "asls", 0x2E8A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asls<.f> a,limm,limm 0010111000001010F111111110AAAAAA. */
+{ "asls", 0x2E0A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asls<.f> 0,limm,limm 0010111000001010F111111110111110. */
+{ "asls", 0x2E0A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asls<.f><.cc> 0,limm,limm 0010111011001010F1111111100QQQQQ. */
+{ "asls", 0x2ECA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* aslsacc c 00101001001011110000CCCCCC111111. */
+{ "aslsacc", 0x292F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RC_CHK }, { 0 }},
+
+/* aslsacc u6 00101001011011110000uuuuuu111111. */
+{ "aslsacc", 0x296F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { UIMM6_20 }, { 0 }},
+
+/* asl_s b,c 01111bbbccc11011. */
+{ "asl_s", 0x0000781B, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* asl_s b,b,c 01111bbbccc11000. */
+{ "asl_s", 0x00007818, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* asl_s c,b,u3 01101bbbccc10uuu. */
+{ "asl_s", 0x00006810, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+
+/* asl_s b,b,u5 10111bbb000uuuuu. */
+{ "asl_s", 0x0000B800, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* asr<.f> b,c 00100bbb00101111FBBBCCCCCC000001. */
+{ "asr", 0x202F0001, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* asr<.f> 0,c 0010011000101111F111CCCCCC000001. */
+{ "asr", 0x262F7001, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* asr<.f> a,b,c 00101bbb00000010FBBBCCCCCCAAAAAA. */
+{ "asr", 0x28020000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* asr<.f> 0,b,c 00101bbb00000010FBBBCCCCCC111110. */
+{ "asr", 0x2802003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* asr<.f><.cc> b,b,c 00101bbb11000010FBBBCCCCCC0QQQQQ. */
+{ "asr", 0x28C20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asr<.f> b,u6 00100bbb01101111FBBBuuuuuu000001. */
+{ "asr", 0x206F0001, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* asr<.f> 0,u6 0010011001101111F111uuuuuu000001. */
+{ "asr", 0x266F7001, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* asr<.f> a,b,u6 00101bbb01000010FBBBuuuuuuAAAAAA. */
+{ "asr", 0x28420000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asr<.f> 0,b,u6 00101bbb01000010FBBBuuuuuu111110. */
+{ "asr", 0x2842003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asr<.f><.cc> b,b,u6 00101bbb11000010FBBBuuuuuu1QQQQQ. */
+{ "asr", 0x28C20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asr<.f> b,b,s12 00101bbb10000010FBBBssssssSSSSSS. */
+{ "asr", 0x28820000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asr<.f> b,limm 00100bbb00101111FBBB111110000001. */
+{ "asr", 0x202F0F81, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* asr<.f> 0,limm 0010011000101111F111111110000001. */
+{ "asr", 0x262F7F81, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* asr<.f> a,limm,c 0010111000000010F111CCCCCCAAAAAA. */
+{ "asr", 0x2E027000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* asr<.f> a,b,limm 00101bbb00000010FBBB111110AAAAAA. */
+{ "asr", 0x28020F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* asr<.f> 0,limm,c 0010111000000010F111CCCCCC111110. */
+{ "asr", 0x2E02703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* asr<.f> 0,b,limm 00101bbb00000010FBBB111110111110. */
+{ "asr", 0x28020FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* asr<.f><.cc> b,b,limm 00101bbb11000010FBBB1111100QQQQQ. */
+{ "asr", 0x28C20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asr<.f><.cc> 0,limm,c 0010111011000010F111CCCCCC0QQQQQ. */
+{ "asr", 0x2EC27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asr<.f> a,limm,u6 0010111001000010F111uuuuuuAAAAAA. */
+{ "asr", 0x2E427000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asr<.f> 0,limm,u6 0010111001000010F111uuuuuu111110. */
+{ "asr", 0x2E42703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asr<.f><.cc> 0,limm,u6 0010111011000010F111uuuuuu1QQQQQ. */
+{ "asr", 0x2EC27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asr<.f> 0,limm,s12 0010111010000010F111ssssssSSSSSS. */
+{ "asr", 0x2E827000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asr<.f> a,limm,limm 0010111000000010F111111110AAAAAA. */
+{ "asr", 0x2E027F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asr<.f> 0,limm,limm 0010111000000010F111111110111110. */
+{ "asr", 0x2E027FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asr<.f><.cc> 0,limm,limm 0010111011000010F1111111100QQQQQ. */
+{ "asr", 0x2EC27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asr16<.f> b,c 00101bbb00101111FBBBCCCCCC001100. */
+{ "asr16", 0x282F000C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* asr16<.f> 0,c 0010111000101111F111CCCCCC001100. */
+{ "asr16", 0x2E2F700C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* asr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001100. */
+{ "asr16", 0x286F000C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* asr16<.f> 0,u6 0010111001101111F111uuuuuu001100. */
+{ "asr16", 0x2E6F700C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* asr16<.f> b,limm 00101bbb00101111FBBB111110001100. */
+{ "asr16", 0x282F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* asr16<.f> 0,limm 0010111000101111F111111110001100. */
+{ "asr16", 0x2E2F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* asr8<.f> b,c 00101bbb00101111FBBBCCCCCC001101. */
+{ "asr8", 0x282F000D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* asr8<.f> 0,c 0010111000101111F111CCCCCC001101. */
+{ "asr8", 0x2E2F700D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* asr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001101. */
+{ "asr8", 0x286F000D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* asr8<.f> 0,u6 0010111001101111F111uuuuuu001101. */
+{ "asr8", 0x2E6F700D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* asr8<.f> b,limm 00101bbb00101111FBBB111110001101. */
+{ "asr8", 0x282F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* asr8<.f> 0,limm 0010111000101111F111111110001101. */
+{ "asr8", 0x2E2F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* asrl<.f> RA,RB,RC 01011bbb00100010FBBBccccccaaaaaa. */
+{ "asrl", 0x58220000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* asrl<.f> 0,RB,RC 01011bbb00100010FBBBcccccc111110. */
+{ "asrl", 0x5822003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asrl<.f><.cc> RB,RB,RC 01011bbb11100010FBBBcccccc0QQQQQ. */
+{ "asrl", 0x58E20000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asrl<.f> RB,RC 01011bbb00101111FBBBcccccc000001. */
+{ "asrl", 0x582F0001, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* asrl<.f> 0,RC 0101111000101111F111cccccc000001. */
+{ "asrl", 0x5E2F7001, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* asrl<.f> RA,RB,u6 01011bbb01100010FBBBuuuuuuaaaaaa. */
+{ "asrl", 0x58620000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asrl<.f> 0,RB,u6 01011bbb01100010FBBBuuuuuu111110. */
+{ "asrl", 0x5862003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asrl<.f><.cc> RB,RB,u6 01011bbb11100010FBBBuuuuuu1QQQQQ. */
+{ "asrl", 0x58E20020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrl<.f> RB,u6 01011bbb01101111FBBBuuuuuu000001. */
+{ "asrl", 0x586F0001, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* asrl<.f> 0,u6 0101111001101111F111uuuuuu000001. */
+{ "asrl", 0x5E6F7001, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* asrl<.f> RB,RB,s12 01011bbb10100010FBBBssssssSSSSSS. */
+{ "asrl", 0x58A20000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asrl<.f> RA,ximm,RC 0101110000100010F111ccccccaaaaaa. */
+{ "asrl", 0x5C227000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* asrl<.f> RA,RB,ximm 01011bbb00100010FBBB111100aaaaaa. */
+{ "asrl", 0x58220F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* asrl<.f> 0,ximm,RC 0101110000100010F111cccccc111110. */
+{ "asrl", 0x5C22703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* asrl<.f> 0,RB,ximm 01011bbb00100010FBBB111100111110. */
+{ "asrl", 0x58220F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* asrl<.f><.cc> 0,ximm,RC 0101110011100010F111cccccc0QQQQQ. */
+{ "asrl", 0x5CE27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* asrl<.f><.cc> RB,RB,ximm 01011bbb11100010FBBB1111000QQQQQ. */
+{ "asrl", 0x58E20F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* asrl<.f> RB,ximm 01011bbb00101111FBBB111100000001. */
+{ "asrl", 0x582F0F01, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* asrl<.f> 0,ximm 0101111000101111F111111100000001. */
+{ "asrl", 0x5E2F7F01, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* asrl<.f> RA,ximm,u6 0101110001100010F111uuuuuuaaaaaa. */
+{ "asrl", 0x5C627000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* asrl<.f> 0,ximm,u6 0101110001100010F111uuuuuu111110. */
+{ "asrl", 0x5C62703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* asrl<.f><.cc> 0,ximm,u6 0101110011100010F111uuuuuu1QQQQQ. */
+{ "asrl", 0x5CE27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrl<.f> RA,limm,RC 0101111000100010F111ccccccaaaaaa. */
+{ "asrl", 0x5E227000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asrl<.f> RA,RB,limm 01011bbb00100010FBBB111110aaaaaa. */
+{ "asrl", 0x58220F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asrl<.f> 0,limm,RC 0101111000100010F111cccccc111110. */
+{ "asrl", 0x5E22703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asrl<.f> 0,RB,limm 01011bbb00100010FBBB111110111110. */
+{ "asrl", 0x58220FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asrl<.f><.cc> 0,limm,RC 0101111011100010F111cccccc0QQQQQ. */
+{ "asrl", 0x5EE27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asrl<.f><.cc> RB,RB,limm 01011bbb11100010FBBB1111100QQQQQ. */
+{ "asrl", 0x58E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asrl<.f> RB,limm 01011bbb00101111FBBB111110000001. */
+{ "asrl", 0x582F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* asrl<.f> 0,limm 0101111000101111F111111110000001. */
+{ "asrl", 0x5E2F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* asrl<.f> RA,limm,u6 0101111001100010F111uuuuuuaaaaaa. */
+{ "asrl", 0x5E627000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrl<.f> 0,limm,u6 0101111001100010F111uuuuuu111110. */
+{ "asrl", 0x5E62703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrl<.f><.cc> 0,limm,u6 0101111011100010F111uuuuuu1QQQQQ. */
+{ "asrl", 0x5EE27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrl<.f> 0,ximm,s12 0101110010100010F111ssssssSSSSSS. */
+{ "asrl", 0x5CA27000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* asrl<.f> 0,limm,s12 0101111010100010F111ssssssSSSSSS. */
+{ "asrl", 0x5EA27000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asrl<.f> RA,ximm,ximm 0101110000100010F111111100aaaaaa. */
+{ "asrl", 0x5C227F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* asrl<.f> 0,ximm,ximm 0101110000100010F111111100111110. */
+{ "asrl", 0x5C227F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* asrl<.f><.cc> 0,ximm,ximm 0101110011100010F1111111000QQQQQ. */
+{ "asrl", 0x5CE27F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* asrl<.f> RA,limm,limm 0101111000100010F111111110aaaaaa. */
+{ "asrl", 0x5E227F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asrl<.f> 0,limm,limm 0101111000100010F111111110111110. */
+{ "asrl", 0x5E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asrl<.f><.cc> 0,limm,limm 0101111011100010F1111111100QQQQQ. */
+{ "asrl", 0x5EE27F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asrs<.f> a,b,c 00101bbb00001011FBBBCCCCCCAAAAAA. */
+{ "asrs", 0x280B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* asrs<.f> 0,b,c 00101bbb00001011FBBBCCCCCC111110. */
+{ "asrs", 0x280B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asrs<.f><.cc> b,b,c 00101bbb11001011FBBBCCCCCC0QQQQQ. */
+{ "asrs", 0x28CB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* asrs<.f> a,b,u6 00101bbb01001011FBBBuuuuuuAAAAAA. */
+{ "asrs", 0x284B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* asrs<.f> 0,b,u6 00101bbb01001011FBBBuuuuuu111110. */
+{ "asrs", 0x284B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asrs<.f><.cc> b,b,u6 00101bbb11001011FBBBuuuuuu1QQQQQ. */
+{ "asrs", 0x28CB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrs<.f> b,b,s12 00101bbb10001011FBBBssssssSSSSSS. */
+{ "asrs", 0x288B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* asrs<.f> a,limm,c 0010111000001011F111CCCCCCAAAAAA. */
+{ "asrs", 0x2E0B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* asrs<.f> a,b,limm 00101bbb00001011FBBB111110AAAAAA. */
+{ "asrs", 0x280B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* asrs<.f> 0,limm,c 0010111000001011F111CCCCCC111110. */
+{ "asrs", 0x2E0B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asrs<.f> 0,b,limm 00101bbb00001011FBBB111110111110. */
+{ "asrs", 0x280B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asrs<.f><.cc> b,b,limm 00101bbb11001011FBBB1111100QQQQQ. */
+{ "asrs", 0x28CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asrs<.f><.cc> 0,limm,c 0010111011001011F111CCCCCC0QQQQQ. */
+{ "asrs", 0x2ECB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asrs<.f> a,limm,u6 0010111001001011F111uuuuuuAAAAAA. */
+{ "asrs", 0x2E4B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrs<.f> 0,limm,u6 0010111001001011F111uuuuuu111110. */
+{ "asrs", 0x2E4B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrs<.f><.cc> 0,limm,u6 0010111011001011F111uuuuuu1QQQQQ. */
+{ "asrs", 0x2ECB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrs<.f> 0,limm,s12 0010111010001011F111ssssssSSSSSS. */
+{ "asrs", 0x2E8B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asrs<.f> a,limm,limm 0010111000001011F111111110AAAAAA. */
+{ "asrs", 0x2E0B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* asrs<.f> 0,limm,limm 0010111000001011F111111110111110. */
+{ "asrs", 0x2E0B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asrs<.f><.cc> 0,limm,limm 0010111011001011F1111111100QQQQQ. */
+{ "asrs", 0x2ECB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asrsr<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA. */
+{ "asrsr", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* asrsr<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110. */
+{ "asrsr", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* asrsr<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ. */
+{ "asrsr", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* asrsr<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA. */
+{ "asrsr", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* asrsr<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110. */
+{ "asrsr", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* asrsr<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ. */
+{ "asrsr", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrsr<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS. */
+{ "asrsr", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* asrsr<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA. */
+{ "asrsr", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* asrsr<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA. */
+{ "asrsr", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* asrsr<.f> 0,limm,c 0010111000001100F111CCCCCC111110. */
+{ "asrsr", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* asrsr<.f> 0,b,limm 00101bbb00001100FBBB111110111110. */
+{ "asrsr", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* asrsr<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ. */
+{ "asrsr", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* asrsr<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ. */
+{ "asrsr", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* asrsr<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA. */
+{ "asrsr", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrsr<.f> 0,limm,u6 0010111001001100F111uuuuuu111110. */
+{ "asrsr", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* asrsr<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ. */
+{ "asrsr", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* asrsr<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS. */
+{ "asrsr", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* asrsr<.f> a,limm,limm 0010111000001100F111111110AAAAAA. */
+{ "asrsr", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* asrsr<.f> 0,limm,limm 0010111000001100F111111110111110. */
+{ "asrsr", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* asrsr<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ. */
+{ "asrsr", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* asr_s b,c 01111bbbccc11100. */
+{ "asr_s", 0x0000781C, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* asr_s b,b,c 01111bbbccc11010. */
+{ "asr_s", 0x0000781A, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* asr_s c,b,u3 01101bbbccc11uuu. */
+{ "asr_s", 0x00006818, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+
+/* asr_s b,b,u5 10111bbb010uuuuu. */
+{ "asr_s", 0x0000B840, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* atld<.op><.aq> RB,RC 00100bbb00101111FBBBcccccc110OOO. */
+{ "atld", 0x202F0030, 0xF8FF0038, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_ATOP, C_AQ }},
+
+/* atldl_add<.aq> RB,RC 01011bbb00101111FBBBcccccc110000. */
+{ "atldl", 0x582F0030, 0xF8FF0038, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_ATOP, C_AQ }},
+
+/* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
+{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM25_A16_5 }, { C_D }},
+
+/* b<.d><cc> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ. */
+{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM21_A16_5 }, { C_CC, C_D }},
+
+/* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00110. */
+{ "bbit0", 0x08010006, 0xF801001F, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* bbit0<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10110. */
+{ "bbit0", 0x08010016, 0xF801001F, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* bbit0 b,limm,s9 00001bbbsssssss1SBBB111110000110. */
+{ "bbit0", 0x08010F86, 0xF8010FFF, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0 limm,c,s9 00001110sssssss1S111CCCCCC000110. */
+{ "bbit0", 0x0E017006, 0xFF01703F, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0 limm,u6,s9 00001110sssssss1S111uuuuuu010110. */
+{ "bbit0", 0x0E017016, 0xFF01703F, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0 limm,limm,s9 00001110sssssss1S111111110000110. */
+{ "bbit0", 0x0E017F86, 0xFF017FFF, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0l<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */
+{ "bbit0l", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* bbit0l<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11110. */
+{ "bbit0l", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* bbit0l b,limm,s9 00001bbbsssssss1SBBB111110001110. */
+{ "bbit0l", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC64, BBIT0, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0l limm,c,s9 00001110sssssss1S111CCCCCC001110. */
+{ "bbit0l", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0l limm,u6,s9 00001110sssssss1S111uuuuuu011110. */
+{ "bbit0l", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* bbit0l limm,limm,s9 00001110sssssss1S111111110001110. */
+{ "bbit0l", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC64, BBIT0, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00111. */
+{ "bbit1", 0x08010007, 0xF801001F, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* bbit1<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10111. */
+{ "bbit1", 0x08010017, 0xF801001F, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* bbit1 b,limm,s9 00001bbbsssssss1SBBB111110000111. */
+{ "bbit1", 0x08010F87, 0xF8010FFF, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1 limm,c,s9 00001110sssssss1S111CCCCCC000111. */
+{ "bbit1", 0x0E017007, 0xFF01703F, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1 limm,u6,s9 00001110sssssss1S111uuuuuu010111. */
+{ "bbit1", 0x0E017017, 0xFF01703F, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1 limm,limm,s9 00001110sssssss1S111111110000111. */
+{ "bbit1", 0x0E017F87, 0xFF017FFF, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1l<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01111. */
+{ "bbit1l", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* bbit1l<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11111. */
+{ "bbit1l", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* bbit1l b,limm,s9 00001bbbsssssss1SBBB111110001111. */
+{ "bbit1l", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC64, BBIT1, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1l limm,c,s9 00001110sssssss1S111CCCCCC001111. */
+{ "bbit1l", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1l limm,u6,s9 00001110sssssss1S111uuuuuu011111. */
+{ "bbit1l", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* bbit1l limm,limm,s9 00001110sssssss1S111111110001111. */
+{ "bbit1l", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC64, BBIT1, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+
+/* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA. */
+{ "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bclr<.f> 0,b,c 00100bbb00010000FBBBCCCCCC111110. */
+{ "bclr", 0x2010003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bclr<.f><.cc> b,b,c 00100bbb11010000FBBBCCCCCC0QQQQQ. */
+{ "bclr", 0x20D00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bclr<.f> a,b,u6 00100bbb01010000FBBBuuuuuuAAAAAA. */
+{ "bclr", 0x20500000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bclr<.f> 0,b,u6 00100bbb01010000FBBBuuuuuu111110. */
+{ "bclr", 0x2050003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bclr<.f><.cc> b,b,u6 00100bbb11010000FBBBuuuuuu1QQQQQ. */
+{ "bclr", 0x20D00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclr<.f> b,b,s12 00100bbb10010000FBBBssssssSSSSSS. */
+{ "bclr", 0x20900000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bclr<.f> a,limm,c 0010011000010000F111CCCCCCAAAAAA. */
+{ "bclr", 0x26107000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bclr<.f> a,b,limm 00100bbb00010000FBBB111110AAAAAA. */
+{ "bclr", 0x20100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bclr<.f> 0,limm,c 0010011000010000F111CCCCCC111110. */
+{ "bclr", 0x2610703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bclr<.f> 0,b,limm 00100bbb00010000FBBB111110111110. */
+{ "bclr", 0x20100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bclr<.f><.cc> b,b,limm 00100bbb11010000FBBB1111100QQQQQ. */
+{ "bclr", 0x20D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bclr<.f><.cc> 0,limm,c 0010011011010000F111CCCCCC0QQQQQ. */
+{ "bclr", 0x26D07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bclr<.f> a,limm,u6 0010011001010000F111uuuuuuAAAAAA. */
+{ "bclr", 0x26507000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bclr<.f> 0,limm,u6 0010011001010000F111uuuuuu111110. */
+{ "bclr", 0x2650703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bclr<.f><.cc> 0,limm,u6 0010011011010000F111uuuuuu1QQQQQ. */
+{ "bclr", 0x26D07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclr<.f> 0,limm,s12 0010011010010000F111ssssssSSSSSS. */
+{ "bclr", 0x26907000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bclr<.f> a,limm,limm 0010011000010000F111111110AAAAAA. */
+{ "bclr", 0x26107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bclr<.f> 0,limm,limm 0010011000010000F111111110111110. */
+{ "bclr", 0x26107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bclr<.f><.cc> 0,limm,limm 0010011011010000F1111111100QQQQQ. */
+{ "bclr", 0x26D07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,RB,RC 01011bbb00010000FBBBccccccaaaaaa. */
+{ "bclrl", 0x58100000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bclrl<.f> 0,RB,RC 01011bbb00010000FBBBcccccc111110. */
+{ "bclrl", 0x5810003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bclrl<.f><.cc> RB,RB,RC 01011bbb11010000FBBBcccccc0QQQQQ. */
+{ "bclrl", 0x58D00000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,RB,u6 01011bbb01010000FBBBuuuuuuaaaaaa. */
+{ "bclrl", 0x58500000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f> 0,RB,u6 01011bbb01010000FBBBuuuuuu111110. */
+{ "bclrl", 0x5850003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f><.cc> RB,RB,u6 01011bbb11010000FBBBuuuuuu1QQQQQ. */
+{ "bclrl", 0x58D00020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclrl<.f> RB,RB,s12 01011bbb10010000FBBBssssssSSSSSS. */
+{ "bclrl", 0x58900000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bclrl<.f> RA,ximm,RC 0101110000010000F111ccccccaaaaaa. */
+{ "bclrl", 0x5C107000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bclrl<.f> RA,RB,ximm 01011bbb00010000FBBB111100aaaaaa. */
+{ "bclrl", 0x58100F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bclrl<.f> 0,ximm,RC 0101110000010000F111cccccc111110. */
+{ "bclrl", 0x5C10703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bclrl<.f> 0,RB,ximm 01011bbb00010000FBBB111100111110. */
+{ "bclrl", 0x58100F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bclrl<.f><.cc> 0,ximm,RC 0101110011010000F111cccccc0QQQQQ. */
+{ "bclrl", 0x5CD07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bclrl<.f><.cc> RB,RB,ximm 01011bbb11010000FBBB1111000QQQQQ. */
+{ "bclrl", 0x58D00F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,ximm,u6 0101110001010000F111uuuuuuaaaaaa. */
+{ "bclrl", 0x5C507000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f> 0,ximm,u6 0101110001010000F111uuuuuu111110. */
+{ "bclrl", 0x5C50703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f><.cc> 0,ximm,u6 0101110011010000F111uuuuuu1QQQQQ. */
+{ "bclrl", 0x5CD07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,limm,RC 0101111000010000F111ccccccaaaaaa. */
+{ "bclrl", 0x5E107000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bclrl<.f> RA,RB,limm 01011bbb00010000FBBB111110aaaaaa. */
+{ "bclrl", 0x58100F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bclrl<.f> 0,limm,RC 0101111000010000F111cccccc111110. */
+{ "bclrl", 0x5E10703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bclrl<.f> 0,RB,limm 01011bbb00010000FBBB111110111110. */
+{ "bclrl", 0x58100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bclrl<.f><.cc> 0,limm,RC 0101111011010000F111cccccc0QQQQQ. */
+{ "bclrl", 0x5ED07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bclrl<.f><.cc> RB,RB,limm 01011bbb11010000FBBB1111100QQQQQ. */
+{ "bclrl", 0x58D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,limm,u6 0101111001010000F111uuuuuuaaaaaa. */
+{ "bclrl", 0x5E507000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f> 0,limm,u6 0101111001010000F111uuuuuu111110. */
+{ "bclrl", 0x5E50703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bclrl<.f><.cc> 0,limm,u6 0101111011010000F111uuuuuu1QQQQQ. */
+{ "bclrl", 0x5ED07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bclrl<.f> 0,ximm,s12 0101110010010000F111ssssssSSSSSS. */
+{ "bclrl", 0x5C907000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bclrl<.f> 0,limm,s12 0101111010010000F111ssssssSSSSSS. */
+{ "bclrl", 0x5E907000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bclrl<.f> RA,ximm,ximm 0101110000010000F111111100aaaaaa. */
+{ "bclrl", 0x5C107F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bclrl<.f> 0,ximm,ximm 0101110000010000F111111100111110. */
+{ "bclrl", 0x5C107F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bclrl<.f><.cc> 0,ximm,ximm 0101110011010000F1111111000QQQQQ. */
+{ "bclrl", 0x5CD07F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bclrl<.f> RA,limm,limm 0101111000010000F111111110aaaaaa. */
+{ "bclrl", 0x5E107F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bclrl<.f> 0,limm,limm 0101111000010000F111111110111110. */
+{ "bclrl", 0x5E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bclrl<.f><.cc> 0,limm,limm 0101111011010000F1111111100QQQQQ. */
+{ "bclrl", 0x5ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bclr_s b,b,u5 10111bbb101uuuuu. */
+{ "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* beq_sCC_EQ s10 1111001sssssssss. */
+{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM10_A16_7_S }, { C_CC_EQ }},
+
+/* bge_sCC_GE s7 1111011001ssssss. */
+{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_GE }},
+
+/* bgt_sCC_GT s7 1111011000ssssss. */
+{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_GT }},
+
+/* bhi_sCC_HI s7 1111011100ssssss. */
+{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_HI }},
+
+/* bhs_sCC_HS s7 1111011101ssssss. */
+{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_HS }},
+
+/* bi c 00100RRR001001000RRRCCCCCCRRRRRR. */
+{ "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BI, CD1, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* bi limm 00100RRR001001000RRR111110RRRRRR. */
+{ "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BI, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* bic<.f> a,b,c 00100bbb00000110FBBBCCCCCCAAAAAA. */
+{ "bic", 0x20060000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bic<.f> 0,b,c 00100bbb00000110FBBBCCCCCC111110. */
+{ "bic", 0x2006003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bic<.f><.cc> b,b,c 00100bbb11000110FBBBCCCCCC0QQQQQ. */
+{ "bic", 0x20C60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bic<.f> a,b,u6 00100bbb01000110FBBBuuuuuuAAAAAA. */
+{ "bic", 0x20460000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bic<.f> 0,b,u6 00100bbb01000110FBBBuuuuuu111110. */
+{ "bic", 0x2046003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bic<.f><.cc> b,b,u6 00100bbb11000110FBBBuuuuuu1QQQQQ. */
+{ "bic", 0x20C60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bic<.f> b,b,s12 00100bbb10000110FBBBssssssSSSSSS. */
+{ "bic", 0x20860000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bic<.f> a,limm,c 0010011000000110F111CCCCCCAAAAAA. */
+{ "bic", 0x26067000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bic<.f> a,b,limm 00100bbb00000110FBBB111110AAAAAA. */
+{ "bic", 0x20060F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bic<.f> 0,limm,c 0010011000000110F111CCCCCC111110. */
+{ "bic", 0x2606703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bic<.f> 0,b,limm 00100bbb00000110FBBB111110111110. */
+{ "bic", 0x20060FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bic<.f><.cc> b,b,limm 00100bbb11000110FBBB1111100QQQQQ. */
+{ "bic", 0x20C60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bic<.f><.cc> 0,limm,c 0010011011000110F111CCCCCC0QQQQQ. */
+{ "bic", 0x26C67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bic<.f> a,limm,u6 0010011001000110F111uuuuuuAAAAAA. */
+{ "bic", 0x26467000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bic<.f> 0,limm,u6 0010011001000110F111uuuuuu111110. */
+{ "bic", 0x2646703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bic<.f><.cc> 0,limm,u6 0010011011000110F111uuuuuu1QQQQQ. */
+{ "bic", 0x26C67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bic<.f> 0,limm,s12 0010011010000110F111ssssssSSSSSS. */
+{ "bic", 0x26867000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bic<.f> a,limm,limm 0010011000000110F111111110AAAAAA. */
+{ "bic", 0x26067F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bic<.f> 0,limm,limm 0010011000000110F111111110111110. */
+{ "bic", 0x26067FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bic<.f><.cc> 0,limm,limm 0010011011000110F1111111100QQQQQ. */
+{ "bic", 0x26C67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bicl<.f> RA,RB,RC 01011bbb00000110FBBBccccccaaaaaa. */
+{ "bicl", 0x58060000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bicl<.f> 0,RB,RC 01011bbb00000110FBBBcccccc111110. */
+{ "bicl", 0x5806003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bicl<.f><.cc> RB,RB,RC 01011bbb11000110FBBBcccccc0QQQQQ. */
+{ "bicl", 0x58C60000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bicl<.f> RA,RB,u6 01011bbb01000110FBBBuuuuuuaaaaaa. */
+{ "bicl", 0x58460000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bicl<.f> 0,RB,u6 01011bbb01000110FBBBuuuuuu111110. */
+{ "bicl", 0x5846003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bicl<.f><.cc> RB,RB,u6 01011bbb11000110FBBBuuuuuu1QQQQQ. */
+{ "bicl", 0x58C60020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bicl<.f> RB,RB,s12 01011bbb10000110FBBBssssssSSSSSS. */
+{ "bicl", 0x58860000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bicl<.f> RA,ximm,RC 0101110000000110F111ccccccaaaaaa. */
+{ "bicl", 0x5C067000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bicl<.f> RA,RB,ximm 01011bbb00000110FBBB111100aaaaaa. */
+{ "bicl", 0x58060F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bicl<.f> 0,ximm,RC 0101110000000110F111cccccc111110. */
+{ "bicl", 0x5C06703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bicl<.f> 0,RB,ximm 01011bbb00000110FBBB111100111110. */
+{ "bicl", 0x58060F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bicl<.f><.cc> 0,ximm,RC 0101110011000110F111cccccc0QQQQQ. */
+{ "bicl", 0x5CC67000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bicl<.f><.cc> RB,RB,ximm 01011bbb11000110FBBB1111000QQQQQ. */
+{ "bicl", 0x58C60F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bicl<.f> RA,ximm,u6 0101110001000110F111uuuuuuaaaaaa. */
+{ "bicl", 0x5C467000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bicl<.f> 0,ximm,u6 0101110001000110F111uuuuuu111110. */
+{ "bicl", 0x5C46703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bicl<.f><.cc> 0,ximm,u6 0101110011000110F111uuuuuu1QQQQQ. */
+{ "bicl", 0x5CC67020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bicl<.f> RA,limm,RC 0101111000000110F111ccccccaaaaaa. */
+{ "bicl", 0x5E067000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bicl<.f> RA,RB,limm 01011bbb00000110FBBB111110aaaaaa. */
+{ "bicl", 0x58060F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bicl<.f> 0,limm,RC 0101111000000110F111cccccc111110. */
+{ "bicl", 0x5E06703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bicl<.f> 0,RB,limm 01011bbb00000110FBBB111110111110. */
+{ "bicl", 0x58060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bicl<.f><.cc> 0,limm,RC 0101111011000110F111cccccc0QQQQQ. */
+{ "bicl", 0x5EC67000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bicl<.f><.cc> RB,RB,limm 01011bbb11000110FBBB1111100QQQQQ. */
+{ "bicl", 0x58C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bicl<.f> RA,limm,u6 0101111001000110F111uuuuuuaaaaaa. */
+{ "bicl", 0x5E467000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bicl<.f> 0,limm,u6 0101111001000110F111uuuuuu111110. */
+{ "bicl", 0x5E46703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bicl<.f><.cc> 0,limm,u6 0101111011000110F111uuuuuu1QQQQQ. */
+{ "bicl", 0x5EC67020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bicl<.f> 0,ximm,s12 0101110010000110F111ssssssSSSSSS. */
+{ "bicl", 0x5C867000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bicl<.f> 0,limm,s12 0101111010000110F111ssssssSSSSSS. */
+{ "bicl", 0x5E867000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bicl<.f> RA,ximm,ximm 0101110000000110F111111100aaaaaa. */
+{ "bicl", 0x5C067F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bicl<.f> 0,ximm,ximm 0101110000000110F111111100111110. */
+{ "bicl", 0x5C067F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bicl<.f><.cc> 0,ximm,ximm 0101110011000110F1111111000QQQQQ. */
+{ "bicl", 0x5CC67F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bicl<.f> RA,limm,limm 0101111000000110F111111110aaaaaa. */
+{ "bicl", 0x5E067F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bicl<.f> 0,limm,limm 0101111000000110F111111110111110. */
+{ "bicl", 0x5E067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bicl<.f><.cc> 0,limm,limm 0101111011000110F1111111100QQQQQ. */
+{ "bicl", 0x5EC67F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bic_s b,b,c 01111bbbccc00110. */
+{ "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* bih c 00100RRR001001010RRRCCCCCCRRRRRR. */
+{ "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BIH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* bih limm 00100RRR001001010RRR111110RRRRRR. */
+{ "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BIH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
+{ "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM25_A32_5 }, { C_D }},
+
+/* bl<.d><.cc> s21 00001sssssssss00SSSSSSSSSSNQQQQQ. */
+{ "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM21_A32_5 }, { C_CC, C_D }},
+
+/* ble_sCC_LE s7 1111011011ssssss. */
+{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LE }},
+
+/* blo_sCC_LO s7 1111011110ssssss. */
+{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LO }},
+
+/* bls_sCC_LS s7 1111011111ssssss. */
+{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LS }},
+
+/* blt_sCC_LT s7 1111011010ssssss. */
+{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM7_A16_10_S }, { C_CC_LT }},
+
+/* bl_s s13 11111sssssssssss. */
+{ "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM13_A32_5_S }, { 0 }},
+
+/* bmsk<.f> a,b,c 00100bbb00010011FBBBCCCCCCAAAAAA. */
+{ "bmsk", 0x20130000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bmsk<.f> 0,b,c 00100bbb00010011FBBBCCCCCC111110. */
+{ "bmsk", 0x2013003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bmsk<.f><.cc> b,b,c 00100bbb11010011FBBBCCCCCC0QQQQQ. */
+{ "bmsk", 0x20D30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bmsk<.f> a,b,u6 00100bbb01010011FBBBuuuuuuAAAAAA. */
+{ "bmsk", 0x20530000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f> 0,b,u6 00100bbb01010011FBBBuuuuuu111110. */
+{ "bmsk", 0x2053003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f><.cc> b,b,u6 00100bbb11010011FBBBuuuuuu1QQQQQ. */
+{ "bmsk", 0x20D30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsk<.f> b,b,s12 00100bbb10010011FBBBssssssSSSSSS. */
+{ "bmsk", 0x20930000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bmsk<.f> a,limm,c 0010011000010011F111CCCCCCAAAAAA. */
+{ "bmsk", 0x26137000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bmsk<.f> a,b,limm 00100bbb00010011FBBB111110AAAAAA. */
+{ "bmsk", 0x20130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bmsk<.f> 0,limm,c 0010011000010011F111CCCCCC111110. */
+{ "bmsk", 0x2613703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bmsk<.f> 0,b,limm 00100bbb00010011FBBB111110111110. */
+{ "bmsk", 0x20130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bmsk<.f><.cc> b,b,limm 00100bbb11010011FBBB1111100QQQQQ. */
+{ "bmsk", 0x20D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bmsk<.f><.cc> 0,limm,c 0010011011010011F111CCCCCC0QQQQQ. */
+{ "bmsk", 0x26D37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bmsk<.f> a,limm,u6 0010011001010011F111uuuuuuAAAAAA. */
+{ "bmsk", 0x26537000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f> 0,limm,u6 0010011001010011F111uuuuuu111110. */
+{ "bmsk", 0x2653703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmsk<.f><.cc> 0,limm,u6 0010011011010011F111uuuuuu1QQQQQ. */
+{ "bmsk", 0x26D37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsk<.f> 0,limm,s12 0010011010010011F111ssssssSSSSSS. */
+{ "bmsk", 0x26937000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bmsk<.f> a,limm,limm 0010011000010011F111111110AAAAAA. */
+{ "bmsk", 0x26137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bmsk<.f> 0,limm,limm 0010011000010011F111111110111110. */
+{ "bmsk", 0x26137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bmsk<.f><.cc> 0,limm,limm 0010011011010011F1111111100QQQQQ. */
+{ "bmsk", 0x26D37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,RB,RC 01011bbb00010011FBBBccccccaaaaaa. */
+{ "bmskl", 0x58130000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bmskl<.f> 0,RB,RC 01011bbb00010011FBBBcccccc111110. */
+{ "bmskl", 0x5813003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bmskl<.f><.cc> RB,RB,RC 01011bbb11010011FBBBcccccc0QQQQQ. */
+{ "bmskl", 0x58D30000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,RB,u6 01011bbb01010011FBBBuuuuuuaaaaaa. */
+{ "bmskl", 0x58530000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f> 0,RB,u6 01011bbb01010011FBBBuuuuuu111110. */
+{ "bmskl", 0x5853003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f><.cc> RB,RB,u6 01011bbb11010011FBBBuuuuuu1QQQQQ. */
+{ "bmskl", 0x58D30020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskl<.f> RB,RB,s12 01011bbb10010011FBBBssssssSSSSSS. */
+{ "bmskl", 0x58930000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bmskl<.f> RA,ximm,RC 0101110000010011F111ccccccaaaaaa. */
+{ "bmskl", 0x5C137000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bmskl<.f> RA,RB,ximm 01011bbb00010011FBBB111100aaaaaa. */
+{ "bmskl", 0x58130F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bmskl<.f> 0,ximm,RC 0101110000010011F111cccccc111110. */
+{ "bmskl", 0x5C13703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bmskl<.f> 0,RB,ximm 01011bbb00010011FBBB111100111110. */
+{ "bmskl", 0x58130F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bmskl<.f><.cc> 0,ximm,RC 0101110011010011F111cccccc0QQQQQ. */
+{ "bmskl", 0x5CD37000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bmskl<.f><.cc> RB,RB,ximm 01011bbb11010011FBBB1111000QQQQQ. */
+{ "bmskl", 0x58D30F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,ximm,u6 0101110001010011F111uuuuuuaaaaaa. */
+{ "bmskl", 0x5C537000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f> 0,ximm,u6 0101110001010011F111uuuuuu111110. */
+{ "bmskl", 0x5C53703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f><.cc> 0,ximm,u6 0101110011010011F111uuuuuu1QQQQQ. */
+{ "bmskl", 0x5CD37020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,limm,RC 0101111000010011F111ccccccaaaaaa. */
+{ "bmskl", 0x5E137000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bmskl<.f> RA,RB,limm 01011bbb00010011FBBB111110aaaaaa. */
+{ "bmskl", 0x58130F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bmskl<.f> 0,limm,RC 0101111000010011F111cccccc111110. */
+{ "bmskl", 0x5E13703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bmskl<.f> 0,RB,limm 01011bbb00010011FBBB111110111110. */
+{ "bmskl", 0x58130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bmskl<.f><.cc> 0,limm,RC 0101111011010011F111cccccc0QQQQQ. */
+{ "bmskl", 0x5ED37000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bmskl<.f><.cc> RB,RB,limm 01011bbb11010011FBBB1111100QQQQQ. */
+{ "bmskl", 0x58D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,limm,u6 0101111001010011F111uuuuuuaaaaaa. */
+{ "bmskl", 0x5E537000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f> 0,limm,u6 0101111001010011F111uuuuuu111110. */
+{ "bmskl", 0x5E53703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmskl<.f><.cc> 0,limm,u6 0101111011010011F111uuuuuu1QQQQQ. */
+{ "bmskl", 0x5ED37020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskl<.f> 0,ximm,s12 0101110010010011F111ssssssSSSSSS. */
+{ "bmskl", 0x5C937000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bmskl<.f> 0,limm,s12 0101111010010011F111ssssssSSSSSS. */
+{ "bmskl", 0x5E937000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bmskl<.f> RA,ximm,ximm 0101110000010011F111111100aaaaaa. */
+{ "bmskl", 0x5C137F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bmskl<.f> 0,ximm,ximm 0101110000010011F111111100111110. */
+{ "bmskl", 0x5C137F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bmskl<.f><.cc> 0,ximm,ximm 0101110011010011F1111111000QQQQQ. */
+{ "bmskl", 0x5CD37F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bmskl<.f> RA,limm,limm 0101111000010011F111111110aaaaaa. */
+{ "bmskl", 0x5E137F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bmskl<.f> 0,limm,limm 0101111000010011F111111110111110. */
+{ "bmskl", 0x5E137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bmskl<.f><.cc> 0,limm,limm 0101111011010011F1111111100QQQQQ. */
+{ "bmskl", 0x5ED37F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bmskn<.f> a,b,c 00100bbb00101100FBBBCCCCCCAAAAAA. */
+{ "bmskn", 0x202C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bmskn<.f> 0,b,c 00100bbb00101100FBBBCCCCCC111110. */
+{ "bmskn", 0x202C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bmskn<.f><.cc> b,b,c 00100bbb11101100FBBBCCCCCC0QQQQQ. */
+{ "bmskn", 0x20EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bmskn<.f> a,b,u6 00100bbb01101100FBBBuuuuuuAAAAAA. */
+{ "bmskn", 0x206C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f> 0,b,u6 00100bbb01101100FBBBuuuuuu111110. */
+{ "bmskn", 0x206C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f><.cc> b,b,u6 00100bbb11101100FBBBuuuuuu1QQQQQ. */
+{ "bmskn", 0x20EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskn<.f> b,b,s12 00100bbb10101100FBBBssssssSSSSSS. */
+{ "bmskn", 0x20AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bmskn<.f> a,limm,c 0010011000101100F111CCCCCCAAAAAA. */
+{ "bmskn", 0x262C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bmskn<.f> a,b,limm 00100bbb00101100FBBB111110AAAAAA. */
+{ "bmskn", 0x202C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bmskn<.f> 0,limm,c 0010011000101100F111CCCCCC111110. */
+{ "bmskn", 0x262C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bmskn<.f> 0,b,limm 00100bbb00101100FBBB111110111110. */
+{ "bmskn", 0x202C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bmskn<.f><.cc> b,b,limm 00100bbb11101100FBBB1111100QQQQQ. */
+{ "bmskn", 0x20EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bmskn<.f><.cc> 0,limm,c 0010011011101100F111CCCCCC0QQQQQ. */
+{ "bmskn", 0x26EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bmskn<.f> a,limm,u6 0010011001101100F111uuuuuuAAAAAA. */
+{ "bmskn", 0x266C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f> 0,limm,u6 0010011001101100F111uuuuuu111110. */
+{ "bmskn", 0x266C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmskn<.f><.cc> 0,limm,u6 0010011011101100F111uuuuuu1QQQQQ. */
+{ "bmskn", 0x26EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmskn<.f> 0,limm,s12 0010011010101100F111ssssssSSSSSS. */
+{ "bmskn", 0x26AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bmskn<.f> a,limm,limm 0010011000101100F111111110AAAAAA. */
+{ "bmskn", 0x262C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bmskn<.f> 0,limm,limm 0010011000101100F111111110111110. */
+{ "bmskn", 0x262C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bmskn<.f><.cc> 0,limm,limm 0010011011101100F1111111100QQQQQ. */
+{ "bmskn", 0x26EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,RB,RC 01011bbb00101100FBBBccccccaaaaaa. */
+{ "bmsknl", 0x582C0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bmsknl<.f> 0,RB,RC 01011bbb00101100FBBBcccccc111110. */
+{ "bmsknl", 0x582C003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bmsknl<.f><.cc> RB,RB,RC 01011bbb11101100FBBBcccccc0QQQQQ. */
+{ "bmsknl", 0x58EC0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,RB,u6 01011bbb01101100FBBBuuuuuuaaaaaa. */
+{ "bmsknl", 0x586C0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f> 0,RB,u6 01011bbb01101100FBBBuuuuuu111110. */
+{ "bmsknl", 0x586C003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f><.cc> RB,RB,u6 01011bbb11101100FBBBuuuuuu1QQQQQ. */
+{ "bmsknl", 0x58EC0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsknl<.f> RB,RB,s12 01011bbb10101100FBBBssssssSSSSSS. */
+{ "bmsknl", 0x58AC0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bmsknl<.f> RA,ximm,RC 0101110000101100F111ccccccaaaaaa. */
+{ "bmsknl", 0x5C2C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bmsknl<.f> RA,RB,ximm 01011bbb00101100FBBB111100aaaaaa. */
+{ "bmsknl", 0x582C0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bmsknl<.f> 0,ximm,RC 0101110000101100F111cccccc111110. */
+{ "bmsknl", 0x5C2C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bmsknl<.f> 0,RB,ximm 01011bbb00101100FBBB111100111110. */
+{ "bmsknl", 0x582C0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,ximm,RC 0101110011101100F111cccccc0QQQQQ. */
+{ "bmsknl", 0x5CEC7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bmsknl<.f><.cc> RB,RB,ximm 01011bbb11101100FBBB1111000QQQQQ. */
+{ "bmsknl", 0x58EC0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,ximm,u6 0101110001101100F111uuuuuuaaaaaa. */
+{ "bmsknl", 0x5C6C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f> 0,ximm,u6 0101110001101100F111uuuuuu111110. */
+{ "bmsknl", 0x5C6C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,ximm,u6 0101110011101100F111uuuuuu1QQQQQ. */
+{ "bmsknl", 0x5CEC7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,limm,RC 0101111000101100F111ccccccaaaaaa. */
+{ "bmsknl", 0x5E2C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bmsknl<.f> RA,RB,limm 01011bbb00101100FBBB111110aaaaaa. */
+{ "bmsknl", 0x582C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bmsknl<.f> 0,limm,RC 0101111000101100F111cccccc111110. */
+{ "bmsknl", 0x5E2C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bmsknl<.f> 0,RB,limm 01011bbb00101100FBBB111110111110. */
+{ "bmsknl", 0x582C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,limm,RC 0101111011101100F111cccccc0QQQQQ. */
+{ "bmsknl", 0x5EEC7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bmsknl<.f><.cc> RB,RB,limm 01011bbb11101100FBBB1111100QQQQQ. */
+{ "bmsknl", 0x58EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,limm,u6 0101111001101100F111uuuuuuaaaaaa. */
+{ "bmsknl", 0x5E6C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f> 0,limm,u6 0101111001101100F111uuuuuu111110. */
+{ "bmsknl", 0x5E6C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,limm,u6 0101111011101100F111uuuuuu1QQQQQ. */
+{ "bmsknl", 0x5EEC7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bmsknl<.f> 0,ximm,s12 0101110010101100F111ssssssSSSSSS. */
+{ "bmsknl", 0x5CAC7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bmsknl<.f> 0,limm,s12 0101111010101100F111ssssssSSSSSS. */
+{ "bmsknl", 0x5EAC7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bmsknl<.f> RA,ximm,ximm 0101110000101100F111111100aaaaaa. */
+{ "bmsknl", 0x5C2C7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bmsknl<.f> 0,ximm,ximm 0101110000101100F111111100111110. */
+{ "bmsknl", 0x5C2C7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,ximm,ximm 0101110011101100F1111111000QQQQQ. */
+{ "bmsknl", 0x5CEC7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bmsknl<.f> RA,limm,limm 0101111000101100F111111110aaaaaa. */
+{ "bmsknl", 0x5E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bmsknl<.f> 0,limm,limm 0101111000101100F111111110111110. */
+{ "bmsknl", 0x5E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bmsknl<.f><.cc> 0,limm,limm 0101111011101100F1111111100QQQQQ. */
+{ "bmsknl", 0x5EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bmsk_s b,b,u5 10111bbb110uuuuu. */
+{ "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* bne_sCC_NE s10 1111010sssssssss. */
+{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, COND, { SIMM10_A16_7_S }, { C_CC_NE }},
+
+/* breq<.d>CC_EQ b,c,s9 00001bbbsssssss1SBBBCCCCCCN00000. */
+{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_EQ }},
+
+/* breq<.d>CC_EQ b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10000. */
+{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_EQ }},
+
+/* breqCC_EQ b,limm,s9 00001bbbsssssss1SBBB111110000000. */
+{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_EQ }},
+
+/* breqCC_EQ limm,c,s9 00001110sssssss1S111CCCCCC000000. */
+{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_EQ }},
+
+/* breqCC_EQ limm,u6,s9 00001110sssssss1S111uuuuuu010000. */
+{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_EQ }},
+
+/* breqCC_EQ limm,limm,s9 00001110sssssss1S111111110000000. */
+{ "breq", 0x0E017F80, 0xFF017FFF, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_EQ }},
+
+/* breql<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01000. */
+{ "breql", 0x08010008, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* breql<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11000. */
+{ "breql", 0x08010018, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* breql b,limm,s9 00001bbbsssssss1SBBB111110001000. */
+{ "breql", 0x08010F88, 0xF8010FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* breql limm,c,s9 00001110sssssss1S111CCCCCC001000. */
+{ "breql", 0x0E017008, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* breql limm,u6,s9 00001110sssssss1S111uuuuuu011000. */
+{ "breql", 0x0E017018, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* breql_s b,0,s8 11101bbb0sssssss. */
+{ "breql_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
+
+/* brge<.d>CC_GE b,c,s9 00001bbbsssssss1SBBBCCCCCCN00011. */
+{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_GE }},
+
+/* brge<.d>CC_GE b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10011. */
+{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_GE }},
+
+/* brgeCC_GE b,limm,s9 00001bbbsssssss1SBBB111110000011. */
+{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_GE }},
+
+/* brgeCC_GE limm,c,s9 00001110sssssss1S111CCCCCC000011. */
+{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_GE }},
+
+/* brgeCC_GE limm,u6,s9 00001110sssssss1S111uuuuuu010011. */
+{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_GE }},
+
+/* brgeCC_GE limm,limm,s9 00001110sssssss1S111111110000011. */
+{ "brge", 0x0E017F83, 0xFF017FFF, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_GE }},
+
+/* brgel<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01011. */
+{ "brgel", 0x0801000B, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brgel<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11011. */
+{ "brgel", 0x0801001B, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brgel b,limm,s9 00001bbbsssssss1SBBB111110001011. */
+{ "brgel", 0x08010F8B, 0xF8010FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brgel limm,c,s9 00001110sssssss1S111CCCCCC001011. */
+{ "brgel", 0x0E01700B, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brgel limm,u6,s9 00001110sssssss1S111uuuuuu011011. */
+{ "brgel", 0x0E01701B, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brhs<.d>CC_HS b,c,s9 00001bbbsssssss1SBBBCCCCCCN00101. */
+{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_HS }},
+
+/* brhs<.d>CC_HS b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10101. */
+{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_HS }},
+
+/* brhsCC_HS b,limm,s9 00001bbbsssssss1SBBB111110000101. */
+{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_HS }},
+
+/* brhsCC_HS limm,c,s9 00001110sssssss1S111CCCCCC000101. */
+{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_HS }},
+
+/* brhsCC_HS limm,u6,s9 00001110sssssss1S111uuuuuu010101. */
+{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_HS }},
+
+/* brhsCC_HS limm,limm,s9 00001110sssssss1S111111110000101. */
+{ "brhs", 0x0E017F85, 0xFF017FFF, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_HS }},
+
+/* brhsl<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01101. */
+{ "brhsl", 0x0801000D, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brhsl<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11101. */
+{ "brhsl", 0x0801001D, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brhsl b,limm,s9 00001bbbsssssss1SBBB111110001101. */
+{ "brhsl", 0x08010F8D, 0xF8010FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brhsl limm,c,s9 00001110sssssss1S111CCCCCC001101. */
+{ "brhsl", 0x0E01700D, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brhsl limm,u6,s9 00001110sssssss1S111uuuuuu011101. */
+{ "brhsl", 0x0E01701D, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brk 00100101011011110000000000111111. */
+{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* brk_s 0111111111111111. */
+{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* brlo<.d>CC_LO b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100. */
+{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LO }},
+
+/* brlo<.d>CC_LO b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10100. */
+{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LO }},
+
+/* brloCC_LO b,limm,s9 00001bbbsssssss1SBBB111110000100. */
+{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LO }},
+
+/* brloCC_LO limm,c,s9 00001110sssssss1S111CCCCCC000100. */
+{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LO }},
+
+/* brloCC_LO limm,u6,s9 00001110sssssss1S111uuuuuu010100. */
+{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LO }},
+
+/* brloCC_LO limm,limm,s9 00001110sssssss1S111111110000100. */
+{ "brlo", 0x0E017F84, 0xFF017FFF, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_LO }},
+
+/* brlol<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01100. */
+{ "brlol", 0x0801000C, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brlol<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11100. */
+{ "brlol", 0x0801001C, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brlol b,limm,s9 00001bbbsssssss1SBBB111110001100. */
+{ "brlol", 0x08010F8C, 0xF8010FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brlol limm,c,s9 00001110sssssss1S111CCCCCC001100. */
+{ "brlol", 0x0E01700C, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brlol limm,u6,s9 00001110sssssss1S111uuuuuu011100. */
+{ "brlol", 0x0E01701C, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brlt<.d>CC_LT b,c,s9 00001bbbsssssss1SBBBCCCCCCN00010. */
+{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_LT }},
+
+/* brlt<.d>CC_LT b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10010. */
+{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_LT }},
+
+/* brltCC_LT b,limm,s9 00001bbbsssssss1SBBB111110000010. */
+{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_LT }},
+
+/* brltCC_LT limm,c,s9 00001110sssssss1S111CCCCCC000010. */
+{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_LT }},
+
+/* brltCC_LT limm,u6,s9 00001110sssssss1S111uuuuuu010010. */
+{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_LT }},
+
+/* brltCC_LT limm,limm,s9 00001110sssssss1S111111110000010. */
+{ "brlt", 0x0E017F82, 0xFF017FFF, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_LT }},
+
+/* brltl<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01010. */
+{ "brltl", 0x0801000A, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brltl<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11010. */
+{ "brltl", 0x0801001A, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brltl b,limm,s9 00001bbbsssssss1SBBB111110001010. */
+{ "brltl", 0x08010F8A, 0xF8010FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brltl limm,c,s9 00001110sssssss1S111CCCCCC001010. */
+{ "brltl", 0x0E01700A, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brltl limm,u6,s9 00001110sssssss1S111uuuuuu011010. */
+{ "brltl", 0x0E01701A, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brne<.d>CC_NE b,c,s9 00001bbbsssssss1SBBBCCCCCCN00001. */
+{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_CC_NE }},
+
+/* brne<.d>CC_NE b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10001. */
+{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC64, BRCC, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_CC_NE }},
+
+/* brneCC_NE b,limm,s9 00001bbbsssssss1SBBB111110000001. */
+{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC64, BRCC, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_CC_NE }},
+
+/* brneCC_NE limm,c,s9 00001110sssssss1S111CCCCCC000001. */
+{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_CC_NE }},
+
+/* brneCC_NE limm,u6,s9 00001110sssssss1S111uuuuuu010001. */
+{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_CC_NE }},
+
+/* brneCC_NE limm,limm,s9 00001110sssssss1S111111110000001. */
+{ "brne", 0x0E017F81, 0xFF017FFF, ARC_OPCODE_ARC64, BRCC, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_CC_NE }},
+
+/* brnel<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01001. */
+{ "brnel", 0x08010009, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+
+/* brnel<.d> b,u6,s9 00001bbbsssssss1SBBBUUUUUUN11001. */
+{ "brnel", 0x08010019, 0xF801001F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+
+/* brnel b,limm,s9 00001bbbsssssss1SBBB111110001001. */
+{ "brnel", 0x08010F89, 0xF8010FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+
+/* brnel limm,c,s9 00001110sssssss1S111CCCCCC001001. */
+{ "brnel", 0x0E017009, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+
+/* brnel limm,u6,s9 00001110sssssss1S111uuuuuu011001. */
+{ "brnel", 0x0E017019, 0xFF01703F, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+
+/* brnel_s b,0,s8 11101bbb1sssssss. */
+{ "brnel_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
+
+/* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA. */
+{ "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bset<.f> 0,b,c 00100bbb00001111FBBBCCCCCC111110. */
+{ "bset", 0x200F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bset<.f><.cc> b,b,c 00100bbb11001111FBBBCCCCCC0QQQQQ. */
+{ "bset", 0x20CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bset<.f> a,b,u6 00100bbb01001111FBBBuuuuuuAAAAAA. */
+{ "bset", 0x204F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bset<.f> 0,b,u6 00100bbb01001111FBBBuuuuuu111110. */
+{ "bset", 0x204F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bset<.f><.cc> b,b,u6 00100bbb11001111FBBBuuuuuu1QQQQQ. */
+{ "bset", 0x20CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bset<.f> b,b,s12 00100bbb10001111FBBBssssssSSSSSS. */
+{ "bset", 0x208F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bset<.f> a,limm,c 0010011000001111F111CCCCCCAAAAAA. */
+{ "bset", 0x260F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bset<.f> a,b,limm 00100bbb00001111FBBB111110AAAAAA. */
+{ "bset", 0x200F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bset<.f> 0,limm,c 0010011000001111F111CCCCCC111110. */
+{ "bset", 0x260F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bset<.f> 0,b,limm 00100bbb00001111FBBB111110111110. */
+{ "bset", 0x200F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bset<.f><.cc> b,b,limm 00100bbb11001111FBBB1111100QQQQQ. */
+{ "bset", 0x20CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bset<.f><.cc> 0,limm,c 0010011011001111F111CCCCCC0QQQQQ. */
+{ "bset", 0x26CF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bset<.f> a,limm,u6 0010011001001111F111uuuuuuAAAAAA. */
+{ "bset", 0x264F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bset<.f> 0,limm,u6 0010011001001111F111uuuuuu111110. */
+{ "bset", 0x264F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bset<.f><.cc> 0,limm,u6 0010011011001111F111uuuuuu1QQQQQ. */
+{ "bset", 0x26CF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bset<.f> 0,limm,s12 0010011010001111F111ssssssSSSSSS. */
+{ "bset", 0x268F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bset<.f> a,limm,limm 0010011000001111F111111110AAAAAA. */
+{ "bset", 0x260F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bset<.f> 0,limm,limm 0010011000001111F111111110111110. */
+{ "bset", 0x260F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bset<.f><.cc> 0,limm,limm 0010011011001111F1111111100QQQQQ. */
+{ "bset", 0x26CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,RB,RC 01011bbb00001111FBBBccccccaaaaaa. */
+{ "bsetl", 0x580F0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bsetl<.f> 0,RB,RC 01011bbb00001111FBBBcccccc111110. */
+{ "bsetl", 0x580F003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bsetl<.f><.cc> RB,RB,RC 01011bbb11001111FBBBcccccc0QQQQQ. */
+{ "bsetl", 0x58CF0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,RB,u6 01011bbb01001111FBBBuuuuuuaaaaaa. */
+{ "bsetl", 0x584F0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f> 0,RB,u6 01011bbb01001111FBBBuuuuuu111110. */
+{ "bsetl", 0x584F003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f><.cc> RB,RB,u6 01011bbb11001111FBBBuuuuuu1QQQQQ. */
+{ "bsetl", 0x58CF0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bsetl<.f> RB,RB,s12 01011bbb10001111FBBBssssssSSSSSS. */
+{ "bsetl", 0x588F0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bsetl<.f> RA,ximm,RC 0101110000001111F111ccccccaaaaaa. */
+{ "bsetl", 0x5C0F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bsetl<.f> RA,RB,ximm 01011bbb00001111FBBB111100aaaaaa. */
+{ "bsetl", 0x580F0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bsetl<.f> 0,ximm,RC 0101110000001111F111cccccc111110. */
+{ "bsetl", 0x5C0F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bsetl<.f> 0,RB,ximm 01011bbb00001111FBBB111100111110. */
+{ "bsetl", 0x580F0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bsetl<.f><.cc> 0,ximm,RC 0101110011001111F111cccccc0QQQQQ. */
+{ "bsetl", 0x5CCF7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bsetl<.f><.cc> RB,RB,ximm 01011bbb11001111FBBB1111000QQQQQ. */
+{ "bsetl", 0x58CF0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,ximm,u6 0101110001001111F111uuuuuuaaaaaa. */
+{ "bsetl", 0x5C4F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f> 0,ximm,u6 0101110001001111F111uuuuuu111110. */
+{ "bsetl", 0x5C4F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f><.cc> 0,ximm,u6 0101110011001111F111uuuuuu1QQQQQ. */
+{ "bsetl", 0x5CCF7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,limm,RC 0101111000001111F111ccccccaaaaaa. */
+{ "bsetl", 0x5E0F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bsetl<.f> RA,RB,limm 01011bbb00001111FBBB111110aaaaaa. */
+{ "bsetl", 0x580F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bsetl<.f> 0,limm,RC 0101111000001111F111cccccc111110. */
+{ "bsetl", 0x5E0F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bsetl<.f> 0,RB,limm 01011bbb00001111FBBB111110111110. */
+{ "bsetl", 0x580F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bsetl<.f><.cc> 0,limm,RC 0101111011001111F111cccccc0QQQQQ. */
+{ "bsetl", 0x5ECF7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bsetl<.f><.cc> RB,RB,limm 01011bbb11001111FBBB1111100QQQQQ. */
+{ "bsetl", 0x58CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,limm,u6 0101111001001111F111uuuuuuaaaaaa. */
+{ "bsetl", 0x5E4F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f> 0,limm,u6 0101111001001111F111uuuuuu111110. */
+{ "bsetl", 0x5E4F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bsetl<.f><.cc> 0,limm,u6 0101111011001111F111uuuuuu1QQQQQ. */
+{ "bsetl", 0x5ECF7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bsetl<.f> 0,ximm,s12 0101110010001111F111ssssssSSSSSS. */
+{ "bsetl", 0x5C8F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bsetl<.f> 0,limm,s12 0101111010001111F111ssssssSSSSSS. */
+{ "bsetl", 0x5E8F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bsetl<.f> RA,ximm,ximm 0101110000001111F111111100aaaaaa. */
+{ "bsetl", 0x5C0F7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bsetl<.f> 0,ximm,ximm 0101110000001111F111111100111110. */
+{ "bsetl", 0x5C0F7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bsetl<.f><.cc> 0,ximm,ximm 0101110011001111F1111111000QQQQQ. */
+{ "bsetl", 0x5CCF7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bsetl<.f> RA,limm,limm 0101111000001111F111111110aaaaaa. */
+{ "bsetl", 0x5E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bsetl<.f> 0,limm,limm 0101111000001111F111111110111110. */
+{ "bsetl", 0x5E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bsetl<.f><.cc> 0,limm,limm 0101111011001111F1111111100QQQQQ. */
+{ "bsetl", 0x5ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bset_s b,b,u5 10111bbb100uuuuu. */
+{ "bset_s", 0x0000B880, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* btst b,c 00100bbb000100011BBBCCCCCCRRRRRR. */
+{ "btst", 0x20118000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { 0 }},
+
+/* btst<.cc> b,c 00100bbb110100011BBBCCCCCC0QQQQQ. */
+{ "btst", 0x20D18000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_CC }},
+
+/* btst b,u6 00100bbb010100011BBBuuuuuuRRRRRR. */
+{ "btst", 0x20518000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* btst<.cc> b,u6 00100bbb110100011BBBuuuuuu1QQQQQ. */
+{ "btst", 0x20D18020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* btst b,s12 00100bbb100100011BBBssssssSSSSSS. */
+{ "btst", 0x20918000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* btst limm,c 00100110000100011111CCCCCCRRRRRR. */
+{ "btst", 0x2611F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, RC }, { 0 }},
+
+/* btst b,limm 00100bbb000100011BBB111110RRRRRR. */
+{ "btst", 0x20118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { 0 }},
+
+/* btst<.cc> b,limm 00100bbb110100011BBB1111100QQQQQ. */
+{ "btst", 0x20D18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_CC }},
+
+/* btst<.cc> limm,c 00100110110100011111CCCCCC0QQQQQ. */
+{ "btst", 0x26D1F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, RC }, { C_CC }},
+
+/* btst limm,u6 00100110010100011111uuuuuuRRRRRR. */
+{ "btst", 0x2651F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* btst<.cc> limm,u6 00100110110100011111uuuuuu1QQQQQ. */
+{ "btst", 0x26D1F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* btst limm,s12 00100110100100011111ssssssSSSSSS. */
+{ "btst", 0x2691F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* btst limm,limm 00100110000100011111111110RRRRRR. */
+{ "btst", 0x2611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* btst<.cc> limm,limm 001001101101000111111111100QQQQQ. */
+{ "btst", 0x26D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* btstl RB,RC 01011bbb000100011BBBccccccRRRRRR. */
+{ "btstl", 0x58118000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* btstl<.cc> RB,RC 01011bbb110100011BBBcccccc0QQQQQ. */
+{ "btstl", 0x58D18000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* btstl RB,u6 01011bbb010100011BBBuuuuuuRRRRRR. */
+{ "btstl", 0x58518000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* btstl<.cc> RB,u6 01011bbb110100011BBBuuuuuu1QQQQQ. */
+{ "btstl", 0x58D18020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* btstl RB,s12 01011bbb100100011BBBssssssSSSSSS. */
+{ "btstl", 0x58918000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* btstl ximm,RC 01011100000100011111ccccccRRRRRR. */
+{ "btstl", 0x5C11F000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { XIMM, RC }, { 0 }},
+
+/* btstl RB,ximm 01011bbb000100011BBB111100RRRRRR. */
+{ "btstl", 0x58118F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 }},
+
+/* btstl<.cc> RB,ximm 01011bbb110100011BBB1111000QQQQQ. */
+{ "btstl", 0x58D18F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC }},
+
+/* btstl limm,RC 01011110000100011111ccccccRRRRRR. */
+{ "btstl", 0x5E11F000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* btstl RB,limm 01011bbb000100011BBB111110RRRRRR. */
+{ "btstl", 0x58118F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* btstl<.cc> RB,limm 01011bbb110100011BBB1111100QQQQQ. */
+{ "btstl", 0x58D18F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* btst_s b,u5 10111bbb111uuuuu. */
+{ "btst_s", 0x0000B8E0, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, UIMM5_11_S }, { 0 }},
+
+/* bxor<.f> a,b,c 00100bbb00010010FBBBCCCCCCAAAAAA. */
+{ "bxor", 0x20120000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* bxor<.f> 0,b,c 00100bbb00010010FBBBCCCCCC111110. */
+{ "bxor", 0x2012003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bxor<.f><.cc> b,b,c 00100bbb11010010FBBBCCCCCC0QQQQQ. */
+{ "bxor", 0x20D20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bxor<.f> a,b,u6 00100bbb01010010FBBBuuuuuuAAAAAA. */
+{ "bxor", 0x20520000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bxor<.f> 0,b,u6 00100bbb01010010FBBBuuuuuu111110. */
+{ "bxor", 0x2052003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bxor<.f><.cc> b,b,u6 00100bbb11010010FBBBuuuuuu1QQQQQ. */
+{ "bxor", 0x20D20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxor<.f> b,b,s12 00100bbb10010010FBBBssssssSSSSSS. */
+{ "bxor", 0x20920000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bxor<.f> a,limm,c 0010011000010010F111CCCCCCAAAAAA. */
+{ "bxor", 0x26127000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bxor<.f> a,b,limm 00100bbb00010010FBBB111110AAAAAA. */
+{ "bxor", 0x20120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bxor<.f> 0,limm,c 0010011000010010F111CCCCCC111110. */
+{ "bxor", 0x2612703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bxor<.f> 0,b,limm 00100bbb00010010FBBB111110111110. */
+{ "bxor", 0x20120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bxor<.f><.cc> b,b,limm 00100bbb11010010FBBB1111100QQQQQ. */
+{ "bxor", 0x20D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bxor<.f><.cc> 0,limm,c 0010011011010010F111CCCCCC0QQQQQ. */
+{ "bxor", 0x26D27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bxor<.f> a,limm,u6 0010011001010010F111uuuuuuAAAAAA. */
+{ "bxor", 0x26527000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bxor<.f> 0,limm,u6 0010011001010010F111uuuuuu111110. */
+{ "bxor", 0x2652703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bxor<.f><.cc> 0,limm,u6 0010011011010010F111uuuuuu1QQQQQ. */
+{ "bxor", 0x26D27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxor<.f> 0,limm,s12 0010011010010010F111ssssssSSSSSS. */
+{ "bxor", 0x26927000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bxor<.f> a,limm,limm 0010011000010010F111111110AAAAAA. */
+{ "bxor", 0x26127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bxor<.f> 0,limm,limm 0010011000010010F111111110111110. */
+{ "bxor", 0x26127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bxor<.f><.cc> 0,limm,limm 0010011011010010F1111111100QQQQQ. */
+{ "bxor", 0x26D27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,RB,RC 01011bbb00010010FBBBccccccaaaaaa. */
+{ "bxorl", 0x58120000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* bxorl<.f> 0,RB,RC 01011bbb00010010FBBBcccccc111110. */
+{ "bxorl", 0x5812003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* bxorl<.f><.cc> RB,RB,RC 01011bbb11010010FBBBcccccc0QQQQQ. */
+{ "bxorl", 0x58D20000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,RB,u6 01011bbb01010010FBBBuuuuuuaaaaaa. */
+{ "bxorl", 0x58520000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f> 0,RB,u6 01011bbb01010010FBBBuuuuuu111110. */
+{ "bxorl", 0x5852003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f><.cc> RB,RB,u6 01011bbb11010010FBBBuuuuuu1QQQQQ. */
+{ "bxorl", 0x58D20020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxorl<.f> RB,RB,s12 01011bbb10010010FBBBssssssSSSSSS. */
+{ "bxorl", 0x58920000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* bxorl<.f> RA,ximm,RC 0101110000010010F111ccccccaaaaaa. */
+{ "bxorl", 0x5C127000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* bxorl<.f> RA,RB,ximm 01011bbb00010010FBBB111100aaaaaa. */
+{ "bxorl", 0x58120F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* bxorl<.f> 0,ximm,RC 0101110000010010F111cccccc111110. */
+{ "bxorl", 0x5C12703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* bxorl<.f> 0,RB,ximm 01011bbb00010010FBBB111100111110. */
+{ "bxorl", 0x58120F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* bxorl<.f><.cc> 0,ximm,RC 0101110011010010F111cccccc0QQQQQ. */
+{ "bxorl", 0x5CD27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* bxorl<.f><.cc> RB,RB,ximm 01011bbb11010010FBBB1111000QQQQQ. */
+{ "bxorl", 0x58D20F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,ximm,u6 0101110001010010F111uuuuuuaaaaaa. */
+{ "bxorl", 0x5C527000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f> 0,ximm,u6 0101110001010010F111uuuuuu111110. */
+{ "bxorl", 0x5C52703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f><.cc> 0,ximm,u6 0101110011010010F111uuuuuu1QQQQQ. */
+{ "bxorl", 0x5CD27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,limm,RC 0101111000010010F111ccccccaaaaaa. */
+{ "bxorl", 0x5E127000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* bxorl<.f> RA,RB,limm 01011bbb00010010FBBB111110aaaaaa. */
+{ "bxorl", 0x58120F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* bxorl<.f> 0,limm,RC 0101111000010010F111cccccc111110. */
+{ "bxorl", 0x5E12703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* bxorl<.f> 0,RB,limm 01011bbb00010010FBBB111110111110. */
+{ "bxorl", 0x58120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* bxorl<.f><.cc> 0,limm,RC 0101111011010010F111cccccc0QQQQQ. */
+{ "bxorl", 0x5ED27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* bxorl<.f><.cc> RB,RB,limm 01011bbb11010010FBBB1111100QQQQQ. */
+{ "bxorl", 0x58D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,limm,u6 0101111001010010F111uuuuuuaaaaaa. */
+{ "bxorl", 0x5E527000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f> 0,limm,u6 0101111001010010F111uuuuuu111110. */
+{ "bxorl", 0x5E52703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* bxorl<.f><.cc> 0,limm,u6 0101111011010010F111uuuuuu1QQQQQ. */
+{ "bxorl", 0x5ED27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* bxorl<.f> 0,ximm,s12 0101110010010010F111ssssssSSSSSS. */
+{ "bxorl", 0x5C927000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* bxorl<.f> 0,limm,s12 0101111010010010F111ssssssSSSSSS. */
+{ "bxorl", 0x5E927000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* bxorl<.f> RA,ximm,ximm 0101110000010010F111111100aaaaaa. */
+{ "bxorl", 0x5C127F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* bxorl<.f> 0,ximm,ximm 0101110000010010F111111100111110. */
+{ "bxorl", 0x5C127F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* bxorl<.f><.cc> 0,ximm,ximm 0101110011010010F1111111000QQQQQ. */
+{ "bxorl", 0x5CD27F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* bxorl<.f> RA,limm,limm 0101111000010010F111111110aaaaaa. */
+{ "bxorl", 0x5E127F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* bxorl<.f> 0,limm,limm 0101111000010010F111111110111110. */
+{ "bxorl", 0x5E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* bxorl<.f><.cc> 0,limm,limm 0101111011010010F1111111100QQQQQ. */
+{ "bxorl", 0x5ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* b_s s10 1111000sssssssss. */
+{ "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }},
+
+/* cbflyhf0r a,b,c 00110bbb000110111BBBCCCCCCAAAAAA. */
+{ "cbflyhf0r", 0x301B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* cbflyhf0r 0,b,c 00110bbb000110111BBBCCCCCC111110. */
+{ "cbflyhf0r", 0x301B803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cbflyhf0r<.cc> b,b,c 00110bbb110110111BBBCCCCCC0QQQQQ. */
+{ "cbflyhf0r", 0x30DB8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* cbflyhf0r a,b,u6 00110bbb010110111BBBuuuuuuAAAAAA. */
+{ "cbflyhf0r", 0x305B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* cbflyhf0r 0,b,u6 00110bbb010110111BBBuuuuuu111110. */
+{ "cbflyhf0r", 0x305B803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cbflyhf0r<.cc> b,b,u6 00110bbb110110111BBBuuuuuu1QQQQQ. */
+{ "cbflyhf0r", 0x30DB8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cbflyhf0r b,b,s12 00110bbb100110111BBBssssssSSSSSS. */
+{ "cbflyhf0r", 0x309B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* cbflyhf0r a,limm,c 00110110000110111111CCCCCCAAAAAA. */
+{ "cbflyhf0r", 0x361BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* cbflyhf0r a,b,limm 00110bbb000110111BBB111110AAAAAA. */
+{ "cbflyhf0r", 0x301B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* cbflyhf0r 0,limm,c 00110110000110111111CCCCCC111110. */
+{ "cbflyhf0r", 0x361BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cbflyhf0r 0,b,limm 00110bbb000110111BBB111110111110. */
+{ "cbflyhf0r", 0x301B8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cbflyhf0r<.cc> b,b,limm 00110bbb110110111BBB1111100QQQQQ. */
+{ "cbflyhf0r", 0x30DB8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* cbflyhf0r<.cc> 0,limm,c 00110110110110111111CCCCCC0QQQQQ. */
+{ "cbflyhf0r", 0x36DBF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cbflyhf0r a,limm,u6 00110110010110111111uuuuuuAAAAAA. */
+{ "cbflyhf0r", 0x365BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* cbflyhf0r 0,limm,u6 00110110010110111111uuuuuu111110. */
+{ "cbflyhf0r", 0x365BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cbflyhf0r<.cc> 0,limm,u6 00110110110110111111uuuuuu1QQQQQ. */
+{ "cbflyhf0r", 0x36DBF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cbflyhf0r 0,limm,s12 00110110100110111111ssssssSSSSSS. */
+{ "cbflyhf0r", 0x369BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cbflyhf0r a,limm,limm 00110110000110111111111110AAAAAA. */
+{ "cbflyhf0r", 0x361BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* cbflyhf0r 0,limm,limm 00110110000110111111111110111110. */
+{ "cbflyhf0r", 0x361BFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cbflyhf0r<.cc> 0,limm,limm 001101101101101111111111100QQQQQ. */
+{ "cbflyhf0r", 0x36DBFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cbflyhf1r b,c 00110bbb001011110BBBCCCCCC111001. */
+{ "cbflyhf1r", 0x302F0039, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* cbflyhf1r 0,c 00110110001011110111CCCCCC011001. */
+{ "cbflyhf1r", 0x362F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* cbflyhf1r b,u6 00110bbb011011110BBBuuuuuu011001. */
+{ "cbflyhf1r", 0x306F0019, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* cbflyhf1r 0,u6 00110110011011110111uuuuuu011001. */
+{ "cbflyhf1r", 0x366F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* cbflyhf1r b,limm 00110bbb001011110BBB111110011001. */
+{ "cbflyhf1r", 0x302F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* cbflyhf1r 0,limm 00110110001011110111111110011001. */
+{ "cbflyhf1r", 0x362F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* clri c 00100111001011110000CCCCCC111111. */
+{ "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { 0 }},
+
+/* clri u6 00100111011011110000uuuuuu111111. */
+{ "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* clri 00100111001011110000000000111111. */
+{ "clri", 0x276F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* cmacchfr a,b,c 00110bbb000010011BBBCCCCCCAAAAAA. */
+{ "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* cmacchfr 0,b,c 00110bbb000010011BBBCCCCCC111110. */
+{ "cmacchfr", 0x3009803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmacchfr<.cc> b,b,c 00110bbb110010011BBBCCCCCC0QQQQQ. */
+{ "cmacchfr", 0x30C98000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* cmacchfr a,b,u6 00110bbb010010011BBBuuuuuuAAAAAA. */
+{ "cmacchfr", 0x30498000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* cmacchfr 0,b,u6 00110bbb010010011BBBuuuuuu111110. */
+{ "cmacchfr", 0x3049803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmacchfr<.cc> b,b,u6 00110bbb110010011BBBuuuuuu1QQQQQ. */
+{ "cmacchfr", 0x30C98020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmacchfr b,b,s12 00110bbb100010011BBBssssssSSSSSS. */
+{ "cmacchfr", 0x30898000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmacchfr a,limm,c 00110110000010011111CCCCCCAAAAAA. */
+{ "cmacchfr", 0x3609F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* cmacchfr a,b,limm 00110bbb000010011BBB111110AAAAAA. */
+{ "cmacchfr", 0x30098F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* cmacchfr 0,limm,c 00110110000010011111CCCCCC111110. */
+{ "cmacchfr", 0x3609F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmacchfr 0,b,limm 00110bbb000010011BBB111110111110. */
+{ "cmacchfr", 0x30098FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmacchfr<.cc> b,b,limm 00110bbb110010011BBB1111100QQQQQ. */
+{ "cmacchfr", 0x30C98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* cmacchfr<.cc> 0,limm,c 00110110110010011111CCCCCC0QQQQQ. */
+{ "cmacchfr", 0x36C9F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmacchfr a,limm,u6 00110110010010011111uuuuuuAAAAAA. */
+{ "cmacchfr", 0x3649F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmacchfr 0,limm,u6 00110110010010011111uuuuuu111110. */
+{ "cmacchfr", 0x3649F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmacchfr<.cc> 0,limm,u6 00110110110010011111uuuuuu1QQQQQ. */
+{ "cmacchfr", 0x36C9F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmacchfr 0,limm,s12 00110110100010011111ssssssSSSSSS. */
+{ "cmacchfr", 0x3689F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmacchfr a,limm,limm 00110110000010011111111110AAAAAA. */
+{ "cmacchfr", 0x3609FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* cmacchfr 0,limm,limm 00110110000010011111111110111110. */
+{ "cmacchfr", 0x3609FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmacchfr<.cc> 0,limm,limm 001101101100100111111111100QQQQQ. */
+{ "cmacchfr", 0x36C9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmacchnfr a,b,c 00110bbb000010001BBBCCCCCCAAAAAA. */
+{ "cmacchnfr", 0x30088000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* cmacchnfr 0,b,c 00110bbb000010001BBBCCCCCC111110. */
+{ "cmacchnfr", 0x3008803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmacchnfr<.cc> b,b,c 00110bbb110010001BBBCCCCCC0QQQQQ. */
+{ "cmacchnfr", 0x30C88000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* cmacchnfr a,b,u6 00110bbb010010001BBBuuuuuuAAAAAA. */
+{ "cmacchnfr", 0x30488000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* cmacchnfr 0,b,u6 00110bbb010010001BBBuuuuuu111110. */
+{ "cmacchnfr", 0x3048803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmacchnfr<.cc> b,b,u6 00110bbb110010001BBBuuuuuu1QQQQQ. */
+{ "cmacchnfr", 0x30C88020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmacchnfr b,b,s12 00110bbb100010001BBBssssssSSSSSS. */
+{ "cmacchnfr", 0x30888000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmacchnfr a,limm,c 00110110000010001111CCCCCCAAAAAA. */
+{ "cmacchnfr", 0x3608F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* cmacchnfr a,b,limm 00110bbb000010001BBB111110AAAAAA. */
+{ "cmacchnfr", 0x30088F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* cmacchnfr 0,limm,c 00110110000010001111CCCCCC111110. */
+{ "cmacchnfr", 0x3608F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmacchnfr 0,b,limm 00110bbb000010001BBB111110111110. */
+{ "cmacchnfr", 0x30088FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmacchnfr<.cc> b,b,limm 00110bbb110010001BBB1111100QQQQQ. */
+{ "cmacchnfr", 0x30C88F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* cmacchnfr<.cc> 0,limm,c 00110110110010001111CCCCCC0QQQQQ. */
+{ "cmacchnfr", 0x36C8F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmacchnfr a,limm,u6 00110110010010001111uuuuuuAAAAAA. */
+{ "cmacchnfr", 0x3648F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmacchnfr 0,limm,u6 00110110010010001111uuuuuu111110. */
+{ "cmacchnfr", 0x3648F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmacchnfr<.cc> 0,limm,u6 00110110110010001111uuuuuu1QQQQQ. */
+{ "cmacchnfr", 0x36C8F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmacchnfr 0,limm,s12 00110110100010001111ssssssSSSSSS. */
+{ "cmacchnfr", 0x3688F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmacchnfr a,limm,limm 00110110000010001111111110AAAAAA. */
+{ "cmacchnfr", 0x3608FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* cmacchnfr 0,limm,limm 00110110000010001111111110111110. */
+{ "cmacchnfr", 0x3608FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmacchnfr<.cc> 0,limm,limm 001101101100100011111111100QQQQQ. */
+{ "cmacchnfr", 0x36C8FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmachfr a,b,c 00110bbb000001111BBBCCCCCCAAAAAA. */
+{ "cmachfr", 0x30078000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* cmachfr 0,b,c 00110bbb000001111BBBCCCCCC111110. */
+{ "cmachfr", 0x3007803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmachfr<.cc> b,b,c 00110bbb110001111BBBCCCCCC0QQQQQ. */
+{ "cmachfr", 0x30C78000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* cmachfr a,b,u6 00110bbb010001111BBBuuuuuuAAAAAA. */
+{ "cmachfr", 0x30478000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* cmachfr 0,b,u6 00110bbb010001111BBBuuuuuu111110. */
+{ "cmachfr", 0x3047803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmachfr<.cc> b,b,u6 00110bbb110001111BBBuuuuuu1QQQQQ. */
+{ "cmachfr", 0x30C78020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmachfr b,b,s12 00110bbb100001111BBBssssssSSSSSS. */
+{ "cmachfr", 0x30878000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmachfr a,limm,c 00110110000001111111CCCCCCAAAAAA. */
+{ "cmachfr", 0x3607F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* cmachfr a,b,limm 00110bbb000001111BBB111110AAAAAA. */
+{ "cmachfr", 0x30078F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* cmachfr 0,limm,c 00110110000001111111CCCCCC111110. */
+{ "cmachfr", 0x3607F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmachfr 0,b,limm 00110bbb000001111BBB111110111110. */
+{ "cmachfr", 0x30078FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmachfr<.cc> b,b,limm 00110bbb110001111BBB1111100QQQQQ. */
+{ "cmachfr", 0x30C78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* cmachfr<.cc> 0,limm,c 00110110110001111111CCCCCC0QQQQQ. */
+{ "cmachfr", 0x36C7F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmachfr a,limm,u6 00110110010001111111uuuuuuAAAAAA. */
+{ "cmachfr", 0x3647F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmachfr 0,limm,u6 00110110010001111111uuuuuu111110. */
+{ "cmachfr", 0x3647F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmachfr<.cc> 0,limm,u6 00110110110001111111uuuuuu1QQQQQ. */
+{ "cmachfr", 0x36C7F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmachfr 0,limm,s12 00110110100001111111ssssssSSSSSS. */
+{ "cmachfr", 0x3687F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmachfr a,limm,limm 00110110000001111111111110AAAAAA. */
+{ "cmachfr", 0x3607FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* cmachfr 0,limm,limm 00110110000001111111111110111110. */
+{ "cmachfr", 0x3607FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmachfr<.cc> 0,limm,limm 001101101100011111111111100QQQQQ. */
+{ "cmachfr", 0x36C7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmachnfr a,b,c 00110bbb000001101BBBCCCCCCAAAAAA. */
+{ "cmachnfr", 0x30068000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* cmachnfr 0,b,c 00110bbb000001101BBBCCCCCC111110. */
+{ "cmachnfr", 0x3006803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmachnfr<.cc> b,b,c 00110bbb110001101BBBCCCCCC0QQQQQ. */
+{ "cmachnfr", 0x30C68000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* cmachnfr a,b,u6 00110bbb010001101BBBuuuuuuAAAAAA. */
+{ "cmachnfr", 0x30468000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* cmachnfr 0,b,u6 00110bbb010001101BBBuuuuuu111110. */
+{ "cmachnfr", 0x3046803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmachnfr<.cc> b,b,u6 00110bbb110001101BBBuuuuuu1QQQQQ. */
+{ "cmachnfr", 0x30C68020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmachnfr b,b,s12 00110bbb100001101BBBssssssSSSSSS. */
+{ "cmachnfr", 0x30868000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmachnfr a,limm,c 00110110000001101111CCCCCCAAAAAA. */
+{ "cmachnfr", 0x3606F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* cmachnfr a,b,limm 00110bbb000001101BBB111110AAAAAA. */
+{ "cmachnfr", 0x30068F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* cmachnfr 0,limm,c 00110110000001101111CCCCCC111110. */
+{ "cmachnfr", 0x3606F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmachnfr 0,b,limm 00110bbb000001101BBB111110111110. */
+{ "cmachnfr", 0x30068FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmachnfr<.cc> b,b,limm 00110bbb110001101BBB1111100QQQQQ. */
+{ "cmachnfr", 0x30C68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* cmachnfr<.cc> 0,limm,c 00110110110001101111CCCCCC0QQQQQ. */
+{ "cmachnfr", 0x36C6F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmachnfr a,limm,u6 00110110010001101111uuuuuuAAAAAA. */
+{ "cmachnfr", 0x3646F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmachnfr 0,limm,u6 00110110010001101111uuuuuu111110. */
+{ "cmachnfr", 0x3646F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmachnfr<.cc> 0,limm,u6 00110110110001101111uuuuuu1QQQQQ. */
+{ "cmachnfr", 0x36C6F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmachnfr 0,limm,s12 00110110100001101111ssssssSSSSSS. */
+{ "cmachnfr", 0x3686F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmachnfr a,limm,limm 00110110000001101111111110AAAAAA. */
+{ "cmachnfr", 0x3606FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* cmachnfr 0,limm,limm 00110110000001101111111110111110. */
+{ "cmachnfr", 0x3606FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmachnfr<.cc> 0,limm,limm 001101101100011011111111100QQQQQ. */
+{ "cmachnfr", 0x36C6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmp b,c 00100bbb000011001BBBCCCCCCRRRRRR. */
+{ "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* cmp<.cc> b,c 00100bbb110011001BBBCCCCCC0QQQQQ. */
+{ "cmp", 0x20CC8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* cmp b,u6 00100bbb010011001BBBuuuuuuRRRRRR. */
+{ "cmp", 0x204C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* cmp<.cc> b,u6 00100bbb110011001BBBuuuuuu1QQQQQ. */
+{ "cmp", 0x20CC8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* cmp b,s12 00100bbb100011001BBBssssssSSSSSS. */
+{ "cmp", 0x208C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* cmp limm,c 00100110000011001111CCCCCCRRRRRR. */
+{ "cmp", 0x260CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* cmp b,limm 00100bbb000011001BBB111110RRRRRR. */
+{ "cmp", 0x200C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* cmp<.cc> b,limm 00100bbb110011001BBB1111100QQQQQ. */
+{ "cmp", 0x20CC8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* cmp<.cc> limm,c 00100110110011001111CCCCCC0QQQQQ. */
+{ "cmp", 0x26CCF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { C_CC }},
+
+/* cmp limm,u6 00100110010011001111uuuuuuRRRRRR. */
+{ "cmp", 0x264CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* cmp<.cc> limm,u6 00100110110011001111uuuuuu1QQQQQ. */
+{ "cmp", 0x26CCF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmp limm,s12 00100110100011001111ssssssSSSSSS. */
+{ "cmp", 0x268CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* cmp limm,limm 00100110000011001111111110RRRRRR. */
+{ "cmp", 0x260CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* cmp<.cc> limm,limm 001001101100110011111111100QQQQQ. */
+{ "cmp", 0x26CCFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* cmpl RB,RC 01011bbb000011001BBBccccccRRRRRR. */
+{ "cmpl", 0x580C8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* cmpl<.cc> RB,RC 01011bbb110011001BBBcccccc0QQQQQ. */
+{ "cmpl", 0x58CC8000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* cmpl RB,u6 01011bbb010011001BBBuuuuuuRRRRRR. */
+{ "cmpl", 0x584C8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* cmpl<.cc> RB,u6 01011bbb110011001BBBuuuuuu1QQQQQ. */
+{ "cmpl", 0x58CC8020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* cmpl RB,s12 01011bbb100011001BBBssssssSSSSSS. */
+{ "cmpl", 0x588C8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* cmpl ximm,RC 01011100000011001111ccccccRRRRRR. */
+{ "cmpl", 0x5C0CF000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { XIMM, RC }, { 0 }},
+
+/* cmpl RB,ximm 01011bbb000011001BBB111100RRRRRR. */
+{ "cmpl", 0x580C8F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 }},
+
+/* cmpl<.cc> RB,ximm 01011bbb110011001BBB1111000QQQQQ. */
+{ "cmpl", 0x58CC8F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC }},
+
+/* cmpl limm,RC 01011110000011001111ccccccRRRRRR. */
+{ "cmpl", 0x5E0CF000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* cmpl RB,limm 01011bbb000011001BBB111110RRRRRR. */
+{ "cmpl", 0x580C8F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* cmpl<.cc> RB,limm 01011bbb110011001BBB1111100QQQQQ. */
+{ "cmpl", 0x58CC8F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* cmpychfr a,b,c 00110bbb000001011BBBCCCCCCAAAAAA. */
+{ "cmpychfr", 0x30058000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* cmpychfr 0,b,c 00110bbb000001011BBBCCCCCC111110. */
+{ "cmpychfr", 0x3005803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmpychfr<.cc> b,b,c 00110bbb110001011BBBCCCCCC0QQQQQ. */
+{ "cmpychfr", 0x30C58000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* cmpychfr a,b,u6 00110bbb010001011BBBuuuuuuAAAAAA. */
+{ "cmpychfr", 0x30458000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* cmpychfr 0,b,u6 00110bbb010001011BBBuuuuuu111110. */
+{ "cmpychfr", 0x3045803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpychfr<.cc> b,b,u6 00110bbb110001011BBBuuuuuu1QQQQQ. */
+{ "cmpychfr", 0x30C58020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmpychfr b,b,s12 00110bbb100001011BBBssssssSSSSSS. */
+{ "cmpychfr", 0x30858000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmpychfr a,limm,c 00110110000001011111CCCCCCAAAAAA. */
+{ "cmpychfr", 0x3605F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* cmpychfr a,b,limm 00110bbb000001011BBB111110AAAAAA. */
+{ "cmpychfr", 0x30058F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* cmpychfr 0,limm,c 00110110000001011111CCCCCC111110. */
+{ "cmpychfr", 0x3605F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmpychfr 0,b,limm 00110bbb000001011BBB111110111110. */
+{ "cmpychfr", 0x30058FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmpychfr<.cc> b,b,limm 00110bbb110001011BBB1111100QQQQQ. */
+{ "cmpychfr", 0x30C58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* cmpychfr<.cc> 0,limm,c 00110110110001011111CCCCCC0QQQQQ. */
+{ "cmpychfr", 0x36C5F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmpychfr a,limm,u6 00110110010001011111uuuuuuAAAAAA. */
+{ "cmpychfr", 0x3645F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpychfr 0,limm,u6 00110110010001011111uuuuuu111110. */
+{ "cmpychfr", 0x3645F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpychfr<.cc> 0,limm,u6 00110110110001011111uuuuuu1QQQQQ. */
+{ "cmpychfr", 0x36C5F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmpychfr 0,limm,s12 00110110100001011111ssssssSSSSSS. */
+{ "cmpychfr", 0x3685F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmpychfr a,limm,limm 00110110000001011111111110AAAAAA. */
+{ "cmpychfr", 0x3605FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* cmpychfr 0,limm,limm 00110110000001011111111110111110. */
+{ "cmpychfr", 0x3605FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpychfr<.cc> 0,limm,limm 001101101100010111111111100QQQQQ. */
+{ "cmpychfr", 0x36C5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmpychnfr a,b,c 00110bbb000000101BBBCCCCCCAAAAAA. */
+{ "cmpychnfr", 0x30028000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* cmpychnfr 0,b,c 00110bbb000000001BBBCCCCCC111110. */
+{ "cmpychnfr", 0x3000803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmpychnfr<.cc> b,b,c 00110bbb110000001BBBCCCCCC0QQQQQ. */
+{ "cmpychnfr", 0x30C08000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* cmpychnfr a,b,u6 00110bbb010000001BBBuuuuuuAAAAAA. */
+{ "cmpychnfr", 0x30408000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* cmpychnfr 0,b,u6 00110bbb010000001BBBuuuuuu111110. */
+{ "cmpychnfr", 0x3040803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpychnfr<.cc> b,b,u6 00110bbb110000001BBBuuuuuu1QQQQQ. */
+{ "cmpychnfr", 0x30C08020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmpychnfr b,b,s12 00110bbb100000001BBBssssssSSSSSS. */
+{ "cmpychnfr", 0x30808000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmpychnfr a,limm,c 00110110000000001111CCCCCCAAAAAA. */
+{ "cmpychnfr", 0x3600F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* cmpychnfr a,b,limm 00110bbb000000001BBB111110AAAAAA. */
+{ "cmpychnfr", 0x30008F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* cmpychnfr 0,limm,c 00110110000000001111CCCCCC111110. */
+{ "cmpychnfr", 0x3600F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmpychnfr 0,b,limm 00110bbb000000001BBB111110111110. */
+{ "cmpychnfr", 0x30008FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmpychnfr<.cc> b,b,limm 00110bbb110000001BBB1111100QQQQQ. */
+{ "cmpychnfr", 0x30C08F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* cmpychnfr<.cc> 0,limm,c 00110110110000001111CCCCCC0QQQQQ. */
+{ "cmpychnfr", 0x36C0F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmpychnfr a,limm,u6 00110110010000001111uuuuuuAAAAAA. */
+{ "cmpychnfr", 0x3640F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpychnfr 0,limm,u6 00110110010000001111uuuuuu111110. */
+{ "cmpychnfr", 0x3640F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpychnfr<.cc> 0,limm,u6 00110110110000001111uuuuuu1QQQQQ. */
+{ "cmpychnfr", 0x36C0F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmpychnfr 0,limm,s12 00110110100000001111ssssssSSSSSS. */
+{ "cmpychnfr", 0x3680F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmpychnfr a,limm,limm 00110110000000001111111110AAAAAA. */
+{ "cmpychnfr", 0x3600FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* cmpychnfr 0,limm,limm 00110110000000001111111110111110. */
+{ "cmpychnfr", 0x3600FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpychnfr<.cc> 0,limm,limm 001101101100000011111111100QQQQQ. */
+{ "cmpychnfr", 0x36C0FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmpyhfmr a,b,c 00110bbb000110110BBBCCCCCCAAAAAA. */
+{ "cmpyhfmr", 0x301B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* cmpyhfmr 0,b,c 00110bbb000110110BBBCCCCCC111110. */
+{ "cmpyhfmr", 0x301B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmpyhfmr<.cc> b,b,c 00110bbb110110110BBBCCCCCC0QQQQQ. */
+{ "cmpyhfmr", 0x30DB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* cmpyhfmr a,b,u6 00110bbb010110110BBBuuuuuuAAAAAA. */
+{ "cmpyhfmr", 0x305B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhfmr 0,b,u6 00110bbb010110110BBBuuuuuu111110. */
+{ "cmpyhfmr", 0x305B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhfmr<.cc> b,b,u6 00110bbb110110110BBBuuuuuu1QQQQQ. */
+{ "cmpyhfmr", 0x30DB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmpyhfmr b,b,s12 00110bbb100110110BBBssssssSSSSSS. */
+{ "cmpyhfmr", 0x309B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmpyhfmr a,limm,c 00110110000110110111CCCCCCAAAAAA. */
+{ "cmpyhfmr", 0x361B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* cmpyhfmr a,b,limm 00110bbb000110110BBB111110AAAAAA. */
+{ "cmpyhfmr", 0x301B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* cmpyhfmr 0,limm,c 00110110000110110111CCCCCC111110. */
+{ "cmpyhfmr", 0x361B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmpyhfmr 0,b,limm 00110bbb000110110BBB111110111110. */
+{ "cmpyhfmr", 0x301B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmpyhfmr<.cc> b,b,limm 00110bbb110110110BBB1111100QQQQQ. */
+{ "cmpyhfmr", 0x30DB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* cmpyhfmr<.cc> 0,limm,c 00110110110110110111CCCCCC0QQQQQ. */
+{ "cmpyhfmr", 0x36DB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmpyhfmr a,limm,u6 00110110010110110111uuuuuuAAAAAA. */
+{ "cmpyhfmr", 0x365B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhfmr 0,limm,u6 00110110010110110111uuuuuu111110. */
+{ "cmpyhfmr", 0x365B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhfmr<.cc> 0,limm,u6 00110110110110110111uuuuuu1QQQQQ. */
+{ "cmpyhfmr", 0x36DB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmpyhfmr 0,limm,s12 00110110100110110111ssssssSSSSSS. */
+{ "cmpyhfmr", 0x369B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmpyhfmr a,limm,limm 00110110000110110111111110AAAAAA. */
+{ "cmpyhfmr", 0x361B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhfmr 0,limm,limm 00110110000110110111111110111110. */
+{ "cmpyhfmr", 0x361B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhfmr<.cc> 0,limm,limm 001101101101101101111111100QQQQQ. */
+{ "cmpyhfmr", 0x36DB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmpyhfr a,b,c 00110bbb000000011BBBCCCCCCAAAAAA. */
+{ "cmpyhfr", 0x30018000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* cmpyhfr 0,b,c 00110bbb000000011BBBCCCCCC111110. */
+{ "cmpyhfr", 0x3001803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmpyhfr<.cc> b,b,c 00110bbb110000011BBBCCCCCC0QQQQQ. */
+{ "cmpyhfr", 0x30C18000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* cmpyhfr a,b,u6 00110bbb010000011BBBuuuuuuAAAAAA. */
+{ "cmpyhfr", 0x30418000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhfr 0,b,u6 00110bbb010000011BBBuuuuuu111110. */
+{ "cmpyhfr", 0x3041803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhfr<.cc> b,b,u6 00110bbb110000011BBBuuuuuu1QQQQQ. */
+{ "cmpyhfr", 0x30C18020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmpyhfr b,b,s12 00110bbb100000011BBBssssssSSSSSS. */
+{ "cmpyhfr", 0x30818000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmpyhfr a,limm,c 00110110000000011111CCCCCCAAAAAA. */
+{ "cmpyhfr", 0x3601F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* cmpyhfr a,b,limm 00110bbb000000011BBB111110AAAAAA. */
+{ "cmpyhfr", 0x30018F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* cmpyhfr 0,limm,c 00110110000000011111CCCCCC111110. */
+{ "cmpyhfr", 0x3601F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmpyhfr 0,b,limm 00110bbb000000011BBB111110111110. */
+{ "cmpyhfr", 0x30018FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmpyhfr<.cc> b,b,limm 00110bbb110000011BBB1111100QQQQQ. */
+{ "cmpyhfr", 0x30C18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* cmpyhfr<.cc> 0,limm,c 00110110110000011111CCCCCC0QQQQQ. */
+{ "cmpyhfr", 0x36C1F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmpyhfr a,limm,u6 00110110010000011111uuuuuuAAAAAA. */
+{ "cmpyhfr", 0x3641F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhfr 0,limm,u6 00110110010000011111uuuuuu111110. */
+{ "cmpyhfr", 0x3641F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhfr<.cc> 0,limm,u6 00110110110000011111uuuuuu1QQQQQ. */
+{ "cmpyhfr", 0x36C1F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmpyhfr 0,limm,s12 00110110100000011111ssssssSSSSSS. */
+{ "cmpyhfr", 0x3681F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmpyhfr a,limm,limm 00110110000000011111111110AAAAAA. */
+{ "cmpyhfr", 0x3601FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhfr 0,limm,limm 00110110000000011111111110111110. */
+{ "cmpyhfr", 0x3601FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhfr<.cc> 0,limm,limm 001101101100000111111111100QQQQQ. */
+{ "cmpyhfr", 0x36C1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmpyhnfr a,b,c 00110bbb000000001BBBCCCCCCAAAAAA. */
+{ "cmpyhnfr", 0x30008000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* cmpyhnfr 0,b,c 00110bbb000000101BBBCCCCCC111110. */
+{ "cmpyhnfr", 0x3002803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* cmpyhnfr<.cc> b,b,c 00110bbb110000101BBBCCCCCC0QQQQQ. */
+{ "cmpyhnfr", 0x30C28000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* cmpyhnfr a,b,u6 00110bbb010000101BBBuuuuuuAAAAAA. */
+{ "cmpyhnfr", 0x30428000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhnfr 0,b,u6 00110bbb010000101BBBuuuuuu111110. */
+{ "cmpyhnfr", 0x3042803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* cmpyhnfr<.cc> b,b,u6 00110bbb110000101BBBuuuuuu1QQQQQ. */
+{ "cmpyhnfr", 0x30C28020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* cmpyhnfr b,b,s12 00110bbb100000101BBBssssssSSSSSS. */
+{ "cmpyhnfr", 0x30828000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* cmpyhnfr a,limm,c 00110110000000101111CCCCCCAAAAAA. */
+{ "cmpyhnfr", 0x3602F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* cmpyhnfr a,b,limm 00110bbb000000101BBB111110AAAAAA. */
+{ "cmpyhnfr", 0x30028F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* cmpyhnfr 0,limm,c 00110110000000101111CCCCCC111110. */
+{ "cmpyhnfr", 0x3602F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* cmpyhnfr 0,b,limm 00110bbb000000101BBB111110111110. */
+{ "cmpyhnfr", 0x30028FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* cmpyhnfr<.cc> b,b,limm 00110bbb110000101BBB1111100QQQQQ. */
+{ "cmpyhnfr", 0x30C28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* cmpyhnfr<.cc> 0,limm,c 00110110110000101111CCCCCC0QQQQQ. */
+{ "cmpyhnfr", 0x36C2F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* cmpyhnfr a,limm,u6 00110110010000101111uuuuuuAAAAAA. */
+{ "cmpyhnfr", 0x3642F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhnfr 0,limm,u6 00110110010000101111uuuuuu111110. */
+{ "cmpyhnfr", 0x3642F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* cmpyhnfr<.cc> 0,limm,u6 00110110110000101111uuuuuu1QQQQQ. */
+{ "cmpyhnfr", 0x36C2F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* cmpyhnfr 0,limm,s12 00110110100000101111ssssssSSSSSS. */
+{ "cmpyhnfr", 0x3682F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* cmpyhnfr a,limm,limm 00110110000000101111111110AAAAAA. */
+{ "cmpyhnfr", 0x3602FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhnfr 0,limm,limm 00110110000000101111111110111110. */
+{ "cmpyhnfr", 0x3602FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* cmpyhnfr<.cc> 0,limm,limm 001101101100001011111111100QQQQQ. */
+{ "cmpyhnfr", 0x36C2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* cmp_s b,h 01110bbbhhh100HH. */
+{ "cmp_s", 0x00007010, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RH_S }, { 0 }},
+
+/* cmp_s h,s3 01110ssshhh101HH. */
+{ "cmp_s", 0x00007014, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, SIMM3_5_S }, { 0 }},
+
+/* cmp_s b,limm 01110bbb11010011. */
+{ "cmp_s", 0x000070D3, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, LIMM_S }, { 0 }},
+
+/* cmp_s limm,s3 01110sss11010111. */
+{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM_S, SIMM3_5_S }, { 0 }},
+
+/* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS. */
+{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, BRANCH, NONE, { RB, SIMM13_A16_20 }, { C_DNZ_D }},
+
+/* div<.f> a,b,c 00101bbb00000100FBBBCCCCCCAAAAAA. */
+{ "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* div<.f> 0,b,c 00101bbb00000100FBBBCCCCCC111110. */
+{ "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
+
+/* div<.f><.cc> b,b,c 00101bbb11000100FBBBCCCCCC0QQQQQ. */
+{ "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* div<.f> a,b,c 00101bbb00000100FBBBCCCCCCAAAAAA. */
+{ "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* div<.f> 0,b,c 00101bbb00000100FBBBCCCCCC111110. */
+{ "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, RB, RC }, { C_F }},
+
+/* div<.f><.cc> b,b,c 00101bbb11000100FBBBCCCCCC0QQQQQ. */
+{ "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* div<.f> a,b,u6 00101bbb01000100FBBBuuuuuuAAAAAA. */
+{ "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* div<.f> 0,b,u6 00101bbb01000100FBBBuuuuuu111110. */
+{ "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* div<.f><.cc> b,b,u6 00101bbb11000100FBBBuuuuuu1QQQQQ. */
+{ "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* div<.f> a,b,u6 00101bbb01000100FBBBuuuuuuAAAAAA. */
+{ "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* div<.f> 0,b,u6 00101bbb01000100FBBBuuuuuu111110. */
+{ "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* div<.f><.cc> b,b,u6 00101bbb11000100FBBBuuuuuu1QQQQQ. */
+{ "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* div<.f> b,b,s12 00101bbb10000100FBBBssssssSSSSSS. */
+{ "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* div<.f> b,b,s12 00101bbb10000100FBBBssssssSSSSSS. */
+{ "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* div<.f> a,limm,c 0010111000000100F111CCCCCCAAAAAA. */
+{ "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* div<.f> a,b,limm 00101bbb00000100FBBB111110AAAAAA. */
+{ "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* div<.f> 0,limm,c 0010111000000100F111CCCCCC111110. */
+{ "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* div<.f> 0,b,limm 00101bbb00000100FBBB111110111110. */
+{ "div", 0x28040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* div<.f><.cc> b,b,limm 00101bbb11000100FBBB1111100QQQQQ. */
+{ "div", 0x28C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* div<.f><.cc> 0,limm,c 0010111011000100F111CCCCCC0QQQQQ. */
+{ "div", 0x2EC47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* div<.f> a,limm,c 0010111000000100F111CCCCCCAAAAAA. */
+{ "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* div<.f> a,b,limm 00101bbb00000100FBBB111110AAAAAA. */
+{ "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* div<.f> 0,limm,c 0010111000000100F111CCCCCC111110. */
+{ "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* div<.f> 0,b,limm 00101bbb00000100FBBB111110111110. */
+{ "div", 0x28040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* div<.f><.cc> b,b,limm 00101bbb11000100FBBB1111100QQQQQ. */
+{ "div", 0x28C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* div<.f><.cc> 0,limm,c 0010111011000100F111CCCCCC0QQQQQ. */
+{ "div", 0x2EC47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* div<.f> a,limm,u6 0010111001000100F111uuuuuuAAAAAA. */
+{ "div", 0x2E447000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* div<.f> 0,limm,u6 0010111001000100F111uuuuuu111110. */
+{ "div", 0x2E44703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* div<.f><.cc> 0,limm,u6 0010111011000100F111uuuuuu1QQQQQ. */
+{ "div", 0x2EC47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* div<.f> a,limm,u6 0010111001000100F111uuuuuuAAAAAA. */
+{ "div", 0x2E447000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* div<.f> 0,limm,u6 0010111001000100F111uuuuuu111110. */
+{ "div", 0x2E44703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* div<.f><.cc> 0,limm,u6 0010111011000100F111uuuuuu1QQQQQ. */
+{ "div", 0x2EC47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* div<.f> 0,limm,s12 0010111010000100F111ssssssSSSSSS. */
+{ "div", 0x2E847000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* div<.f> 0,limm,s12 0010111010000100F111ssssssSSSSSS. */
+{ "div", 0x2E847000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* div<.f> a,limm,limm 0010111000000100F111111110AAAAAA. */
+{ "div", 0x2E047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* div<.f> 0,limm,limm 0010111000000100F111111110111110. */
+{ "div", 0x2E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* div<.f><.cc> 0,limm,limm 0010111011000100F1111111100QQQQQ. */
+{ "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* div<.f> a,limm,limm 0010111000000100F111111110AAAAAA. */
+{ "div", 0x2E047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* div<.f> 0,limm,limm 0010111000000100F111111110111110. */
+{ "div", 0x2E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* div<.f><.cc> 0,limm,limm 0010111011000100F1111111100QQQQQ. */
+{ "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* divf<.f> a,b,c 00110bbb00010000FBBBCCCCCCAAAAAA. */
+{ "divf", 0x30100000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* divf<.f> 0,b,c 00110bbb00010000FBBBCCCCCC111110. */
+{ "divf", 0x3010003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* divf<.f><.cc> b,b,c 00110bbb11010000FBBBCCCCCC0QQQQQ. */
+{ "divf", 0x30D00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* divf<.f> a,b,u6 00110bbb01010000FBBBuuuuuuAAAAAA. */
+{ "divf", 0x30500000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* divf<.f> 0,b,u6 00110bbb01010000FBBBuuuuuu111110. */
+{ "divf", 0x3050003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* divf<.f><.cc> b,b,u6 00110bbb11010000FBBBuuuuuu1QQQQQ. */
+{ "divf", 0x30D00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* divf<.f> b,b,s12 00110bbb10010000FBBBssssssSSSSSS. */
+{ "divf", 0x30900000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* divf<.f> a,limm,c 0011011000010000F111CCCCCCAAAAAA. */
+{ "divf", 0x36107000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* divf<.f> a,b,limm 00110bbb00010000FBBB111110AAAAAA. */
+{ "divf", 0x30100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* divf<.f> 0,limm,c 0011011000010000F111CCCCCC111110. */
+{ "divf", 0x3610703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* divf<.f> 0,b,limm 00110bbb00010000FBBB111110111110. */
+{ "divf", 0x30100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* divf<.f><.cc> b,b,limm 00110bbb11010000FBBB1111100QQQQQ. */
+{ "divf", 0x30D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* divf<.f><.cc> 0,limm,c 0011011011010000F111CCCCCC0QQQQQ. */
+{ "divf", 0x36D07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* divf<.f> a,limm,u6 0011011001010000F111uuuuuuAAAAAA. */
+{ "divf", 0x36507000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* divf<.f> 0,limm,u6 0011011001010000F111uuuuuu111110. */
+{ "divf", 0x3650703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divf<.f><.cc> 0,limm,u6 0011011011010000F111uuuuuu1QQQQQ. */
+{ "divf", 0x36D07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divf<.f> 0,limm,s12 0011011010010000F111ssssssSSSSSS. */
+{ "divf", 0x36907000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* divf<.f> a,limm,limm 0011011000010000F111111110AAAAAA. */
+{ "divf", 0x36107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* divf<.f> 0,limm,limm 0011011000010000F111111110111110. */
+{ "divf", 0x36107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* divf<.f><.cc> 0,limm,limm 0011011011010000F1111111100QQQQQ. */
+{ "divf", 0x36D07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* divl<.f> RA,RB,RC 01011bbb00100100FBBBccccccaaaaaa. */
+{ "divl", 0x58240000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* divl<.f> 0,RB,RC 01011bbb00100100FBBBcccccc111110. */
+{ "divl", 0x5824003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* divl<.f><.cc> RB,RB,RC 01011bbb11100100FBBBcccccc0QQQQQ. */
+{ "divl", 0x58E40000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* divl<.f> RA,RB,u6 01011bbb01100100FBBBuuuuuuaaaaaa. */
+{ "divl", 0x58640000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* divl<.f> 0,RB,u6 01011bbb01100100FBBBuuuuuu111110. */
+{ "divl", 0x5864003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* divl<.f><.cc> RB,RB,u6 01011bbb11100100FBBBuuuuuu1QQQQQ. */
+{ "divl", 0x58E40020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* divl<.f> RB,RB,s12 01011bbb10100100FBBBssssssSSSSSS. */
+{ "divl", 0x58A40000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* divl<.f> RA,ximm,RC 0101110000100100F111ccccccaaaaaa. */
+{ "divl", 0x5C247000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* divl<.f> RA,RB,ximm 01011bbb00100100FBBB111100aaaaaa. */
+{ "divl", 0x58240F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* divl<.f> 0,ximm,RC 0101110000100100F111cccccc111110. */
+{ "divl", 0x5C24703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* divl<.f> 0,RB,ximm 01011bbb00100100FBBB111100111110. */
+{ "divl", 0x58240F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* divl<.f><.cc> 0,ximm,RC 0101110011100100F111cccccc0QQQQQ. */
+{ "divl", 0x5CE47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* divl<.f><.cc> RB,RB,ximm 01011bbb11100100FBBB1111000QQQQQ. */
+{ "divl", 0x58E40F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* divl<.f> RA,ximm,u6 0101110001100100F111uuuuuuaaaaaa. */
+{ "divl", 0x5C647000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* divl<.f> 0,ximm,u6 0101110001100100F111uuuuuu111110. */
+{ "divl", 0x5C64703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* divl<.f><.cc> 0,ximm,u6 0101110011100100F111uuuuuu1QQQQQ. */
+{ "divl", 0x5CE47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divl<.f> RA,limm,RC 0101111000100100F111ccccccaaaaaa. */
+{ "divl", 0x5E247000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* divl<.f> RA,RB,limm 01011bbb00100100FBBB111110aaaaaa. */
+{ "divl", 0x58240F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* divl<.f> 0,limm,RC 0101111000100100F111cccccc111110. */
+{ "divl", 0x5E24703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* divl<.f> 0,RB,limm 01011bbb00100100FBBB111110111110. */
+{ "divl", 0x58240FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* divl<.f><.cc> 0,limm,RC 0101111011100100F111cccccc0QQQQQ. */
+{ "divl", 0x5EE47000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* divl<.f><.cc> RB,RB,limm 01011bbb11100100FBBB1111100QQQQQ. */
+{ "divl", 0x58E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* divl<.f> RA,limm,u6 0101111001100100F111uuuuuuaaaaaa. */
+{ "divl", 0x5E647000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divl<.f> 0,limm,u6 0101111001100100F111uuuuuu111110. */
+{ "divl", 0x5E64703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divl<.f><.cc> 0,limm,u6 0101111011100100F111uuuuuu1QQQQQ. */
+{ "divl", 0x5EE47020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divl<.f> 0,ximm,s12 0101110010100100F111ssssssSSSSSS. */
+{ "divl", 0x5CA47000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* divl<.f> 0,limm,s12 0101111010100100F111ssssssSSSSSS. */
+{ "divl", 0x5EA47000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* divl<.f> RA,ximm,ximm 0101110000100100F111111100aaaaaa. */
+{ "divl", 0x5C247F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* divl<.f> 0,ximm,ximm 0101110000100100F111111100111110. */
+{ "divl", 0x5C247F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* divl<.f><.cc> 0,ximm,ximm 0101110011100100F1111111000QQQQQ. */
+{ "divl", 0x5CE47F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* divl<.f> RA,limm,limm 0101111000100100F111111110aaaaaa. */
+{ "divl", 0x5E247F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* divl<.f> 0,limm,limm 0101111000100100F111111110111110. */
+{ "divl", 0x5E247FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* divl<.f><.cc> 0,limm,limm 0101111011100100F1111111100QQQQQ. */
+{ "divl", 0x5EE47F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA. */
+{ "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* divu<.f> 0,b,c 00101bbb00000101FBBBCCCCCC111110. */
+{ "divu", 0x2805003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
+
+/* divu<.f><.cc> b,b,c 00101bbb11000101FBBBCCCCCC0QQQQQ. */
+{ "divu", 0x28C50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA. */
+{ "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* divu<.f> 0,b,c 00101bbb00000101FBBBCCCCCC111110. */
+{ "divu", 0x2805003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* divu<.f><.cc> b,b,c 00101bbb11000101FBBBCCCCCC0QQQQQ. */
+{ "divu", 0x28C50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* divu<.f> a,b,u6 00101bbb01000101FBBBuuuuuuAAAAAA. */
+{ "divu", 0x28450000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* divu<.f> 0,b,u6 00101bbb01000101FBBBuuuuuu111110. */
+{ "divu", 0x2845003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* divu<.f><.cc> b,b,u6 00101bbb11000101FBBBuuuuuu1QQQQQ. */
+{ "divu", 0x28C50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* divu<.f> a,b,u6 00101bbb01000101FBBBuuuuuuAAAAAA. */
+{ "divu", 0x28450000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* divu<.f> 0,b,u6 00101bbb01000101FBBBuuuuuu111110. */
+{ "divu", 0x2845003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* divu<.f><.cc> b,b,u6 00101bbb11000101FBBBuuuuuu1QQQQQ. */
+{ "divu", 0x28C50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* divu<.f> b,b,s12 00101bbb10000101FBBBssssssSSSSSS. */
+{ "divu", 0x28850000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* divu<.f> b,b,s12 00101bbb10000101FBBBssssssSSSSSS. */
+{ "divu", 0x28850000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* divu<.f> a,limm,c 0010111000000101F111CCCCCCAAAAAA. */
+{ "divu", 0x2E057000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* divu<.f> a,b,limm 00101bbb00000101FBBB111110AAAAAA. */
+{ "divu", 0x28050F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* divu<.f> 0,limm,c 0010111000000101F111CCCCCC111110. */
+{ "divu", 0x2E05703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* divu<.f> 0,b,limm 00101bbb00000101FBBB111110111110. */
+{ "divu", 0x28050FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* divu<.f><.cc> b,b,limm 00101bbb11000101FBBB1111100QQQQQ. */
+{ "divu", 0x28C50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* divu<.f><.cc> 0,limm,c 0010111011000101F111CCCCCC0QQQQQ. */
+{ "divu", 0x2EC57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* divu<.f> a,limm,c 0010111000000101F111CCCCCCAAAAAA. */
+{ "divu", 0x2E057000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* divu<.f> a,b,limm 00101bbb00000101FBBB111110AAAAAA. */
+{ "divu", 0x28050F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* divu<.f> 0,limm,c 0010111000000101F111CCCCCC111110. */
+{ "divu", 0x2E05703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* divu<.f> 0,b,limm 00101bbb00000101FBBB111110111110. */
+{ "divu", 0x28050FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* divu<.f><.cc> b,b,limm 00101bbb11000101FBBB1111100QQQQQ. */
+{ "divu", 0x28C50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* divu<.f><.cc> 0,limm,c 0010111011000101F111CCCCCC0QQQQQ. */
+{ "divu", 0x2EC57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* divu<.f> a,limm,u6 0010111001000101F111uuuuuuAAAAAA. */
+{ "divu", 0x2E457000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* divu<.f> 0,limm,u6 0010111001000101F111uuuuuu111110. */
+{ "divu", 0x2E45703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divu<.f><.cc> 0,limm,u6 0010111011000101F111uuuuuu1QQQQQ. */
+{ "divu", 0x2EC57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divu<.f> a,limm,u6 0010111001000101F111uuuuuuAAAAAA. */
+{ "divu", 0x2E457000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* divu<.f> 0,limm,u6 0010111001000101F111uuuuuu111110. */
+{ "divu", 0x2E45703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divu<.f><.cc> 0,limm,u6 0010111011000101F111uuuuuu1QQQQQ. */
+{ "divu", 0x2EC57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divu<.f> 0,limm,s12 0010111010000101F111ssssssSSSSSS. */
+{ "divu", 0x2E857000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* divu<.f> 0,limm,s12 0010111010000101F111ssssssSSSSSS. */
+{ "divu", 0x2E857000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* divu<.f> a,limm,limm 0010111000000101F111111110AAAAAA. */
+{ "divu", 0x2E057F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* divu<.f> 0,limm,limm 0010111000000101F111111110111110. */
+{ "divu", 0x2E057FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* divu<.f><.cc> 0,limm,limm 0010111011000101F1111111100QQQQQ. */
+{ "divu", 0x2EC57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* divu<.f> a,limm,limm 0010111000000101F111111110AAAAAA. */
+{ "divu", 0x2E057F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* divu<.f> 0,limm,limm 0010111000000101F111111110111110. */
+{ "divu", 0x2E057FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* divu<.f><.cc> 0,limm,limm 0010111011000101F1111111100QQQQQ. */
+{ "divu", 0x2EC57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* divul<.f> RA,RB,RC 01011bbb00100101FBBBccccccaaaaaa. */
+{ "divul", 0x58250000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* divul<.f> 0,RB,RC 01011bbb00100101FBBBcccccc111110. */
+{ "divul", 0x5825003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* divul<.f><.cc> RB,RB,RC 01011bbb11100101FBBBcccccc0QQQQQ. */
+{ "divul", 0x58E50000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* divul<.f> RA,RB,u6 01011bbb01100101FBBBuuuuuuaaaaaa. */
+{ "divul", 0x58650000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* divul<.f> 0,RB,u6 01011bbb01100101FBBBuuuuuu111110. */
+{ "divul", 0x5865003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* divul<.f><.cc> RB,RB,u6 01011bbb11100101FBBBuuuuuu1QQQQQ. */
+{ "divul", 0x58E50020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* divul<.f> RB,RB,s12 01011bbb10100101FBBBssssssSSSSSS. */
+{ "divul", 0x58A50000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* divul<.f> RA,ximm,RC 0101110000100101F111ccccccaaaaaa. */
+{ "divul", 0x5C257000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* divul<.f> RA,RB,ximm 01011bbb00100101FBBB111100aaaaaa. */
+{ "divul", 0x58250F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* divul<.f> 0,ximm,RC 0101110000100101F111cccccc111110. */
+{ "divul", 0x5C25703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* divul<.f> 0,RB,ximm 01011bbb00100101FBBB111100111110. */
+{ "divul", 0x58250F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* divul<.f><.cc> 0,ximm,RC 0101110011100101F111cccccc0QQQQQ. */
+{ "divul", 0x5CE57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* divul<.f><.cc> RB,RB,ximm 01011bbb11100101FBBB1111000QQQQQ. */
+{ "divul", 0x58E50F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* divul<.f> RA,ximm,u6 0101110001100101F111uuuuuuaaaaaa. */
+{ "divul", 0x5C657000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* divul<.f> 0,ximm,u6 0101110001100101F111uuuuuu111110. */
+{ "divul", 0x5C65703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* divul<.f><.cc> 0,ximm,u6 0101110011100101F111uuuuuu1QQQQQ. */
+{ "divul", 0x5CE57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divul<.f> RA,limm,RC 0101111000100101F111ccccccaaaaaa. */
+{ "divul", 0x5E257000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* divul<.f> RA,RB,limm 01011bbb00100101FBBB111110aaaaaa. */
+{ "divul", 0x58250F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* divul<.f> 0,limm,RC 0101111000100101F111cccccc111110. */
+{ "divul", 0x5E25703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* divul<.f> 0,RB,limm 01011bbb00100101FBBB111110111110. */
+{ "divul", 0x58250FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* divul<.f><.cc> 0,limm,RC 0101111011100101F111cccccc0QQQQQ. */
+{ "divul", 0x5EE57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* divul<.f><.cc> RB,RB,limm 01011bbb11100101FBBB1111100QQQQQ. */
+{ "divul", 0x58E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* divul<.f> RA,limm,u6 0101111001100101F111uuuuuuaaaaaa. */
+{ "divul", 0x5E657000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divul<.f> 0,limm,u6 0101111001100101F111uuuuuu111110. */
+{ "divul", 0x5E65703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* divul<.f><.cc> 0,limm,u6 0101111011100101F111uuuuuu1QQQQQ. */
+{ "divul", 0x5EE57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* divul<.f> 0,ximm,s12 0101110010100101F111ssssssSSSSSS. */
+{ "divul", 0x5CA57000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* divul<.f> 0,limm,s12 0101111010100101F111ssssssSSSSSS. */
+{ "divul", 0x5EA57000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* divul<.f> RA,ximm,ximm 0101110000100101F111111100aaaaaa. */
+{ "divul", 0x5C257F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* divul<.f> 0,ximm,ximm 0101110000100101F111111100111110. */
+{ "divul", 0x5C257F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* divul<.f><.cc> 0,ximm,ximm 0101110011100101F1111111000QQQQQ. */
+{ "divul", 0x5CE57F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* divul<.f> RA,limm,limm 0101111000100101F111111110aaaaaa. */
+{ "divul", 0x5E257F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* divul<.f> 0,limm,limm 0101111000100101F111111110111110. */
+{ "divul", 0x5E257FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* divul<.f><.cc> 0,limm,limm 0101111011100101F1111111100QQQQQ. */
+{ "divul", 0x5EE57F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmach<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA. */
+{ "dmach", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmach<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110. */
+{ "dmach", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmach<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ. */
+{ "dmach", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmach<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA. */
+{ "dmach", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmach<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110. */
+{ "dmach", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmach<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ. */
+{ "dmach", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmach<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS. */
+{ "dmach", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmach<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA. */
+{ "dmach", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmach<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA. */
+{ "dmach", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmach<.f> 0,limm,c 0010111000010010F111CCCCCC111110. */
+{ "dmach", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmach<.f> 0,b,limm 00101bbb00010010FBBB111110111110. */
+{ "dmach", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmach<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ. */
+{ "dmach", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmach<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ. */
+{ "dmach", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmach<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA. */
+{ "dmach", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmach<.f> 0,limm,u6 0010111001010010F111uuuuuu111110. */
+{ "dmach", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmach<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ. */
+{ "dmach", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmach<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS. */
+{ "dmach", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmach<.f> a,limm,limm 0010111000010010F111111110AAAAAA. */
+{ "dmach", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmach<.f> 0,limm,limm 0010111000010010F111111110111110. */
+{ "dmach", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmach<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ. */
+{ "dmach", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachbl<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA. */
+{ "dmachbl", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmachbl<.f> 0,b,c 00110bbb00011000FBBBCCCCCC111110. */
+{ "dmachbl", 0x3018003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmachbl<.f><.cc> b,b,c 00110bbb11011000FBBBCCCCCC0QQQQQ. */
+{ "dmachbl", 0x30D80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachbl<.f> a,b,u6 00110bbb01011000FBBBuuuuuuAAAAAA. */
+{ "dmachbl", 0x30580000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmachbl<.f> 0,b,u6 00110bbb01011000FBBBuuuuuu111110. */
+{ "dmachbl", 0x3058003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachbl<.f><.cc> b,b,u6 00110bbb11011000FBBBuuuuuu1QQQQQ. */
+{ "dmachbl", 0x30D80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachbl<.f> b,b,s12 00110bbb10011000FBBBssssssSSSSSS. */
+{ "dmachbl", 0x30980000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachbl<.f> a,limm,c 0011011000011000F111CCCCCCAAAAAA. */
+{ "dmachbl", 0x36187000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmachbl<.f> a,b,limm 00110bbb00011000FBBB111110AAAAAA. */
+{ "dmachbl", 0x30180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmachbl<.f> 0,limm,c 0011011000011000F111CCCCCC111110. */
+{ "dmachbl", 0x3618703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachbl<.f> 0,b,limm 00110bbb00011000FBBB111110111110. */
+{ "dmachbl", 0x30180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachbl<.f><.cc> b,b,limm 00110bbb11011000FBBB1111100QQQQQ. */
+{ "dmachbl", 0x30D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachbl<.f><.cc> 0,limm,c 0011011011011000F111CCCCCC0QQQQQ. */
+{ "dmachbl", 0x36D87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachbl<.f> a,limm,u6 0011011001011000F111uuuuuuAAAAAA. */
+{ "dmachbl", 0x36587000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachbl<.f> 0,limm,u6 0011011001011000F111uuuuuu111110. */
+{ "dmachbl", 0x3658703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachbl<.f><.cc> 0,limm,u6 0011011011011000F111uuuuuu1QQQQQ. */
+{ "dmachbl", 0x36D87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachbl<.f> 0,limm,s12 0011011010011000F111ssssssSSSSSS. */
+{ "dmachbl", 0x36987000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachbl<.f> a,limm,limm 0011011000011000F111111110AAAAAA. */
+{ "dmachbl", 0x36187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmachbl<.f> 0,limm,limm 0011011000011000F111111110111110. */
+{ "dmachbl", 0x36187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachbl<.f><.cc> 0,limm,limm 0011011011011000F1111111100QQQQQ. */
+{ "dmachbl", 0x36D87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachbm<.f> a,b,c 00110bbb00011001FBBBCCCCCCAAAAAA. */
+{ "dmachbm", 0x30190000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmachbm<.f> 0,b,c 00110bbb00011001FBBBCCCCCC111110. */
+{ "dmachbm", 0x3019003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmachbm<.f><.cc> b,b,c 00110bbb11011001FBBBCCCCCC0QQQQQ. */
+{ "dmachbm", 0x30D90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachbm<.f> a,b,u6 00110bbb01011001FBBBuuuuuuAAAAAA. */
+{ "dmachbm", 0x30590000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmachbm<.f> 0,b,u6 00110bbb01011001FBBBuuuuuu111110. */
+{ "dmachbm", 0x3059003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachbm<.f><.cc> b,b,u6 00110bbb11011001FBBBuuuuuu1QQQQQ. */
+{ "dmachbm", 0x30D90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachbm<.f> b,b,s12 00110bbb10011001FBBBssssssSSSSSS. */
+{ "dmachbm", 0x30990000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachbm<.f> a,limm,c 0011011000011001F111CCCCCCAAAAAA. */
+{ "dmachbm", 0x36197000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmachbm<.f> a,b,limm 00110bbb00011001FBBB111110AAAAAA. */
+{ "dmachbm", 0x30190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmachbm<.f> 0,limm,c 0011011000011001F111CCCCCC111110. */
+{ "dmachbm", 0x3619703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachbm<.f> 0,b,limm 00110bbb00011001FBBB111110111110. */
+{ "dmachbm", 0x30190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachbm<.f><.cc> b,b,limm 00110bbb11011001FBBB1111100QQQQQ. */
+{ "dmachbm", 0x30D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachbm<.f><.cc> 0,limm,c 0011011011011001F111CCCCCC0QQQQQ. */
+{ "dmachbm", 0x36D97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachbm<.f> a,limm,u6 0011011001011001F111uuuuuuAAAAAA. */
+{ "dmachbm", 0x36597000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachbm<.f> 0,limm,u6 0011011001011001F111uuuuuu111110. */
+{ "dmachbm", 0x3659703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachbm<.f><.cc> 0,limm,u6 0011011011011001F111uuuuuu1QQQQQ. */
+{ "dmachbm", 0x36D97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachbm<.f> 0,limm,s12 0011011010011001F111ssssssSSSSSS. */
+{ "dmachbm", 0x36997000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachbm<.f> a,limm,limm 0011011000011001F111111110AAAAAA. */
+{ "dmachbm", 0x36197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmachbm<.f> 0,limm,limm 0011011000011001F111111110111110. */
+{ "dmachbm", 0x36197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachbm<.f><.cc> 0,limm,limm 0011011011011001F1111111100QQQQQ. */
+{ "dmachbm", 0x36D97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachf<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA. */
+{ "dmachf", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmachf<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110. */
+{ "dmachf", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmachf<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ. */
+{ "dmachf", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachf<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA. */
+{ "dmachf", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmachf<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110. */
+{ "dmachf", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachf<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ. */
+{ "dmachf", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachf<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS. */
+{ "dmachf", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachf<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA. */
+{ "dmachf", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmachf<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA. */
+{ "dmachf", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmachf<.f> 0,limm,c 0010111001101100F111CCCCCC111110. */
+{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachf<.f> 0,b,limm 00101bbb00101100FBBB111110111110. */
+{ "dmachf", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachf<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ. */
+{ "dmachf", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachf<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ. */
+{ "dmachf", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachf<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA. */
+{ "dmachf", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachf<.f> 0,limm,u6 0010111001101100F111uuuuuu111110. */
+{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachf<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ. */
+{ "dmachf", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachf<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS. */
+{ "dmachf", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachf<.f> a,limm,limm 0010111000101100F111111110AAAAAA. */
+{ "dmachf", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmachf<.f> 0,limm,limm 0010111000101100F111111110111110. */
+{ "dmachf", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachf<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ. */
+{ "dmachf", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachfr<.f> a,b,c 00101bbb00101101FBBBCCCCCCAAAAAA. */
+{ "dmachfr", 0x282D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmachfr<.f> 0,b,c 00101bbb00101101FBBBCCCCCC111110. */
+{ "dmachfr", 0x282D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmachfr<.f><.cc> b,b,c 00101bbb11101101FBBBCCCCCC0QQQQQ. */
+{ "dmachfr", 0x28ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachfr<.f> a,b,u6 00101bbb01101101FBBBuuuuuuAAAAAA. */
+{ "dmachfr", 0x286D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmachfr<.f> 0,b,u6 00101bbb01101101FBBBuuuuuu111110. */
+{ "dmachfr", 0x286D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachfr<.f><.cc> b,b,u6 00101bbb11101101FBBBuuuuuu1QQQQQ. */
+{ "dmachfr", 0x28ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachfr<.f> b,b,s12 00101bbb10101101FBBBssssssSSSSSS. */
+{ "dmachfr", 0x28AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachfr<.f> a,limm,c 0010111000101101F111CCCCCCAAAAAA. */
+{ "dmachfr", 0x2E2D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmachfr<.f> a,b,limm 00101bbb00101101FBBB111110AAAAAA. */
+{ "dmachfr", 0x282D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmachfr<.f> 0,limm,c 0010111001101101F111CCCCCC111110. */
+{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachfr<.f> 0,b,limm 00101bbb00101101FBBB111110111110. */
+{ "dmachfr", 0x282D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachfr<.f><.cc> b,b,limm 00101bbb11101101FBBB1111100QQQQQ. */
+{ "dmachfr", 0x28ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachfr<.f><.cc> 0,limm,c 0010111011101101F111CCCCCC0QQQQQ. */
+{ "dmachfr", 0x2EED7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachfr<.f> a,limm,u6 0010111001101101F111uuuuuuAAAAAA. */
+{ "dmachfr", 0x2E6D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachfr<.f> 0,limm,u6 0010111001101101F111uuuuuu111110. */
+{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachfr<.f><.cc> 0,limm,u6 0010111011101101F111uuuuuu1QQQQQ. */
+{ "dmachfr", 0x2EED7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachfr<.f> 0,limm,s12 0010111010101101F111ssssssSSSSSS. */
+{ "dmachfr", 0x2EAD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachfr<.f> a,limm,limm 0010111000101101F111111110AAAAAA. */
+{ "dmachfr", 0x2E2D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmachfr<.f> 0,limm,limm 0010111000101101F111111110111110. */
+{ "dmachfr", 0x2E2D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachfr<.f><.cc> 0,limm,limm 0010111011101101F1111111100QQQQQ. */
+{ "dmachfr", 0x2EED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmachu<.f> a,b,c 00101bbb00010011FBBBCCCCCCAAAAAA. */
+{ "dmachu", 0x28130000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmachu<.f> 0,b,c 00101bbb00010011FBBBCCCCCC111110. */
+{ "dmachu", 0x2813003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmachu<.f><.cc> b,b,c 00101bbb11010011FBBBCCCCCC0QQQQQ. */
+{ "dmachu", 0x28D30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmachu<.f> a,b,u6 00101bbb01010011FBBBuuuuuuAAAAAA. */
+{ "dmachu", 0x28530000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f> 0,b,u6 00101bbb01010011FBBBuuuuuu111110. */
+{ "dmachu", 0x2853003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f><.cc> b,b,u6 00101bbb11010011FBBBuuuuuu1QQQQQ. */
+{ "dmachu", 0x28D30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachu<.f> b,b,s12 00101bbb10010011FBBBssssssSSSSSS. */
+{ "dmachu", 0x28930000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmachu<.f> a,limm,c 0010111000010011F111CCCCCCAAAAAA. */
+{ "dmachu", 0x2E137000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmachu<.f> a,b,limm 00101bbb00010011FBBB111110AAAAAA. */
+{ "dmachu", 0x28130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmachu<.f> 0,limm,c 0010111000010011F111CCCCCC111110. */
+{ "dmachu", 0x2E13703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmachu<.f> 0,b,limm 00101bbb00010011FBBB111110111110. */
+{ "dmachu", 0x28130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmachu<.f><.cc> b,b,limm 00101bbb11010011FBBB1111100QQQQQ. */
+{ "dmachu", 0x28D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmachu<.f><.cc> 0,limm,c 0010111011010011F111CCCCCC0QQQQQ. */
+{ "dmachu", 0x2ED37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmachu<.f> a,limm,u6 0010111001010011F111uuuuuuAAAAAA. */
+{ "dmachu", 0x2E537000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f> 0,limm,u6 0010111001010011F111uuuuuu111110. */
+{ "dmachu", 0x2E53703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmachu<.f><.cc> 0,limm,u6 0010111011010011F111uuuuuu1QQQQQ. */
+{ "dmachu", 0x2ED37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmachu<.f> 0,limm,s12 0010111010010011F111ssssssSSSSSS. */
+{ "dmachu", 0x2E937000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmachu<.f> a,limm,limm 0010111000010011F111111110AAAAAA. */
+{ "dmachu", 0x2E137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmachu<.f> 0,limm,limm 0010111000010011F111111110111110. */
+{ "dmachu", 0x2E137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmachu<.f><.cc> 0,limm,limm 0010111011010011F1111111100QQQQQ. */
+{ "dmachu", 0x2ED37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmacwh<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA. */
+{ "dmacwh", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmacwh<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110. */
+{ "dmacwh", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmacwh<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ. */
+{ "dmacwh", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmacwh<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA. */
+{ "dmacwh", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110. */
+{ "dmacwh", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ. */
+{ "dmacwh", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwh<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS. */
+{ "dmacwh", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmacwh<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA. */
+{ "dmacwh", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmacwh<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA. */
+{ "dmacwh", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmacwh<.f> 0,limm,c 0010111000110110F111CCCCCC111110. */
+{ "dmacwh", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmacwh<.f> 0,b,limm 00101bbb00110110FBBB111110111110. */
+{ "dmacwh", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmacwh<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ. */
+{ "dmacwh", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmacwh<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ. */
+{ "dmacwh", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmacwh<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA. */
+{ "dmacwh", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f> 0,limm,u6 0010111001110110F111uuuuuu111110. */
+{ "dmacwh", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwh<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ. */
+{ "dmacwh", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwh<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS. */
+{ "dmacwh", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmacwh<.f> a,limm,limm 0010111000110110F111111110AAAAAA. */
+{ "dmacwh", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwh<.f> 0,limm,limm 0010111000110110F111111110111110. */
+{ "dmacwh", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwh<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ. */
+{ "dmacwh", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmacwhf<.f> a,b,c 00110bbb00110111FBBBCCCCCCAAAAAA. */
+{ "dmacwhf", 0x30370000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmacwhf<.f> 0,b,c 00110bbb00110111FBBBCCCCCC111110. */
+{ "dmacwhf", 0x3037003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmacwhf<.f><.cc> b,b,c 00110bbb11110111FBBBCCCCCC0QQQQQ. */
+{ "dmacwhf", 0x30F70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmacwhf<.f> a,b,u6 00110bbb01110111FBBBuuuuuuAAAAAA. */
+{ "dmacwhf", 0x30770000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwhf<.f> 0,b,u6 00110bbb01110111FBBBuuuuuu111110. */
+{ "dmacwhf", 0x3077003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwhf<.f><.cc> b,b,u6 00110bbb11110111FBBBuuuuuu1QQQQQ. */
+{ "dmacwhf", 0x30F70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwhf<.f> b,b,s12 00110bbb10110111FBBBssssssSSSSSS. */
+{ "dmacwhf", 0x30B70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmacwhf<.f> a,limm,c 0011011000110111F111CCCCCCAAAAAA. */
+{ "dmacwhf", 0x36377000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmacwhf<.f> a,b,limm 00110bbb00110111FBBB111110AAAAAA. */
+{ "dmacwhf", 0x30370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmacwhf<.f> 0,limm,c 0011011000110111F111CCCCCC111110. */
+{ "dmacwhf", 0x3637703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmacwhf<.f> 0,b,limm 00110bbb00110111FBBB111110111110. */
+{ "dmacwhf", 0x30370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmacwhf<.f><.cc> b,b,limm 00110bbb11110111FBBB1111100QQQQQ. */
+{ "dmacwhf", 0x30F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmacwhf<.f><.cc> 0,limm,c 0011011011110111F111CCCCCC0QQQQQ. */
+{ "dmacwhf", 0x36F77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmacwhf<.f> a,limm,u6 0011011001110111F111uuuuuuAAAAAA. */
+{ "dmacwhf", 0x36777000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwhf<.f> 0,limm,u6 0011011001110111F111uuuuuu111110. */
+{ "dmacwhf", 0x3677703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwhf<.f><.cc> 0,limm,u6 0011011011110111F111uuuuuu1QQQQQ. */
+{ "dmacwhf", 0x36F77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwhf<.f> 0,limm,s12 0011011010110111F111ssssssSSSSSS. */
+{ "dmacwhf", 0x36B77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmacwhf<.f> a,limm,limm 0011011000110111F111111110AAAAAA. */
+{ "dmacwhf", 0x36377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwhf<.f> 0,limm,limm 0011011000110111F111111110111110. */
+{ "dmacwhf", 0x36377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwhf<.f><.cc> 0,limm,limm 0011011011110111F1111111100QQQQQ. */
+{ "dmacwhf", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmacwhu<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA. */
+{ "dmacwhu", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmacwhu<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110. */
+{ "dmacwhu", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmacwhu<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ. */
+{ "dmacwhu", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmacwhu<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA. */
+{ "dmacwhu", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110. */
+{ "dmacwhu", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ. */
+{ "dmacwhu", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwhu<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS. */
+{ "dmacwhu", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmacwhu<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA. */
+{ "dmacwhu", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmacwhu<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA. */
+{ "dmacwhu", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmacwhu<.f> 0,limm,c 0010111000110111F111CCCCCC111110. */
+{ "dmacwhu", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmacwhu<.f> 0,b,limm 00101bbb00110111FBBB111110111110. */
+{ "dmacwhu", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmacwhu<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ. */
+{ "dmacwhu", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmacwhu<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ. */
+{ "dmacwhu", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmacwhu<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA. */
+{ "dmacwhu", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f> 0,limm,u6 0010111001110111F111uuuuuu111110. */
+{ "dmacwhu", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmacwhu<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ. */
+{ "dmacwhu", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmacwhu<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS. */
+{ "dmacwhu", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmacwhu<.f> a,limm,limm 0010111000110111F111111110AAAAAA. */
+{ "dmacwhu", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwhu<.f> 0,limm,limm 0010111000110111F111111110111110. */
+{ "dmacwhu", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmacwhu<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ. */
+{ "dmacwhu", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmb 00100011011011110001RRR000111111. */
+{ "dmb", 0x236F103F, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* dmb u3 00100011011011110001RRRuuu111111. */
+{ "dmb", 0x236F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM3_23 }, { 0 }},
+
+/* dmpyh<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA. */
+{ "dmpyh", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpyh<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110. */
+{ "dmpyh", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmpyh<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ. */
+{ "dmpyh", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyh<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA. */
+{ "dmpyh", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110. */
+{ "dmpyh", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ. */
+{ "dmpyh", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyh<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS. */
+{ "dmpyh", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyh<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA. */
+{ "dmpyh", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpyh<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA. */
+{ "dmpyh", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpyh<.f> 0,limm,c 0010111000010000F111CCCCCC111110. */
+{ "dmpyh", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyh<.f> 0,b,limm 00101bbb00010000FBBB111110111110. */
+{ "dmpyh", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyh<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ. */
+{ "dmpyh", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyh<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ. */
+{ "dmpyh", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyh<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA. */
+{ "dmpyh", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f> 0,limm,u6 0010111001010000F111uuuuuu111110. */
+{ "dmpyh", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyh<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ. */
+{ "dmpyh", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyh<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS. */
+{ "dmpyh", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyh<.f> a,limm,limm 0010111000010000F111111110AAAAAA. */
+{ "dmpyh", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyh<.f> 0,limm,limm 0010111000010000F111111110111110. */
+{ "dmpyh", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyh<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ. */
+{ "dmpyh", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhbl<.f> a,b,c 00110bbb00010110FBBBCCCCCCAAAAAA. */
+{ "dmpyhbl", 0x30160000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpyhbl<.f> 0,b,c 00110bbb00010110FBBBCCCCCC111110. */
+{ "dmpyhbl", 0x3016003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhbl<.f><.cc> b,b,c 00110bbb11010110FBBBCCCCCC0QQQQQ. */
+{ "dmpyhbl", 0x30D60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhbl<.f> a,b,u6 00110bbb01010110FBBBuuuuuuAAAAAA. */
+{ "dmpyhbl", 0x30560000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhbl<.f> 0,b,u6 00110bbb01010110FBBBuuuuuu111110. */
+{ "dmpyhbl", 0x3056003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhbl<.f><.cc> b,b,u6 00110bbb11010110FBBBuuuuuu1QQQQQ. */
+{ "dmpyhbl", 0x30D60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhbl<.f> b,b,s12 00110bbb10010110FBBBssssssSSSSSS. */
+{ "dmpyhbl", 0x30960000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhbl<.f> a,limm,c 0011011000010110F111CCCCCCAAAAAA. */
+{ "dmpyhbl", 0x36167000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpyhbl<.f> a,b,limm 00110bbb00010110FBBB111110AAAAAA. */
+{ "dmpyhbl", 0x30160F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpyhbl<.f> 0,limm,c 0011011000010110F111CCCCCC111110. */
+{ "dmpyhbl", 0x3616703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhbl<.f> 0,b,limm 00110bbb00010110FBBB111110111110. */
+{ "dmpyhbl", 0x30160FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhbl<.f><.cc> b,b,limm 00110bbb11010110FBBB1111100QQQQQ. */
+{ "dmpyhbl", 0x30D60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhbl<.f><.cc> 0,limm,c 0011011011010110F111CCCCCC0QQQQQ. */
+{ "dmpyhbl", 0x36D67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhbl<.f> a,limm,u6 0011011001010110F111uuuuuuAAAAAA. */
+{ "dmpyhbl", 0x36567000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhbl<.f> 0,limm,u6 0011011001010110F111uuuuuu111110. */
+{ "dmpyhbl", 0x3656703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhbl<.f><.cc> 0,limm,u6 0011011011010110F111uuuuuu1QQQQQ. */
+{ "dmpyhbl", 0x36D67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhbl<.f> 0,limm,s12 0011011010010110F111ssssssSSSSSS. */
+{ "dmpyhbl", 0x36967000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhbl<.f> a,limm,limm 0011011000010110F111111110AAAAAA. */
+{ "dmpyhbl", 0x36167F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhbl<.f> 0,limm,limm 0011011000010110F111111110111110. */
+{ "dmpyhbl", 0x36167FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhbl<.f><.cc> 0,limm,limm 0011011011010110F1111111100QQQQQ. */
+{ "dmpyhbl", 0x36D67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhbm<.f> a,b,c 00110bbb00010111FBBBCCCCCCAAAAAA. */
+{ "dmpyhbm", 0x30170000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpyhbm<.f> 0,b,c 00110bbb00010111FBBBCCCCCC111110. */
+{ "dmpyhbm", 0x3017003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhbm<.f><.cc> b,b,c 00110bbb11010111FBBBCCCCCC0QQQQQ. */
+{ "dmpyhbm", 0x30D70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhbm<.f> a,b,u6 00110bbb01010111FBBBuuuuuuAAAAAA. */
+{ "dmpyhbm", 0x30570000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhbm<.f> 0,b,u6 00110bbb01010111FBBBuuuuuu111110. */
+{ "dmpyhbm", 0x3057003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhbm<.f><.cc> b,b,u6 00110bbb11010111FBBBuuuuuu1QQQQQ. */
+{ "dmpyhbm", 0x30D70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhbm<.f> b,b,s12 00110bbb10010111FBBBssssssSSSSSS. */
+{ "dmpyhbm", 0x30970000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhbm<.f> a,limm,c 0011011000010111F111CCCCCCAAAAAA. */
+{ "dmpyhbm", 0x36177000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpyhbm<.f> a,b,limm 00110bbb00010111FBBB111110AAAAAA. */
+{ "dmpyhbm", 0x30170F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpyhbm<.f> 0,limm,c 0011011000010111F111CCCCCC111110. */
+{ "dmpyhbm", 0x3617703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhbm<.f> 0,b,limm 00110bbb00010111FBBB111110111110. */
+{ "dmpyhbm", 0x30170FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhbm<.f><.cc> b,b,limm 00110bbb11010111FBBB1111100QQQQQ. */
+{ "dmpyhbm", 0x30D70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhbm<.f><.cc> 0,limm,c 0011011011010111F111CCCCCC0QQQQQ. */
+{ "dmpyhbm", 0x36D77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhbm<.f> a,limm,u6 0011011001010111F111uuuuuuAAAAAA. */
+{ "dmpyhbm", 0x36577000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhbm<.f> 0,limm,u6 0011011001010111F111uuuuuu111110. */
+{ "dmpyhbm", 0x3657703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhbm<.f><.cc> 0,limm,u6 0011011011010111F111uuuuuu1QQQQQ. */
+{ "dmpyhbm", 0x36D77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhbm<.f> 0,limm,s12 0011011010010111F111ssssssSSSSSS. */
+{ "dmpyhbm", 0x36977000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhbm<.f> a,limm,limm 0011011000010111F111111110AAAAAA. */
+{ "dmpyhbm", 0x36177F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhbm<.f> 0,limm,limm 0011011000010111F111111110111110. */
+{ "dmpyhbm", 0x36177FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhbm<.f><.cc> 0,limm,limm 0011011011010111F1111111100QQQQQ. */
+{ "dmpyhbm", 0x36D77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhf<.f> a,b,c 00101bbb00101010FBBBCCCCCCAAAAAA. */
+{ "dmpyhf", 0x282A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpyhf<.f> 0,b,c 00101bbb00101010FBBBCCCCCC111110. */
+{ "dmpyhf", 0x282A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhf<.f><.cc> b,b,c 00101bbb11101010FBBBCCCCCC0QQQQQ. */
+{ "dmpyhf", 0x28EA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhf<.f> a,b,u6 00101bbb01101010FBBBuuuuuuAAAAAA. */
+{ "dmpyhf", 0x286A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhf<.f> 0,b,u6 00101bbb01101010FBBBuuuuuu111110. */
+{ "dmpyhf", 0x286A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhf<.f><.cc> b,b,u6 00101bbb11101010FBBBuuuuuu1QQQQQ. */
+{ "dmpyhf", 0x28EA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhf<.f> b,b,s12 00101bbb10101010FBBBssssssSSSSSS. */
+{ "dmpyhf", 0x28AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhf<.f> a,limm,c 0010111000101010F111CCCCCCAAAAAA. */
+{ "dmpyhf", 0x2E2A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpyhf<.f> a,b,limm 00101bbb00101010FBBB111110AAAAAA. */
+{ "dmpyhf", 0x282A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpyhf<.f> 0,limm,c 0010111001101010F111CCCCCC111110. */
+{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhf<.f> 0,b,limm 00101bbb00101010FBBB111110111110. */
+{ "dmpyhf", 0x282A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhf<.f><.cc> b,b,limm 00101bbb11101010FBBB1111100QQQQQ. */
+{ "dmpyhf", 0x28EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhf<.f><.cc> 0,limm,c 0010111011101010F111CCCCCC0QQQQQ. */
+{ "dmpyhf", 0x2EEA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhf<.f> a,limm,u6 0010111001101010F111uuuuuuAAAAAA. */
+{ "dmpyhf", 0x2E6A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhf<.f> 0,limm,u6 0010111001101010F111uuuuuu111110. */
+{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhf<.f><.cc> 0,limm,u6 0010111011101010F111uuuuuu1QQQQQ. */
+{ "dmpyhf", 0x2EEA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhf<.f> 0,limm,s12 0010111010101010F111ssssssSSSSSS. */
+{ "dmpyhf", 0x2EAA7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhf<.f> a,limm,limm 0010111000101010F111111110AAAAAA. */
+{ "dmpyhf", 0x2E2A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhf<.f> 0,limm,limm 0010111000101010F111111110111110. */
+{ "dmpyhf", 0x2E2A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhf<.f><.cc> 0,limm,limm 0010111011101010F1111111100QQQQQ. */
+{ "dmpyhf", 0x2EEA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhfr<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA. */
+{ "dmpyhfr", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpyhfr<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110. */
+{ "dmpyhfr", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhfr<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ. */
+{ "dmpyhfr", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhfr<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA. */
+{ "dmpyhfr", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhfr<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110. */
+{ "dmpyhfr", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhfr<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ. */
+{ "dmpyhfr", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhfr<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS. */
+{ "dmpyhfr", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhfr<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA. */
+{ "dmpyhfr", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpyhfr<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA. */
+{ "dmpyhfr", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpyhfr<.f> 0,limm,c 0010111001101011F111CCCCCC111110. */
+{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhfr<.f> 0,b,limm 00101bbb00101011FBBB111110111110. */
+{ "dmpyhfr", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhfr<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ. */
+{ "dmpyhfr", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhfr<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ. */
+{ "dmpyhfr", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhfr<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA. */
+{ "dmpyhfr", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhfr<.f> 0,limm,u6 0010111001101011F111uuuuuu111110. */
+{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhfr<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ. */
+{ "dmpyhfr", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhfr<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS. */
+{ "dmpyhfr", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhfr<.f> a,limm,limm 0010111000101011F111111110AAAAAA. */
+{ "dmpyhfr", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhfr<.f> 0,limm,limm 0010111000101011F111111110111110. */
+{ "dmpyhfr", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhfr<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ. */
+{ "dmpyhfr", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhu<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA. */
+{ "dmpyhu", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpyhu<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110. */
+{ "dmpyhu", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhu<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ. */
+{ "dmpyhu", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhu<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA. */
+{ "dmpyhu", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110. */
+{ "dmpyhu", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ. */
+{ "dmpyhu", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhu<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS. */
+{ "dmpyhu", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhu<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA. */
+{ "dmpyhu", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpyhu<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA. */
+{ "dmpyhu", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpyhu<.f> 0,limm,c 0010111000010001F111CCCCCC111110. */
+{ "dmpyhu", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhu<.f> 0,b,limm 00101bbb00010001FBBB111110111110. */
+{ "dmpyhu", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhu<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ. */
+{ "dmpyhu", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhu<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ. */
+{ "dmpyhu", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhu<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA. */
+{ "dmpyhu", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f> 0,limm,u6 0010111001010001F111uuuuuu111110. */
+{ "dmpyhu", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhu<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ. */
+{ "dmpyhu", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhu<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS. */
+{ "dmpyhu", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhu<.f> a,limm,limm 0010111000010001F111111110AAAAAA. */
+{ "dmpyhu", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhu<.f> 0,limm,limm 0010111000010001F111111110111110. */
+{ "dmpyhu", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhu<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ. */
+{ "dmpyhu", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpyhwf<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA. */
+{ "dmpyhwf", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpyhwf<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110. */
+{ "dmpyhwf", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* dmpyhwf<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ. */
+{ "dmpyhwf", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpyhwf<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA. */
+{ "dmpyhwf", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhwf<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110. */
+{ "dmpyhwf", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpyhwf<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ. */
+{ "dmpyhwf", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhwf<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS. */
+{ "dmpyhwf", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpyhwf<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA. */
+{ "dmpyhwf", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpyhwf<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA. */
+{ "dmpyhwf", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpyhwf<.f> 0,limm,c 0010111001101000F111CCCCCC111110. */
+{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpyhwf<.f> 0,b,limm 00101bbb00101000FBBB111110111110. */
+{ "dmpyhwf", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpyhwf<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ. */
+{ "dmpyhwf", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpyhwf<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ. */
+{ "dmpyhwf", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpyhwf<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA. */
+{ "dmpyhwf", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhwf<.f> 0,limm,u6 0010111001101000F111uuuuuu111110. */
+{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpyhwf<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ. */
+{ "dmpyhwf", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpyhwf<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS. */
+{ "dmpyhwf", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpyhwf<.f> a,limm,limm 0010111000101000F111111110AAAAAA. */
+{ "dmpyhwf", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhwf<.f> 0,limm,limm 0010111000101000F111111110111110. */
+{ "dmpyhwf", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpyhwf<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ. */
+{ "dmpyhwf", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpywh<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA. */
+{ "dmpywh", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpywh<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110. */
+{ "dmpywh", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmpywh<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ. */
+{ "dmpywh", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpywh<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA. */
+{ "dmpywh", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110. */
+{ "dmpywh", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ. */
+{ "dmpywh", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywh<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS. */
+{ "dmpywh", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpywh<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA. */
+{ "dmpywh", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpywh<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA. */
+{ "dmpywh", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpywh<.f> 0,limm,c 0010111000110010F111CCCCCC111110. */
+{ "dmpywh", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpywh<.f> 0,b,limm 00101bbb00110010FBBB111110111110. */
+{ "dmpywh", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpywh<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ. */
+{ "dmpywh", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpywh<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ. */
+{ "dmpywh", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpywh<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA. */
+{ "dmpywh", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f> 0,limm,u6 0010111001110010F111uuuuuu111110. */
+{ "dmpywh", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywh<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ. */
+{ "dmpywh", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywh<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS. */
+{ "dmpywh", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpywh<.f> a,limm,limm 0010111000110010F111111110AAAAAA. */
+{ "dmpywh", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywh<.f> 0,limm,limm 0010111000110010F111111110111110. */
+{ "dmpywh", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywh<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ. */
+{ "dmpywh", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpywhf<.f> a,b,c 00110bbb00110011FBBBCCCCCCAAAAAA. */
+{ "dmpywhf", 0x30330000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpywhf<.f> 0,b,c 00110bbb00110011FBBBCCCCCC111110. */
+{ "dmpywhf", 0x3033003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmpywhf<.f><.cc> b,b,c 00110bbb11110011FBBBCCCCCC0QQQQQ. */
+{ "dmpywhf", 0x30F30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpywhf<.f> a,b,u6 00110bbb01110011FBBBuuuuuuAAAAAA. */
+{ "dmpywhf", 0x30730000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywhf<.f> 0,b,u6 00110bbb01110011FBBBuuuuuu111110. */
+{ "dmpywhf", 0x3073003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywhf<.f><.cc> b,b,u6 00110bbb11110011FBBBuuuuuu1QQQQQ. */
+{ "dmpywhf", 0x30F30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywhf<.f> b,b,s12 00110bbb10110011FBBBssssssSSSSSS. */
+{ "dmpywhf", 0x30B30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpywhf<.f> a,limm,c 0011011000110011F111CCCCCCAAAAAA. */
+{ "dmpywhf", 0x36337000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpywhf<.f> a,b,limm 00110bbb00110011FBBB111110AAAAAA. */
+{ "dmpywhf", 0x30330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpywhf<.f> 0,limm,c 0011011000110011F111CCCCCC111110. */
+{ "dmpywhf", 0x3633703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpywhf<.f> 0,b,limm 00110bbb00110011FBBB111110111110. */
+{ "dmpywhf", 0x30330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpywhf<.f><.cc> b,b,limm 00110bbb11110011FBBB1111100QQQQQ. */
+{ "dmpywhf", 0x30F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpywhf<.f><.cc> 0,limm,c 0011011011110011F111CCCCCC0QQQQQ. */
+{ "dmpywhf", 0x36F37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpywhf<.f> a,limm,u6 0011011001110011F111uuuuuuAAAAAA. */
+{ "dmpywhf", 0x36737000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywhf<.f> 0,limm,u6 0011011001110011F111uuuuuu111110. */
+{ "dmpywhf", 0x3673703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywhf<.f><.cc> 0,limm,u6 0011011011110011F111uuuuuu1QQQQQ. */
+{ "dmpywhf", 0x36F37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywhf<.f> 0,limm,s12 0011011010110011F111ssssssSSSSSS. */
+{ "dmpywhf", 0x36B37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpywhf<.f> a,limm,limm 0011011000110011F111111110AAAAAA. */
+{ "dmpywhf", 0x36337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywhf<.f> 0,limm,limm 0011011000110011F111111110111110. */
+{ "dmpywhf", 0x36337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywhf<.f><.cc> 0,limm,limm 0011011011110011F1111111100QQQQQ. */
+{ "dmpywhf", 0x36F37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dmpywhu<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA. */
+{ "dmpywhu", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* dmpywhu<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110. */
+{ "dmpywhu", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* dmpywhu<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ. */
+{ "dmpywhu", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* dmpywhu<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA. */
+{ "dmpywhu", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110. */
+{ "dmpywhu", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ. */
+{ "dmpywhu", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywhu<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS. */
+{ "dmpywhu", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* dmpywhu<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA. */
+{ "dmpywhu", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* dmpywhu<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA. */
+{ "dmpywhu", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* dmpywhu<.f> 0,limm,c 0010111000110011F111CCCCCC111110. */
+{ "dmpywhu", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* dmpywhu<.f> 0,b,limm 00101bbb00110011FBBB111110111110. */
+{ "dmpywhu", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* dmpywhu<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ. */
+{ "dmpywhu", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* dmpywhu<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ. */
+{ "dmpywhu", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* dmpywhu<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA. */
+{ "dmpywhu", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f> 0,limm,u6 0010111001110011F111uuuuuu111110. */
+{ "dmpywhu", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* dmpywhu<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ. */
+{ "dmpywhu", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* dmpywhu<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS. */
+{ "dmpywhu", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* dmpywhu<.f> a,limm,limm 0010111000110011F111111110AAAAAA. */
+{ "dmpywhu", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywhu<.f> 0,limm,limm 0010111000110011F111111110111110. */
+{ "dmpywhu", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* dmpywhu<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ. */
+{ "dmpywhu", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* dsync 00100010011011110001RRRRRR111111. */
+{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* enter_s u6 110000UU111uuuu0. */
+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ENTER, CD1, { BRAKET, R13_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }},
+{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ENTER, CD1, { UIMM6_11_S }, { 0 }},
+
+/* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */
+{ "ex", 0x202F000C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> b,u6 00100bbb01101111DBBBuuuuuu001100. */
+{ "ex", 0x206F000C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> b,limm 00100bbb00101111DBBB111110001100. */
+{ "ex", 0x202F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> limm,c 0010011000101111D111CCCCCC001100. */
+{ "ex", 0x262F700C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> limm,u6 0010011001101111D111uuuuuu001100. */
+{ "ex", 0x266F700C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* ex<.di> limm,limm 0010011000101111D111111110001100. */
+{ "ex", 0x262F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }},
+
+/* exl<.aq> RB,RC 01011bbb00101111FBBBcccccc001100. */
+{ "exl", 0x582F000C, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_AQ }},
+
+/* extb<.f> b,c 00100bbb00101111FBBBCCCCCC000111. */
+{ "extb", 0x202F0007, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* extb<.f> 0,c 0010011000101111F111CCCCCC000111. */
+{ "extb", 0x262F7007, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* extb<.f> b,u6 00100bbb01101111FBBBuuuuuu000111. */
+{ "extb", 0x206F0007, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* extb<.f> 0,u6 0010011001101111F111uuuuuu000111. */
+{ "extb", 0x266F7007, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* extb<.f> b,limm 00100bbb00101111FBBB111110000111. */
+{ "extb", 0x202F0F87, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* extb<.f> 0,limm 0010011000101111F111111110000111. */
+{ "extb", 0x262F7F87, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* extb_s b,c 01111bbbccc01111. */
+{ "extb_s", 0x0000780F, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* exth<.f> b,c 00100bbb00101111FBBBCCCCCC001000. */
+{ "exth", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* exth<.f> 0,c 0010011000101111F111CCCCCC001000. */
+{ "exth", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* exth<.f> b,u6 00100bbb01101111FBBBuuuuuu001000. */
+{ "exth", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* exth<.f> 0,u6 0010011001101111F111uuuuuu001000. */
+{ "exth", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* exth<.f> b,limm 00100bbb00101111FBBB111110001000. */
+{ "exth", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* exth<.f> 0,limm 0010011000101111F111111110001000. */
+{ "exth", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* exth_s b,c 01111bbbccc10000. */
+{ "exth_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* ffs<.f> b,c 00101bbb00101111FBBBCCCCCC010010. */
+{ "ffs", 0x282F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, RC }, { C_F }},
+
+/* ffs<.f> 0,c 0010111000101111F111CCCCCC010010. */
+{ "ffs", 0x2E2F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, RC }, { C_F }},
+
+/* ffs<.f> b,u6 00101bbb01101111FBBBuuuuuu010010. */
+{ "ffs", 0x286F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }},
+
+/* ffs<.f> 0,u6 0010111001101111F111uuuuuu010010. */
+{ "ffs", 0x2E6F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }},
+
+/* ffs<.f> b,limm 00101bbb00101111FBBB111110010010. */
+{ "ffs", 0x282F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, LIMM }, { C_F }},
+
+/* ffs<.f> 0,limm 0010111000101111F111111110010010. */
+{ "ffs", 0x2E2F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, LIMM }, { C_F }},
+
+/* ffsl<.f> RB,RC 01011bbb00101111FBBBcccccc010010. */
+{ "ffsl", 0x582F0012, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* ffsl<.f> 0,RC 0101111000101111F111cccccc010010. */
+{ "ffsl", 0x5E2F7012, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* ffsl<.f> RB,u6 01011bbb01101111FBBBuuuuuu010010. */
+{ "ffsl", 0x586F0012, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* ffsl<.f> 0,u6 0101111001101111F111uuuuuu010010. */
+{ "ffsl", 0x5E6F7012, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* ffsl<.f> RB,ximm 01011bbb00101111FBBB111100010010. */
+{ "ffsl", 0x582F0F12, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* ffsl<.f> 0,ximm 0101111000101111F111111100010010. */
+{ "ffsl", 0x5E2F7F12, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* ffsl<.f> RB,limm 01011bbb00101111FBBB111110010010. */
+{ "ffsl", 0x582F0F92, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* ffsl<.f> 0,limm 0101111000101111F111111110010010. */
+{ "ffsl", 0x5E2F7F92, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* flag c 00100RRR001010010RRRCCCCCCRRRRRR. */
+{ "flag", 0x20290000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { 0 }},
+
+/* flag<.cc> c 00100RRR111010010RRRCCCCCC0QQQQQ. */
+{ "flag", 0x20E90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { C_CC }},
+
+/* flag u6 00100RRR011010010RRRuuuuuuRRRRRR. */
+{ "flag", 0x20690000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* flag<.cc> u6 00100RRR111010010RRRuuuuuu1QQQQQ. */
+{ "flag", 0x20E90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { C_CC }},
+
+/* flag s12 00100RRR101010010RRRssssssSSSSSS. */
+{ "flag", 0x20A90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { SIMM12_20 }, { 0 }},
+
+/* flag limm 00100RRR001010010RRR111110RRRRRR. */
+{ "flag", 0x20290F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { LIMM }, { 0 }},
+
+/* flag<.cc> limm 00100RRR111010010RRR1111100QQQQQ. */
+{ "flag", 0x20E90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { LIMM }, { C_CC }},
+
+/* flagacc c 00101100001011111000CCCCCC111111. */
+{ "flagacc", 0x2C2F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RC_CHK }, { 0 }},
+
+/* flagacc u6 00101100011011111000uuuuuu111111. */
+{ "flagacc", 0x2C6F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { UIMM6_20 }, { 0 }},
+
+/* fls<.f> b,c 00101bbb00101111FBBBCCCCCC010011. */
+{ "fls", 0x282F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, RC }, { C_F }},
+
+/* fls<.f> 0,c 0010111000101111F111CCCCCC010011. */
+{ "fls", 0x2E2F7013, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, RC }, { C_F }},
+
+/* fls<.f> b,u6 00101bbb01101111FBBBuuuuuu010011. */
+{ "fls", 0x286F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }},
+
+/* fls<.f> 0,u6 0010111001101111F111uuuuuu010011. */
+{ "fls", 0x2E6F7013, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }},
+
+/* fls<.f> b,limm 00101bbb00101111FBBB111110010011. */
+{ "fls", 0x282F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, LIMM }, { C_F }},
+
+/* fls<.f> 0,limm 0010111000101111F111111110010011. */
+{ "fls", 0x2E2F7F93, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, LIMM }, { C_F }},
+
+/* flsl<.f> RB,RC 01011bbb00101111FBBBcccccc010011. */
+{ "flsl", 0x582F0013, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* flsl<.f> 0,RC 0101111000101111F111cccccc010011. */
+{ "flsl", 0x5E2F7013, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* flsl<.f> RB,u6 01011bbb01101111FBBBuuuuuu010011. */
+{ "flsl", 0x586F0013, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* flsl<.f> 0,u6 0101111001101111F111uuuuuu010011. */
+{ "flsl", 0x5E6F7013, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* flsl<.f> RB,ximm 01011bbb00101111FBBB111100010011. */
+{ "flsl", 0x582F0F13, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* flsl<.f> 0,ximm 0101111000101111F111111100010011. */
+{ "flsl", 0x5E2F7F13, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* flsl<.f> RB,limm 01011bbb00101111FBBB111110010011. */
+{ "flsl", 0x582F0F93, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* flsl<.f> 0,limm 0101111000101111F111111110010011. */
+{ "flsl", 0x5E2F7F93, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* fmp_adds<.f> a,b,c 00111bbb00100010FBBBCCCCCCAAAAAA. */
+{ "fmp_adds", 0x38220000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, RB, RC }, { C_F }},
+
+/* fmp_adds<.f> 0,b,c 00111bbb00100010FBBBCCCCCC111110. */
+{ "fmp_adds", 0x3822003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RB, RC }, { C_F }},
+
+/* fmp_adds<.f><.cc> b,b,c 00111bbb11100010FBBBCCCCCC0QQQQQ. */
+{ "fmp_adds", 0x38E20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* fmp_adds<.f> a,b,u6 00111bbb01100010FBBBuuuuuuAAAAAA. */
+{ "fmp_adds", 0x38620000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* fmp_adds<.f> 0,b,u6 00111bbb01100010FBBBuuuuuu111110. */
+{ "fmp_adds", 0x3862003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* fmp_adds<.f><.cc> b,b,u6 00111bbb11100010FBBBuuuuuu1QQQQQ. */
+{ "fmp_adds", 0x38E20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* fmp_adds<.f> b,b,s12 00111bbb10100010FBBBssssssSSSSSS. */
+{ "fmp_adds", 0x38A20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* fmp_adds<.f> a,limm,c 0011111000100010F111CCCCCCAAAAAA. */
+{ "fmp_adds", 0x3E227000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, LIMM, RC }, { C_F }},
+
+/* fmp_adds<.f> a,b,limm 00111bbb00100010FBBB111110AAAAAA. */
+{ "fmp_adds", 0x38220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, RB, LIMM }, { C_F }},
+
+/* fmp_adds<.f> 0,limm,c 0011111000100010F111CCCCCC111110. */
+{ "fmp_adds", 0x3E22703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, RC }, { C_F }},
+
+/* fmp_adds<.f> 0,b,limm 00111bbb00100010FBBB111110111110. */
+{ "fmp_adds", 0x38220FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RB, LIMM }, { C_F }},
+
+/* fmp_adds<.f><.cc> b,b,limm 00111bbb11100010FBBB1111100QQQQQ. */
+{ "fmp_adds", 0x38E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* fmp_adds<.f><.cc> 0,limm,c 0011111011100010F111CCCCCC0QQQQQ. */
+{ "fmp_adds", 0x3EE27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* fmp_adds<.f> a,limm,u6 0011111001100010F111uuuuuuAAAAAA. */
+{ "fmp_adds", 0x3E627000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fmp_adds<.f> 0,limm,u6 0011111001100010F111uuuuuu111110. */
+{ "fmp_adds", 0x3E62703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fmp_adds<.f><.cc> 0,limm,u6 0011111011100010F111uuuuuu1QQQQQ. */
+{ "fmp_adds", 0x3EE27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* fmp_adds<.f> 0,limm,s12 0011111010100010F111ssssssSSSSSS. */
+{ "fmp_adds", 0x3EA27000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* fmp_adds<.f> a,limm,limm 0011111000100010F111111110AAAAAA. */
+{ "fmp_adds", 0x3E227F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* fmp_adds<.f> 0,limm,limm 0011111000100010F111111110111110. */
+{ "fmp_adds", 0x3E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* fmp_adds<.f><.cc> 0,limm,limm 0011111011100010F1111111100QQQQQ. */
+{ "fmp_adds", 0x3EE27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* fmp_atan<.f> b,c 00111bbb00101111FBBBCCCCCC100101. */
+{ "fmp_atan", 0x382F0025, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_atan<.f> 0,c 0011111000101111F111CCCCCC100101. */
+{ "fmp_atan", 0x3E2F7025, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_atan<.f> b,u6 00111bbb01101111FBBBuuuuuu100101. */
+{ "fmp_atan", 0x386F0025, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_atan<.f> 0,u6 0011111001101111F111uuuuuu100101. */
+{ "fmp_atan", 0x3E6F7025, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_atan<.f> b,limm 00111bbb00101111FBBB111110100101. */
+{ "fmp_atan", 0x382F0FA5, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_atan<.f> 0,limm 0011111000101111F111111110100101. */
+{ "fmp_atan", 0x3E2F7FA5, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_atan15<.f> b,c 00111bbb00101111FBBBCCCCCC101110. */
+{ "fmp_atan15", 0x382F002E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_atan15<.f> 0,c 0011111000101111F111CCCCCC101110. */
+{ "fmp_atan15", 0x3E2F702E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_atan15<.f> b,u6 00111bbb01101111FBBBuuuuuu101110. */
+{ "fmp_atan15", 0x386F002E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_atan15<.f> 0,u6 0011111001101111F111uuuuuu101110. */
+{ "fmp_atan15", 0x3E6F702E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_atan15<.f> b,limm 00111bbb00101111FBBB111110101110. */
+{ "fmp_atan15", 0x382F0FAE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_atan15<.f> 0,limm 0011111000101111F111111110101110. */
+{ "fmp_atan15", 0x3E2F7FAE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_cos<.f> b,c 00111bbb00101111FBBBCCCCCC011110. */
+{ "fmp_cos", 0x382F001E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_cos<.f> 0,c 0011111000101111F111CCCCCC011110. */
+{ "fmp_cos", 0x3E2F701E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_cos<.f> b,u6 00111bbb01101111FBBBuuuuuu011110. */
+{ "fmp_cos", 0x386F001E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_cos<.f> 0,u6 0011111001101111F111uuuuuu011110. */
+{ "fmp_cos", 0x3E6F701E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_cos<.f> b,limm 00111bbb00101111FBBB111110011110. */
+{ "fmp_cos", 0x382F0F9E, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_cos<.f> 0,limm 0011111000101111F111111110011110. */
+{ "fmp_cos", 0x3E2F7F9E, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_cos15<.f> b,c 00111bbb00101111FBBBCCCCCC101100. */
+{ "fmp_cos15", 0x382F002C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_cos15<.f> 0,c 0011111000101111F111CCCCCC101100. */
+{ "fmp_cos15", 0x3E2F702C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_cos15<.f> b,u6 00111bbb01101111FBBBuuuuuu101100. */
+{ "fmp_cos15", 0x386F002C, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_cos15<.f> 0,u6 0011111001101111F111uuuuuu101100. */
+{ "fmp_cos15", 0x3E6F702C, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_cos15<.f> b,limm 00111bbb00101111FBBB111110101100. */
+{ "fmp_cos15", 0x382F0FAC, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_cos15<.f> 0,limm 0011111000101111F111111110101100. */
+{ "fmp_cos15", 0x3E2F7FAC, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_divf<.f> a,b,c 00111bbb00100000FBBBCCCCCCAAAAAA. */
+{ "fmp_divf", 0x38200000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, RB, RC }, { C_F }},
+
+/* fmp_divf<.f> 0,b,c 00111bbb00100000FBBBCCCCCC111110. */
+{ "fmp_divf", 0x3820003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RB, RC }, { C_F }},
+
+/* fmp_divf<.f><.cc> b,b,c 00111bbb11100000FBBBCCCCCC0QQQQQ. */
+{ "fmp_divf", 0x38E00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* fmp_divf<.f> a,b,u6 00111bbb01100000FBBBuuuuuuAAAAAA. */
+{ "fmp_divf", 0x38600000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* fmp_divf<.f> 0,b,u6 00111bbb01100000FBBBuuuuuu111110. */
+{ "fmp_divf", 0x3860003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* fmp_divf<.f><.cc> b,b,u6 00111bbb11100000FBBBuuuuuu1QQQQQ. */
+{ "fmp_divf", 0x38E00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* fmp_divf<.f> b,b,s12 00111bbb10100000FBBBssssssSSSSSS. */
+{ "fmp_divf", 0x38A00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* fmp_divf<.f> a,limm,c 0011111000100000F111CCCCCCAAAAAA. */
+{ "fmp_divf", 0x3E207000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, LIMM, RC }, { C_F }},
+
+/* fmp_divf<.f> a,b,limm 00111bbb00100000FBBB111110AAAAAA. */
+{ "fmp_divf", 0x38200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, RB, LIMM }, { C_F }},
+
+/* fmp_divf<.f> 0,limm,c 0011111000100000F111CCCCCC111110. */
+{ "fmp_divf", 0x3E20703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, RC }, { C_F }},
+
+/* fmp_divf<.f> 0,b,limm 00111bbb00100000FBBB111110111110. */
+{ "fmp_divf", 0x38200FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RB, LIMM }, { C_F }},
+
+/* fmp_divf<.f><.cc> b,b,limm 00111bbb11100000FBBB1111100QQQQQ. */
+{ "fmp_divf", 0x38E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* fmp_divf<.f><.cc> 0,limm,c 0011111011100000F111CCCCCC0QQQQQ. */
+{ "fmp_divf", 0x3EE07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* fmp_divf<.f> a,limm,u6 0011111001100000F111uuuuuuAAAAAA. */
+{ "fmp_divf", 0x3E607000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fmp_divf<.f> 0,limm,u6 0011111001100000F111uuuuuu111110. */
+{ "fmp_divf", 0x3E60703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fmp_divf<.f><.cc> 0,limm,u6 0011111011100000F111uuuuuu1QQQQQ. */
+{ "fmp_divf", 0x3EE07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* fmp_divf<.f> 0,limm,s12 0011111010100000F111ssssssSSSSSS. */
+{ "fmp_divf", 0x3EA07000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* fmp_divf<.f> a,limm,limm 0011111000100000F111111110AAAAAA. */
+{ "fmp_divf", 0x3E207F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* fmp_divf<.f> 0,limm,limm 0011111000100000F111111110111110. */
+{ "fmp_divf", 0x3E207FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* fmp_divf<.f><.cc> 0,limm,limm 0011111011100000F1111111100QQQQQ. */
+{ "fmp_divf", 0x3EE07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* fmp_divf15<.f> a,b,c 00111bbb00100001FBBBCCCCCCAAAAAA. */
+{ "fmp_divf15", 0x38210000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, RB, RC }, { C_F }},
+
+/* fmp_divf15<.f> 0,b,c 00111bbb00100001FBBBCCCCCC111110. */
+{ "fmp_divf15", 0x3821003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RB, RC }, { C_F }},
+
+/* fmp_divf15<.f><.cc> b,b,c 00111bbb11100001FBBBCCCCCC0QQQQQ. */
+{ "fmp_divf15", 0x38E10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* fmp_divf15<.f> a,b,u6 00111bbb01100001FBBBuuuuuuAAAAAA. */
+{ "fmp_divf15", 0x38610000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* fmp_divf15<.f> 0,b,u6 00111bbb01100001FBBBuuuuuu111110. */
+{ "fmp_divf15", 0x3861003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* fmp_divf15<.f><.cc> b,b,u6 00111bbb11100001FBBBuuuuuu1QQQQQ. */
+{ "fmp_divf15", 0x38E10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* fmp_divf15<.f> b,b,s12 00111bbb10100001FBBBssssssSSSSSS. */
+{ "fmp_divf15", 0x38A10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* fmp_divf15<.f> a,limm,c 0011111000100001F111CCCCCCAAAAAA. */
+{ "fmp_divf15", 0x3E217000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, LIMM, RC }, { C_F }},
+
+/* fmp_divf15<.f> a,b,limm 00111bbb00100001FBBB111110AAAAAA. */
+{ "fmp_divf15", 0x38210F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, RB, LIMM }, { C_F }},
+
+/* fmp_divf15<.f> 0,limm,c 0011111000100001F111CCCCCC111110. */
+{ "fmp_divf15", 0x3E21703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, RC }, { C_F }},
+
+/* fmp_divf15<.f> 0,b,limm 00111bbb00100001FBBB111110111110. */
+{ "fmp_divf15", 0x38210FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RB, LIMM }, { C_F }},
+
+/* fmp_divf15<.f><.cc> b,b,limm 00111bbb11100001FBBB1111100QQQQQ. */
+{ "fmp_divf15", 0x38E10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* fmp_divf15<.f><.cc> 0,limm,c 0011111011100001F111CCCCCC0QQQQQ. */
+{ "fmp_divf15", 0x3EE17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* fmp_divf15<.f> a,limm,u6 0011111001100001F111uuuuuuAAAAAA. */
+{ "fmp_divf15", 0x3E617000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fmp_divf15<.f> 0,limm,u6 0011111001100001F111uuuuuu111110. */
+{ "fmp_divf15", 0x3E61703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* fmp_divf15<.f><.cc> 0,limm,u6 0011111011100001F111uuuuuu1QQQQQ. */
+{ "fmp_divf15", 0x3EE17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* fmp_divf15<.f> 0,limm,s12 0011111010100001F111ssssssSSSSSS. */
+{ "fmp_divf15", 0x3EA17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* fmp_divf15<.f> a,limm,limm 0011111000100001F111111110AAAAAA. */
+{ "fmp_divf15", 0x3E217F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* fmp_divf15<.f> 0,limm,limm 0011111000100001F111111110111110. */
+{ "fmp_divf15", 0x3E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* fmp_divf15<.f><.cc> 0,limm,limm 0011111011100001F1111111100QQQQQ. */
+{ "fmp_divf15", 0x3EE17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* fmp_exp2<.f> b,c 00111bbb00101111FBBBCCCCCC100111. */
+{ "fmp_exp2", 0x382F0027, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_exp2<.f> 0,c 0011111000101111F111CCCCCC100111. */
+{ "fmp_exp2", 0x3E2F7027, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_exp2<.f> b,u6 00111bbb01101111FBBBuuuuuu100111. */
+{ "fmp_exp2", 0x386F0027, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_exp2<.f> 0,u6 0011111001101111F111uuuuuu100111. */
+{ "fmp_exp2", 0x3E6F7027, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_exp2<.f> b,limm 00111bbb00101111FBBB111110100111. */
+{ "fmp_exp2", 0x382F0FA7, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_exp2<.f> 0,limm 0011111000101111F111111110100111. */
+{ "fmp_exp2", 0x3E2F7FA7, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_exp215<.f> b,c 00111bbb00101111FBBBCCCCCC101111. */
+{ "fmp_exp215", 0x382F002F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_exp215<.f> 0,c 0011111000101111F111CCCCCC101111. */
+{ "fmp_exp215", 0x3E2F702F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_exp215<.f> b,u6 00111bbb01101111FBBBuuuuuu101111. */
+{ "fmp_exp215", 0x386F002F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_exp215<.f> 0,u6 0011111001101111F111uuuuuu101111. */
+{ "fmp_exp215", 0x3E6F702F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_exp215<.f> b,limm 00111bbb00101111FBBB111110101111. */
+{ "fmp_exp215", 0x382F0FAF, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_exp215<.f> 0,limm 0011111000101111F111111110101111. */
+{ "fmp_exp215", 0x3E2F7FAF, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_log2<.f> b,c 00111bbb00101111FBBBCCCCCC100110. */
+{ "fmp_log2", 0x382F0026, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_log2<.f> 0,c 0011111000101111F111CCCCCC100110. */
+{ "fmp_log2", 0x3E2F7026, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_log2<.f> b,u6 00111bbb01101111FBBBuuuuuu100110. */
+{ "fmp_log2", 0x386F0026, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_log2<.f> 0,u6 0011111001101111F111uuuuuu100110. */
+{ "fmp_log2", 0x3E6F7026, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_log2<.f> b,limm 00111bbb00101111FBBB111110100110. */
+{ "fmp_log2", 0x382F0FA6, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_log2<.f> 0,limm 0011111000101111F111111110100110. */
+{ "fmp_log2", 0x3E2F7FA6, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_log215<.f> b,c 00111bbb00101111FBBBCCCCCC110000. */
+{ "fmp_log215", 0x382F0030, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_log215<.f> 0,c 0011111000101111F111CCCCCC110000. */
+{ "fmp_log215", 0x3E2F7030, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_log215<.f> b,u6 00111bbb01101111FBBBuuuuuu110000. */
+{ "fmp_log215", 0x386F0030, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_log215<.f> 0,u6 0011111001101111F111uuuuuu110000. */
+{ "fmp_log215", 0x3E6F7030, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_log215<.f> b,limm 00111bbb00101111FBBB111110110000. */
+{ "fmp_log215", 0x382F0FB0, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_log215<.f> 0,limm 0011111000101111F111111110110000. */
+{ "fmp_log215", 0x3E2F7FB0, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_recip<.f> b,c 00111bbb00101111FBBBCCCCCC101010. */
+{ "fmp_recip", 0x382F002A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_recip<.f> 0,c 0011111000101111F111CCCCCC101010. */
+{ "fmp_recip", 0x3E2F702A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_recip<.f> b,u6 00111bbb01101111FBBBuuuuuu101010. */
+{ "fmp_recip", 0x386F002A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_recip<.f> 0,u6 0011111001101111F111uuuuuu101010. */
+{ "fmp_recip", 0x3E6F702A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_recip<.f> b,limm 00111bbb00101111FBBB111110101010. */
+{ "fmp_recip", 0x382F0FAA, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_recip<.f> 0,limm 0011111000101111F111111110101010. */
+{ "fmp_recip", 0x3E2F7FAA, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_recip15<.f> b,c 00111bbb00101111FBBBCCCCCC101011. */
+{ "fmp_recip15", 0x382F002B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_recip15<.f> 0,c 0011111000101111F111CCCCCC101011. */
+{ "fmp_recip15", 0x3E2F702B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_recip15<.f> b,u6 00111bbb01101111FBBBuuuuuu101011. */
+{ "fmp_recip15", 0x386F002B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_recip15<.f> 0,u6 0011111001101111F111uuuuuu101011. */
+{ "fmp_recip15", 0x3E6F702B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_recip15<.f> b,limm 00111bbb00101111FBBB111110101011. */
+{ "fmp_recip15", 0x382F0FAB, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_recip15<.f> 0,limm 0011111000101111F111111110101011. */
+{ "fmp_recip15", 0x3E2F7FAB, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_rndh<.f> b,c 00111bbb00101111FBBBCCCCCC101001. */
+{ "fmp_rndh", 0x382F0029, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_rndh<.f> 0,c 0011111000101111F111CCCCCC101001. */
+{ "fmp_rndh", 0x3E2F7029, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_rndh<.f> b,u6 00111bbb01101111FBBBuuuuuu101001. */
+{ "fmp_rndh", 0x386F0029, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_rndh<.f> 0,u6 0011111001101111F111uuuuuu101001. */
+{ "fmp_rndh", 0x3E6F7029, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_rndh<.f> b,limm 00111bbb00101111FBBB111110101001. */
+{ "fmp_rndh", 0x382F0FA9, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_rndh<.f> 0,limm 0011111000101111F111111110101001. */
+{ "fmp_rndh", 0x3E2F7FA9, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_sath<.f> b,c 00111bbb00101111FBBBCCCCCC101000. */
+{ "fmp_sath", 0x382F0028, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_sath<.f> 0,c 0011111000101111F111CCCCCC101000. */
+{ "fmp_sath", 0x3E2F7028, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_sath<.f> b,u6 00111bbb01101111FBBBuuuuuu101000. */
+{ "fmp_sath", 0x386F0028, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_sath<.f> 0,u6 0011111001101111F111uuuuuu101000. */
+{ "fmp_sath", 0x3E6F7028, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_sath<.f> b,limm 00111bbb00101111FBBB111110101000. */
+{ "fmp_sath", 0x382F0FA8, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_sath<.f> 0,limm 0011111000101111F111111110101000. */
+{ "fmp_sath", 0x3E2F7FA8, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_sin<.f> b,c 00111bbb00101111FBBBCCCCCC011111. */
+{ "fmp_sin", 0x382F001F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_sin<.f> 0,c 0011111000101111F111CCCCCC011111. */
+{ "fmp_sin", 0x3E2F701F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_sin<.f> b,u6 00111bbb01101111FBBBuuuuuu011111. */
+{ "fmp_sin", 0x386F001F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_sin<.f> 0,u6 0011111001101111F111uuuuuu011111. */
+{ "fmp_sin", 0x3E6F701F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_sin<.f> b,limm 00111bbb00101111FBBB111110011111. */
+{ "fmp_sin", 0x382F0F9F, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_sin<.f> 0,limm 0011111000101111F111111110011111. */
+{ "fmp_sin", 0x3E2F7F9F, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_sin15<.f> b,c 00111bbb00101111FBBBCCCCCC101101. */
+{ "fmp_sin15", 0x382F002D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_sin15<.f> 0,c 0011111000101111F111CCCCCC101101. */
+{ "fmp_sin15", 0x3E2F702D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_sin15<.f> b,u6 00111bbb01101111FBBBuuuuuu101101. */
+{ "fmp_sin15", 0x386F002D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_sin15<.f> 0,u6 0011111001101111F111uuuuuu101101. */
+{ "fmp_sin15", 0x3E6F702D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_sin15<.f> b,limm 00111bbb00101111FBBB111110101101. */
+{ "fmp_sin15", 0x382F0FAD, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_sin15<.f> 0,limm 0011111000101111F111111110101101. */
+{ "fmp_sin15", 0x3E2F7FAD, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_sqrtf<.f> b,c 00111bbb00101111FBBBCCCCCC100000. */
+{ "fmp_sqrtf", 0x382F0020, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_sqrtf<.f> 0,c 0011111000101111F111CCCCCC100000. */
+{ "fmp_sqrtf", 0x3E2F7020, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_sqrtf<.f> b,u6 00111bbb01101111FBBBuuuuuu100000. */
+{ "fmp_sqrtf", 0x386F0020, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_sqrtf<.f> 0,u6 0011111001101111F111uuuuuu100000. */
+{ "fmp_sqrtf", 0x3E6F7020, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_sqrtf<.f> b,limm 00111bbb00101111FBBB111110100000. */
+{ "fmp_sqrtf", 0x382F0FA0, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_sqrtf<.f> 0,limm 0011111000101111F111111110100000. */
+{ "fmp_sqrtf", 0x3E2F7FA0, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* fmp_sqrtf15<.f> b,c 00111bbb00101111FBBBCCCCCC100001. */
+{ "fmp_sqrtf15", 0x382F0021, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, RC }, { C_F }},
+
+/* fmp_sqrtf15<.f> 0,c 0011111000101111F111CCCCCC100001. */
+{ "fmp_sqrtf15", 0x3E2F7021, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, RC }, { C_F }},
+
+/* fmp_sqrtf15<.f> b,u6 00111bbb01101111FBBBuuuuuu100001. */
+{ "fmp_sqrtf15", 0x386F0021, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, UIMM6_20 }, { C_F }},
+
+/* fmp_sqrtf15<.f> 0,u6 0011111001101111F111uuuuuu100001. */
+{ "fmp_sqrtf15", 0x3E6F7021, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, UIMM6_20 }, { C_F }},
+
+/* fmp_sqrtf15<.f> b,limm 00111bbb00101111FBBB111110100001. */
+{ "fmp_sqrtf15", 0x382F0FA1, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { RB, LIMM }, { C_F }},
+
+/* fmp_sqrtf15<.f> 0,limm 0011111000101111F111111110100001. */
+{ "fmp_sqrtf15", 0x3E2F7FA1, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, FASTMATH, { ZA, LIMM }, { C_F }},
+
+/* getacc b,c 00101bbb001011110BBBCCCCCC011000. */
+{ "getacc", 0x282F0018, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* getacc 0,c 00101110001011110111CCCCCC011000. */
+{ "getacc", 0x2E2F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* getacc b,u6 00101bbb011011110BBBuuuuuu011000. */
+{ "getacc", 0x286F0018, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* getacc 0,u6 00101110011011110111uuuuuu011000. */
+{ "getacc", 0x2E6F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* getacc b,limm 00101bbb001011110BBB111110011000. */
+{ "getacc", 0x282F0F98, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* getacc 0,limm 00101110001011110111111110011000. */
+{ "getacc", 0x2E2F7F98, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* j c 00100RRR00100000RRRRCCCCCCRRRRRR. */
+{ "j", 0x20200000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* j BLINK 00100RRR00100000RRRR011111RRRRRR. */
+{ "j", 0x202007C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { 0 }},
+
+/* jcc c 00100RRR11100000RRRRCCCCCC0QQQQQ. */
+{ "j", 0x20E00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* jcc BLINK 00100RRR11100000RRRR0111110QQQQQ. */
+{ "j", 0x20E007C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, BLINK, BRAKETdup }, { C_CC }},
+
+/* j.D c 00100RRR00100001RRRRCCCCCCRRRRRR. */
+{ "j", 0x20210000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }},
+
+/* j.D BLINK 00100RRR00100001RRRR011111RRRRRR. */
+{ "j", 0x202107C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_DHARD }},
+
+/* j.Dcc c 00100RRR11100001RRRRCCCCCC0QQQQQ. */
+{ "j", 0x20E10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* j.Dcc BLINK 00100RRR11100001RRRR0111110QQQQQ. */
+{ "j", 0x20E107C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, BLINK, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* j s12 00100RRR10100000RRRRssssssSSSSSS. */
+{ "j", 0x20A00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { SIMM12_20 }, { 0 }},
+
+/* j.D s12 00100RRR10100001RRRRssssssSSSSSS. */
+{ "j", 0x20A10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { SIMM12_20 }, { C_DHARD }},
+
+/* j u6 00100RRR01100000RRRRuuuuuuRRRRRR. */
+{ "j", 0x20600000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { 0 }},
+
+/* jcc u6 00100RRR11100000RRRRuuuuuu1QQQQQ. */
+{ "j", 0x20E00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, COND, { UIMM6_20 }, { C_CC }},
+
+/* j.D u6 00100RRR01100001RRRRuuuuuuRRRRRR. */
+{ "j", 0x20610000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { C_DHARD }},
+
+/* j.Dcc u6 00100RRR11100001RRRRuuuuuu1QQQQQ. */
+{ "j", 0x20E10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, COND, { UIMM6_20 }, { C_CC, C_DHARD }},
+
+/* j limm 00100RRR00100000RRRR111110RRRRRR. */
+{ "j", 0x20200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { LIMM }, { 0 }},
+
+/* jcc limm 00100RRR11100000RRRR1111100QQQQQ. */
+{ "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, COND, { LIMM }, { C_CC }},
+
+/* jeq_sCC_EQ BLINK 0111110011100000. */
+{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_EQ }},
+
+/* jl c 00100RRR00100010RRRRCCCCCCRRRRRR. */
+{ "jl", 0x20220000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* jlcc c 00100RRR11100010RRRRCCCCCC0QQQQQ. */
+{ "jl", 0x20E20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC }},
+
+/* jl.D c 00100RRR00100011RRRRCCCCCCRRRRRR. */
+{ "jl", 0x20230000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }},
+
+/* jl.Dcc c 00100RRR11100011RRRRCCCCCC0QQQQQ. */
+{ "jl", 0x20E30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }},
+
+/* jl s12 00100RRR10100010RRRRssssssSSSSSS. */
+{ "jl", 0x20A20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { SIMM12_20 }, { 0 }},
+
+/* jl.D s12 00100RRR10100011RRRRssssssSSSSSS. */
+{ "jl", 0x20A30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { SIMM12_20 }, { C_DHARD }},
+
+/* jl u6 00100RRR01100010RRRRuuuuuuRRRRRR. */
+{ "jl", 0x20620000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { 0 }},
+
+/* jlcc u6 00100RRR11100010RRRRuuuuuu1QQQQQ. */
+{ "jl", 0x20E20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { C_CC }},
+
+/* jl.D u6 00100RRR01100011RRRRuuuuuuRRRRRR. */
+{ "jl", 0x20630000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { C_DHARD }},
+
+/* jl.Dcc u6 00100RRR11100011RRRRuuuuuu1QQQQQ. */
+{ "jl", 0x20E30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD }},
+
+/* jl limm 00100RRR00100010RRRR111110RRRRRR. */
+{ "jl", 0x20220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { LIMM }, { 0 }},
+
+/* jlcc limm 00100RRR11100010RRRR1111100QQQQQ. */
+{ "jl", 0x20E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { LIMM }, { C_CC }},
+
+/* jli_s u10 01010UUUUUUU1uuu. */
+{ "jli_s", 0x00005008, 0x0000F808, ARC_OPCODE_ARC64, JLI, NONE, { UIMM10_13_S }, { 0 }},
+
+/* jl_s b 01111bbb01000000. */
+{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},
+
+/* jl_s.D b 01111bbb01100000. */
+{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }},
+
+/* jne_sCC_NE BLINK 0111110111100000. */
+{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { C_CC_NE }},
+
+/* j_s b 01111bbb00000000. */
+{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},
+
+/* j_s.D b 01111bbb00100000. */
+{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }},
+
+/* j_s BLINK 0111111011100000. */
+{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+
+/* j_s.D BLINK 0111111111100000. */
+{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { C_DHARD }},
+
+/* kflag c 00100RRR001010011RRRCCCCCCRRRRRR. */
+{ "kflag", 0x20298000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { 0 }},
+
+/* kflag<.cc> c 00100RRR111010011RRRCCCCCC0QQQQQ. */
+{ "kflag", 0x20E98000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { C_CC }},
+
+/* kflag u6 00100RRR011010011RRRuuuuuuRRRRRR. */
+{ "kflag", 0x20698000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* kflag<.cc> u6 00100RRR111010011RRRuuuuuu1QQQQQ. */
+{ "kflag", 0x20E98020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { C_CC }},
+
+/* kflag s12 00100RRR101010011RRRssssssSSSSSS. */
+{ "kflag", 0x20A98000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { SIMM12_20 }, { 0 }},
+
+/* kflag limm 00100RRR001010011RRR111110RRRRRR. */
+{ "kflag", 0x20298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { LIMM }, { 0 }},
+
+/* kflag<.cc> limm 00100RRR111010011RRR1111100QQQQQ. */
+{ "kflag", 0x20E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { LIMM }, { C_CC }},
+
+/* ldZZ_W<.di><.aa> a,b 00010bbb000000000BBBDaa000AAAAAA. */
+{ "ld", 0x10000000, 0xF8FF81C0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }},
+
+/* ldZZ_W<.di><.aa> a,b,c 00100bbbaa110000DBBBCCCCCCAAAAAA. */
+{ "ld", 0x20300000, 0xF83F0000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.di><.aa> 0,b,c 00100bbbaa110000DBBBCCCCCC111110. */
+{ "ld", 0x2030003E, 0xF83F003F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.x><.aa> a,b 00010bbb000000000BBB0aa00XAAAAAA. */
+{ "ld", 0x10000000, 0xF8FF8980, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }},
+
+/* ldZZ_W<.x><.aa> a,b,c 00100bbbaa11000X0BBBCCCCCCAAAAAA. */
+{ "ld", 0x20300000, 0xF83E8000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.x><.aa> 0,b,c 00100bbbaa11000X0BBBCCCCCC111110. */
+{ "ld", 0x2030003E, 0xF83E803F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa000AAAAAA. */
+{ "ld", 0x10000000, 0xF80001C0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }},
+
+/* ldZZ_W<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa000111110. */
+{ "ld", 0x1000003E, 0xF80001FF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }},
+
+/* ldZZ_W<.x><.aa> a,b,s9 00010bbbssssssssSBBB0aa00XAAAAAA. */
+{ "ld", 0x10000000, 0xF8000980, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }},
+
+/* ldZZ_W<.x><.aa> 0,b,s9 00010bbbssssssssSBBB0aa00X111110. */
+{ "ld", 0x1000003E, 0xF80009BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }},
+
+/* ldZZ_W<.di> a,limm 00010110000000000111D00000AAAAAA. */
+{ "ld", 0x16007000, 0xFFFFF7C0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_DI20 }},
+
+/* ldZZ_W<.di> 0,limm 00010110000000000111D00000111110. */
+{ "ld", 0x1600703E, 0xFFFFF7FF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_DI20 }},
+
+/* ldZZ_W<.di><.aa> a,b,limm 00100bbbaa110000DBBB111110AAAAAA. */
+{ "ld", 0x20300F80, 0xF83F0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.di><.aa> a,limm,c 00100110aa110000D111CCCCCCAAAAAA. */
+{ "ld", 0x26307000, 0xFF3F7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.di><.aa> 0,b,limm 00100bbbaa110000DBBB111110111110. */
+{ "ld", 0x20300FBE, 0xF83F0FFF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.di><.aa> 0,limm,c 00100110aa110000D111CCCCCC111110. */
+{ "ld", 0x2630703E, 0xFF3F703F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_DI16, C_AA8 }},
+
+/* ldZZ_W<.x> a,limm 0001011000000000011100000XAAAAAA. */
+{ "ld", 0x16007000, 0xFFFFFF80, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_X25 }},
+
+/* ldZZ_W<.x> 0,limm 0001011000000000011100000X111110. */
+{ "ld", 0x1600703E, 0xFFFFFFBF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_W, C_X25 }},
+
+/* ldZZ_W<.x><.aa> a,b,limm 00100bbbaa11000X0BBB111110AAAAAA. */
+{ "ld", 0x20300F80, 0xF83E8FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.x><.aa> a,b,ximm 00100bbbaa11000X0BBB111100AAAAAA. */
+{ "ld", 0x20300F00, 0xF83E8FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.x><.aa> a,limm,c 00100110aa11000X0111CCCCCCAAAAAA. */
+{ "ld", 0x26307000, 0xFF3EF000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.x><.aa> 0,b,limm 00100bbbaa11000X0BBB111110111110. */
+{ "ld", 0x20300FBE, 0xF83E8FFF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldZZ_W<.di><.aa> a,limm,s9 00010110ssssssssS111Daa000AAAAAA. */
+{ "ld", 0x16007000, 0xFF0071C0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }},
+
+/* ldZZ_W<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa000111110. */
+{ "ld", 0x1600703E, 0xFF0071FF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_DI20, C_AA21 }},
+
+/* ldZZ_W<.x><.aa> a,limm,s9 00010110ssssssssS1110aa00XAAAAAA. */
+{ "ld", 0x16007000, 0xFF007980, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }},
+
+/* ldZZ_W<.x><.aa> 0,limm,s9 00010110ssssssssS1110aa00X111110. */
+{ "ld", 0x1600703E, 0xFF0079BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_W, C_AA21, C_X25 }},
+
+/* ld ZZ_W<.x><.aa> 0,limm,c 00100110aa11000X0111CCCCCC111110. */
+{ "ld ", 0x2630703E, 0xFF3EF03F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, LIMM, RC }, { C_ZZ_W, C_AA8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,b 00010bbb000000000BBBDaa01XAAAAAA. */
+{ "ldb", 0x10000080, 0xF8FF8180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,b,c 00100bbbaa11001XDBBBCCCCCCAAAAAA. */
+{ "ldb", 0x20320000, 0xF83E0000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> 0,b,c 00100bbbaa11001XDBBBCCCCCC111110. */
+{ "ldb", 0x2032003E, 0xF83E003F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa01XAAAAAA. */
+{ "ldb", 0x10000080, 0xF8000180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+
+/* ldbZZ_B<.x><.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa01X111110. */
+{ "ldb", 0x100000BE, 0xF80001BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+
+/* ldbZZ_B<.x><.di> a,ximm 00010100000000000111D0001XAAAAAA. */
+{ "ldb", 0x14007080, 0xFFFFF780, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 }},
+/* ldbZZ_B<.x><.di> a,limm 00010110000000000111D0001XAAAAAA. */
+{ "ldb", 0x16007080, 0xFFFFF780, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 }},
+
+/* ldbZZ_B<.x><.di> 0,limm 00010110000000000111D0001X111110. */
+{ "ldb", 0x160070BE, 0xFFFFF7BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_B, C_DI20, C_X25 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,b,ximm 00100bbbaa11001XDBBB111100AAAAAA. */
+{ "ldb", 0x20320F00, 0xF83E0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+/* ldbZZ_B<.x><.di><.aa> a,b,limm 00100bbbaa11001XDBBB111110AAAAAA. */
+{ "ldb", 0x20320F80, 0xF83E0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,ximm,c 00100100aa11001XD111CCCCCCAAAAAA. */
+{ "ldb", 0x24327000, 0xFF3E7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+/* ldbZZ_B<.x><.di><.aa> a,limm,c 00100110aa11001XD111CCCCCCAAAAAA. */
+{ "ldb", 0x26327000, 0xFF3E7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> 0,b,limm 00100bbbaa11001XDBBB111110111110. */
+{ "ldb", 0x20320FBE, 0xF83E0FFF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> 0,limm,c 00100110aa11001XD111CCCCCC111110. */
+{ "ldb", 0x2632703E, 0xFF3E703F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_B, C_DI16, C_AAB8, C_X15 }},
+
+/* ldbZZ_B<.x><.di><.aa> a,ximm,s9 00010100ssssssssS111Daa01XAAAAAA. */
+{ "ldb", 0x14007080, 0xFF007180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+/* ldbZZ_B<.x><.di><.aa> a,limm,s9 00010110ssssssssS111Daa01XAAAAAA. */
+{ "ldb", 0x16007080, 0xFF007180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+
+/* ldbZZ_B<.x><.di><.aa> 0,limm,s9 00010110ssssssssS111Daa01X111110. */
+{ "ldb", 0x160070BE, 0xFF0071BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_B, C_DI20, C_AAB21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b 00010bbb000000000BBBDaa10XAAAAAA. */
+{ "ldh", 0x10000100, 0xF8FF8180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,c 00100bbbaa11010XDBBBCCCCCCAAAAAA. */
+{ "ldh", 0x20340000, 0xF83E0000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,c 00100bbbaa11010XDBBBCCCCCC111110. */
+{ "ldh", 0x2034003E, 0xF83E003F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa10XAAAAAA. */
+{ "ldh", 0x10000100, 0xF8000180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa10X111110. */
+{ "ldh", 0x1000013E, 0xF80001BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di> a,limm 00010110000000000111D0010XAAAAAA. */
+{ "ldh", 0x16007100, 0xFFFFF780, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }},
+
+/* ldhZZ_H<.x><.di> 0,limm 00010110000000000111D0010X111110. */
+{ "ldh", 0x1600713E, 0xFFFFF7BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,limm 00100bbbaa11010XDBBB111110AAAAAA. */
+{ "ldh", 0x20340F80, 0xF83E0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,ximm 00100bbbaa11010XDBBB111100AAAAAA. */
+{ "ldh", 0x20340F00, 0xF83E0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,limm,c 00100110aa11010XD111CCCCCCAAAAAA. */
+{ "ldh", 0x26347000, 0xFF3E7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,limm 00100bbbaa11010XDBBB111110111110. */
+{ "ldh", 0x20340FBE, 0xF83E0FFF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,limm,c 00100110aa11010XD111CCCCCC111110. */
+{ "ldh", 0x2634703E, 0xFF3E703F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,limm,s9 00010110ssssssssS111Daa10XAAAAAA. */
+{ "ldh", 0x16007100, 0xFF007180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,limm,s9 00010110ssssssssS111Daa10X111110. */
+{ "ldh", 0x1600713E, 0xFF0071BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+
+/* ldhZZ_H<.x><.di><.aa> a,b 00010bbb000000000BBBDaa10XAAAAAA. */
+{ "ldw", 0x10000100, 0xF8FF8180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,c 00100bbbaa11010XDBBBCCCCCCAAAAAA. */
+{ "ldw", 0x20340000, 0xF83E0000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,c 00100bbbaa11010XDBBBCCCCCC111110. */
+{ "ldw", 0x2034003E, 0xF83E003F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa10XAAAAAA. */
+{ "ldw", 0x10000100, 0xF8000180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa10X111110. */
+{ "ldw", 0x1000013E, 0xF80001BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di> a,limm 00010110000000000111D0010XAAAAAA. */
+{ "ldw", 0x16007100, 0xFFFFF780, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }},
+
+/* ldhZZ_H<.x><.di> 0,limm 00010110000000000111D0010X111110. */
+{ "ldw", 0x1600713E, 0xFFFFF7BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_H, C_DI20, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,limm 00100bbbaa11010XDBBB111110AAAAAA. */
+{ "ldw", 0x20340F80, 0xF83E0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,b,ximm 00100bbbaa11010XDBBB111100AAAAAA. */
+{ "ldw", 0x20340F00, 0xF83E0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,limm,c 00100110aa11010XD111CCCCCCAAAAAA. */
+{ "ldw", 0x26347000, 0xFF3E7000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,b,limm 00100bbbaa11010XDBBB111110111110. */
+{ "ldw", 0x20340FBE, 0xF83E0FFF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,limm,c 00100110aa11010XD111CCCCCC111110. */
+{ "ldw", 0x2634703E, 0xFF3E703F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_H, C_DI16, C_AA8, C_X15 }},
+
+/* ldhZZ_H<.x><.di><.aa> a,limm,s9 00010110ssssssssS111Daa10XAAAAAA. */
+{ "ldw", 0x16007100, 0xFF007180, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+/* ldhZZ_H<.x><.di><.aa> 0,limm,s9 00010110ssssssssS111Daa10X111110. */
+{ "ldw", 0x1600713E, 0xFF0071BF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_H, C_DI20, C_AA21, C_X25 }},
+
+
+/* lddl<.aa> a,b 00010bbb000000000BBBq1101QAAAAAA -> lddl a,[b,s9=0] */
+/* lddl<.aa> a,b,s9 00010bbbssssssssSBBBq1101QAAAAAA -> lddl a,[b,s9] */
+/* lddl<.as> a,ximm 00010100000000000111q1101QAAAAAA -> lddl a,[b=60,s9=0] */
+/* lddl<.as> a,limm 00010110000000000111q1101QAAAAAA -> lddl a,[b=62,s9=0] */
+{ "lddl", 0x10000680, 0xF8FF8780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_AA_128S }},
+{ "lddl", 0x10000680, 0xF8000780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA_128S }},
+
+{ "lddl", 0x14007680, 0xFFFFF780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, XIMM, BRAKETdup }, { C_AS_128S }},
+{ "lddl", 0x16007680, 0xFFFFF780, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_AS_128S }},
+
+/* lddl<.aa> a,b,c 00100bbb1111001QQBBBCCCCCCAAAAAA -> lddl a,[b,c] */
+/* lddl<.aa> a,b,ximm 00100bbb1111001QQBBB111100AAAAAA -> lddl a,[b,c=60] */
+/* lddl<.aa> a,b,limm 00100bbb1111001QQBBB111110AAAAAA -> lddl a,[b,c=62] */
+/* lddl<.as> a,ximm,c 001001001111001QQ111CCCCCCAAAAAA -> lddl a,[b=60,c] */
+/* lddl<.as> a,limm,c 001001101111001QQ111CCCCCCAAAAAA -> lddl a,[b=62,c] */
+{ "lddl", 0x20F20000, 0xF8FE0000, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_AA_128 }},
+
+{ "lddl", 0x20F20F00, 0xF8FE0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, XIMM, BRAKETdup }, { C_AA_128 }},
+{ "lddl", 0x20F20F80, 0xF8FE0FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_AA_128 }},
+
+{ "lddl", 0x24F27000, 0xFFFE7000, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, XIMM, RC, BRAKETdup }, { C_AS_128 }},
+{ "lddl", 0x26F27000, 0xFFFE7000, ARC_OPCODE_ARC64, LOAD, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_AS_128 }},
+
+
+/* ldlZZ_L<.aa> a,b 00010bbb000000000BBB1aa001AAAAAA. */
+{ "ldl", 0x10000840, 0xF8FF89C0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldlZZ_L<.aa> 0,b 00010bbb000000000BBB1aa001111110. */
+{ "ldl", 0x1000087E, 0xF8FF89FF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldlZZ_L<.aa> a,b,c 00100bbbaa1100011BBBCCCCCCAAAAAA. */
+{ "ldl", 0x20318000, 0xF83F8000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L<.aa> 0,b,c 00100bbbaa1100011BBBCCCCCC111110. */
+{ "ldl", 0x2031803E, 0xF83F803F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L<.aa> a,b,s9 00010bbbssssssssSBBB1aa001AAAAAA. */
+{ "ldl", 0x10000840, 0xF80009C0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldlZZ_L<.aa> 0,b,s9 00010bbbssssssssSBBB1aa001111110. */
+{ "ldl", 0x1000087E, 0xF80009FF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldlZZ_L 0,limm 00010110000000000111100001111110. */
+{ "ldl", 0x1600787E, 0xFFFFFFFF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L }},
+
+/* ldlZZ_L a,limm 00010110000000000111100001AAAAAA. */
+{ "ldl", 0x16007840, 0xFFFFFFC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L }},
+
+/* ldlZZ_L<.aa> a,b,limm 00100bbbaa1100011BBB111110AAAAAA. */
+{ "ldl", 0x20318F80, 0xF83F8FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L<.aa> a,b,ximm 00100bbbaa1100011BBB111100AAAAAA. */
+{ "ldl", 0x20318F00, 0xF83F8FC0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, RB, XIMM, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L<.aa> 0,b,limm 00100bbbaa1100011BBB111110111110. */
+{ "ldl", 0x20318FBE, 0xF83F8FFF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L 0,limm,c 00100110001100011111CCCCCC111110. */
+{ "ldl", 0x2631F03E, 0xFFFFF03F, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ_L }},
+
+/* ldlZZ_L a,limm,c 00100110aa1100011111CCCCCCAAAAAA. */
+{ "ldl", 0x2631F000, 0xFF3FF000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LO32, RC, BRAKETdup }, { C_ZZ_L, C_AA8 }},
+
+/* ldlZZ_L<.aa> a,ximm,c 00100100aa1100011111CCCCCCAAAAAA. */
+{ "ldl", 0x2431F000, 0xFF3FF000, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, XIMM, RC, BRAKETdup }, { C_ZZ_L , C_AA8 }},
+
+/* ldlZZ_L<.aa> a,limm,s9 00010110ssssssssS1111aa001AAAAAA. */
+{ "ldl", 0x16007840, 0xFF0079C0, ARC_OPCODE_ARC64, LOAD, NONE, { RA_CHK, BRAKET, LO32, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldlZZ_L<.aa> 0,limm,s9 00010110ssssssssS1111aa001111110. */
+{ "ldl", 0x1600787E, 0xFF0079FF, ARC_OPCODE_ARC64, LOAD, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA21 }},
+
+/* ldb_sZZ_B a,b,c 01100bbbccc01aaa. */
+{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_B }},
+
+/* ldb_sZZ_B c,b,u5 10001bbbcccuuuuu. */
+{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B }},
+
+/* ldb_sZZ_B b,SP,u7 11000bbb001uuuuu. */
+{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B }},
+
+/* ldb_sZZ_B R0,GP,s9 1100101sssssssss. */
+{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { C_ZZ_B }},
+
+/* ldh_sZZ_H a,b,c 01100bbbccc10aaa. */
+{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_ZZ_H }},
+
+/* ldh_sZZ_H c,b,u6 10010bbbcccuuuuu. */
+{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }},
+
+/* ldh_sZZ_H.X c,b,u6 10011bbbcccuuuuu. */
+{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H, C_XHARD }},
+
+/* ldh_sZZ_H R0,GP,s10 1100110sssssssss. */
+{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { C_ZZ_H }},
+
+/* ld_s a,b,c 01100bbbccc00aaa. */
+{ "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }},
+
+/* ld_s.AS a,b,c 01001bbbccc00aaa. */
+{ "ld_s", 0x00004800, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, CD2, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_AS }},
+
+/* ld_s b,SP,u7 11000bbb000uuuuu. */
+{ "ld_s", 0x0000C000, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ld_s c,b,u7 10000bbbcccuuuuu. */
+{ "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* ld_s b,PCL,u10 11010bbbuuuuuuuu. */
+{ "ld_s", 0x0000D000, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { RB_S, BRAKET, PCL_S, UIMM10_A32_8_S, BRAKETdup }, { 0 }},
+
+/* ld_s R0,GP,s11 1100100sssssssss. */
+{ "ld_s", 0x0000C800, 0x0000FE00, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, NONE, { R0_S, BRAKET, GP_S, SIMM11_A32_7_S, BRAKETdup }, { 0 }},
+
+/* ld_s R1,GP,s11 01010SSSSSS00sss. */
+{ "ld_s", 0x00005000, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOAD, CD2, { R1_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }},
+
+/* leave_s u7 11000UUU110uuuu0. */
+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LEAVE, CD1, { BRAKET, R13_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }},
+{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LEAVE, CD1, { UIMM7_11_S }, { 0 }},
+
+/* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */
+{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> 0,c 0010011000101111D111CCCCCC010000. */
+{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> b,u6 00100bbb01101111DBBBuuuuuu010000. */
+{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> 0,u6 0010011001101111D111uuuuuu010000. */
+{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> b,limm 00100bbb00101111DBBB111110010000. */
+{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* llock<.di> 0,limm 0010011000101111D111111110010000. */
+{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* llockl<.aq> RB,RC 01011bbb00101111FBBBcccccc010000. */
+{ "llockl", 0x582F0010, 0xF8FF003F, ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_AQ }},
+
+/* lr b,c 00100bbb00101010RBBBCCCCCCRRRRRR. */
+{ "lr", 0x202A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* lr 0,c 0010011000101010R111CCCCCCRRRRRR. */
+{ "lr", 0x262A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { ZA, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* lr b,u6 00100bbb01101010RBBBuuuuuu000000. */
+{ "lr", 0x206A0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* lr 0,u6 0010011001101010R111uuuuuu000000. */
+{ "lr", 0x266A7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* lr b,s12 00100bbb10101010RBBBssssssSSSSSS. */
+{ "lr", 0x20AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* lr 0,s12 0010011010101010R111ssssssSSSSSS. */
+{ "lr", 0x26AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { ZA, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* lr b,limm 00100bbb00101010RBBB111110RRRRRR. */
+{ "lr", 0x202A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* lr 0,limm 0010011000101010R111111110RRRRRR. */
+{ "lr", 0x262A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* lrl RB,RC 01011bbb001010100BBBccccccRRRRRR. */
+{ "lrl", 0x582A0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* lrl RB,u6 01011bbb011010100BBBuuuuuuRRRRRR. */
+{ "lrl", 0x586A0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* lrl RB,s12 01011bbb101010100BBBssssssSSSSSS. */
+{ "lrl", 0x58AA0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* lrl RB,ximm 01011bbb001010100BBB111100RRRRRR. */
+{ "lrl", 0x582A0F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, XIMM, BRAKETdup }, { 0 }},
+
+/* lrl RB,limm 01011bbb001010100BBB111110RRRRRR. */
+{ "lrl", 0x582A0F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* lsl16<.f> b,c 00101bbb00101111FBBBCCCCCC001010. */
+{ "lsl16", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* lsl16<.f> 0,c 0010111000101111F111CCCCCC001010. */
+{ "lsl16", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* lsl16<.f> b,u6 00101bbb01101111FBBBuuuuuu001010. */
+{ "lsl16", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* lsl16<.f> 0,u6 0010111001101111F111uuuuuu001010. */
+{ "lsl16", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsl16<.f> b,limm 00101bbb00101111FBBB111110001010. */
+{ "lsl16", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* lsl16<.f> 0,limm 0010111000101111F111111110001010. */
+{ "lsl16", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* lsl8<.f> b,c 00101bbb00101111FBBBCCCCCC001111. */
+{ "lsl8", 0x282F000F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* lsl8<.f> 0,c 0010111000101111F111CCCCCC001111. */
+{ "lsl8", 0x2E2F700F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* lsl8<.f> b,u6 00101bbb01101111FBBBuuuuuu001111. */
+{ "lsl8", 0x286F000F, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* lsl8<.f> 0,u6 0010111001101111F111uuuuuu001111. */
+{ "lsl8", 0x2E6F700F, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsl8<.f> b,limm 00101bbb00101111FBBB111110001111. */
+{ "lsl8", 0x282F0F8F, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* lsl8<.f> 0,limm 0010111000101111F111111110001111. */
+{ "lsl8", 0x2E2F7F8F, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* lsr<.f> b,c 00100bbb00101111FBBBCCCCCC000010. */
+{ "lsr", 0x202F0002, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* lsr<.f> 0,c 0010011000101111F111CCCCCC000010. */
+{ "lsr", 0x262F7002, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* lsr<.f> a,b,c 00101bbb00000001FBBBCCCCCCAAAAAA. */
+{ "lsr", 0x28010000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* lsr<.f> 0,b,c 00101bbb00000001FBBBCCCCCC111110. */
+{ "lsr", 0x2801003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* lsr<.f><.cc> b,b,c 00101bbb11000001FBBBCCCCCC0QQQQQ. */
+{ "lsr", 0x28C10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* lsr<.f> b,u6 00100bbb01101111FBBBuuuuuu000010. */
+{ "lsr", 0x206F0002, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> 0,u6 0010011001101111F111uuuuuu000010. */
+{ "lsr", 0x266F7002, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> a,b,u6 00101bbb01000001FBBBuuuuuuAAAAAA. */
+{ "lsr", 0x28410000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> 0,b,u6 00101bbb01000001FBBBuuuuuu111110. */
+{ "lsr", 0x2841003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* lsr<.f><.cc> b,b,u6 00101bbb11000001FBBBuuuuuu1QQQQQ. */
+{ "lsr", 0x28C10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsr<.f> b,b,s12 00101bbb10000001FBBBssssssSSSSSS. */
+{ "lsr", 0x28810000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* lsr<.f> b,limm 00100bbb00101111FBBB111110000010. */
+{ "lsr", 0x202F0F82, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* lsr<.f> 0,limm 0010011000101111F111111110000010. */
+{ "lsr", 0x262F7F82, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* lsr<.f> a,limm,c 0010111000000001F111CCCCCCAAAAAA. */
+{ "lsr", 0x2E017000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* lsr<.f> a,b,limm 00101bbb00000001FBBB111110AAAAAA. */
+{ "lsr", 0x28010F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* lsr<.f> 0,limm,c 0010111000000001F111CCCCCC111110. */
+{ "lsr", 0x2E01703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* lsr<.f> 0,b,limm 00101bbb00000001FBBB111110111110. */
+{ "lsr", 0x28010FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* lsr<.f><.cc> b,b,limm 00101bbb11000001FBBB1111100QQQQQ. */
+{ "lsr", 0x28C10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* lsr<.f><.cc> 0,limm,c 0010111011000001F111CCCCCC0QQQQQ. */
+{ "lsr", 0x2EC17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* lsr<.f> a,limm,u6 0010111001000001F111uuuuuuAAAAAA. */
+{ "lsr", 0x2E417000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsr<.f> 0,limm,u6 0010111001000001F111uuuuuu111110. */
+{ "lsr", 0x2E41703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsr<.f><.cc> 0,limm,u6 0010111011000001F111uuuuuu1QQQQQ. */
+{ "lsr", 0x2EC17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsr<.f> 0,limm,s12 0010111010000001F111ssssssSSSSSS. */
+{ "lsr", 0x2E817000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* lsr<.f> a,limm,limm 0010111000000001F111111110AAAAAA. */
+{ "lsr", 0x2E017F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* lsr<.f> 0,limm,limm 0010111000000001F111111110111110. */
+{ "lsr", 0x2E017FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* lsr<.f><.cc> 0,limm,limm 0010111011000001F1111111100QQQQQ. */
+{ "lsr", 0x2EC17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* lsr16<.f> b,c 00101bbb00101111FBBBCCCCCC001011. */
+{ "lsr16", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* lsr16<.f> 0,c 0010111000101111F111CCCCCC001011. */
+{ "lsr16", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* lsr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001011. */
+{ "lsr16", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* lsr16<.f> 0,u6 0010111001101111F111uuuuuu001011. */
+{ "lsr16", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsr16<.f> b,limm 00101bbb00101111FBBB111110001011. */
+{ "lsr16", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* lsr16<.f> 0,limm 0010111000101111F111111110001011. */
+{ "lsr16", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* lsr8<.f> b,c 00101bbb00101111FBBBCCCCCC001110. */
+{ "lsr8", 0x282F000E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, RC }, { C_F }},
+
+/* lsr8<.f> 0,c 0010111000101111F111CCCCCC001110. */
+{ "lsr8", 0x2E2F700E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, RC }, { C_F }},
+
+/* lsr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001110. */
+{ "lsr8", 0x286F000E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* lsr8<.f> 0,u6 0010111001101111F111uuuuuu001110. */
+{ "lsr8", 0x2E6F700E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* lsr8<.f> b,limm 00101bbb00101111FBBB111110001110. */
+{ "lsr8", 0x282F0F8E, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { RB, LIMM }, { C_F }},
+
+/* lsr8<.f> 0,limm 0010111000101111F111111110001110. */
+{ "lsr8", 0x2E2F7F8E, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* lsrl<.f> RA,RB,RC 01011bbb00100001FBBBccccccaaaaaa. */
+{ "lsrl", 0x58210000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* lsrl<.f> 0,RB,RC 01011bbb00100001FBBBcccccc111110. */
+{ "lsrl", 0x5821003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* lsrl<.f><.cc> RB,RB,RC 01011bbb11100001FBBBcccccc0QQQQQ. */
+{ "lsrl", 0x58E10000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* lsrl<.f> RA,RB,u6 01011bbb01100001FBBBuuuuuuaaaaaa. */
+{ "lsrl", 0x58610000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f> 0,RB,u6 01011bbb01100001FBBBuuuuuu111110. */
+{ "lsrl", 0x5861003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f><.cc> RB,RB,u6 01011bbb11100001FBBBuuuuuu1QQQQQ. */
+{ "lsrl", 0x58E10020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsrl<.f> RB,RB,s12 01011bbb10100001FBBBssssssSSSSSS. */
+{ "lsrl", 0x58A10000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* lsrl<.f> RA,ximm,RC 0101110000100001F111ccccccaaaaaa. */
+{ "lsrl", 0x5C217000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* lsrl<.f> RA,RB,ximm 01011bbb00100001FBBB111100aaaaaa. */
+{ "lsrl", 0x58210F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* lsrl<.f> 0,ximm,RC 0101110000100001F111cccccc111110. */
+{ "lsrl", 0x5C21703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* lsrl<.f> 0,RB,ximm 01011bbb00100001FBBB111100111110. */
+{ "lsrl", 0x58210F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* lsrl<.f><.cc> 0,ximm,RC 0101110011100001F111cccccc0QQQQQ. */
+{ "lsrl", 0x5CE17000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* lsrl<.f><.cc> RB,RB,ximm 01011bbb11100001FBBB1111000QQQQQ. */
+{ "lsrl", 0x58E10F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* lsrl<.f> RA,ximm,u6 0101110001100001F111uuuuuuaaaaaa. */
+{ "lsrl", 0x5C617000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f> 0,ximm,u6 0101110001100001F111uuuuuu111110. */
+{ "lsrl", 0x5C61703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f><.cc> 0,ximm,u6 0101110011100001F111uuuuuu1QQQQQ. */
+{ "lsrl", 0x5CE17020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsrl<.f> RA,limm,RC 0101111000100001F111ccccccaaaaaa. */
+{ "lsrl", 0x5E217000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* lsrl<.f> RA,RB,limm 01011bbb00100001FBBB111110aaaaaa. */
+{ "lsrl", 0x58210F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* lsrl<.f> 0,limm,RC 0101111000100001F111cccccc111110. */
+{ "lsrl", 0x5E21703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* lsrl<.f> 0,RB,limm 01011bbb00100001FBBB111110111110. */
+{ "lsrl", 0x58210FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* lsrl<.f><.cc> 0,limm,RC 0101111011100001F111cccccc0QQQQQ. */
+{ "lsrl", 0x5EE17000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* lsrl<.f><.cc> RB,RB,limm 01011bbb11100001FBBB1111100QQQQQ. */
+{ "lsrl", 0x58E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* lsrl<.f> RA,limm,u6 0101111001100001F111uuuuuuaaaaaa. */
+{ "lsrl", 0x5E617000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f> 0,limm,u6 0101111001100001F111uuuuuu111110. */
+{ "lsrl", 0x5E61703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* lsrl<.f><.cc> 0,limm,u6 0101111011100001F111uuuuuu1QQQQQ. */
+{ "lsrl", 0x5EE17020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* lsrl<.f> 0,ximm,s12 0101110010100001F111ssssssSSSSSS. */
+{ "lsrl", 0x5CA17000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* lsrl<.f> 0,limm,s12 0101111010100001F111ssssssSSSSSS. */
+{ "lsrl", 0x5EA17000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* lsrl<.f> RA,ximm,ximm 0101110000100001F111111100aaaaaa. */
+{ "lsrl", 0x5C217F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* lsrl<.f> 0,ximm,ximm 0101110000100001F111111100111110. */
+{ "lsrl", 0x5C217F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* lsrl<.f><.cc> 0,ximm,ximm 0101110011100001F1111111000QQQQQ. */
+{ "lsrl", 0x5CE17F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* lsrl<.f> RA,limm,limm 0101111000100001F111111110aaaaaa. */
+{ "lsrl", 0x5E217F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* lsrl<.f> 0,limm,limm 0101111000100001F111111110111110. */
+{ "lsrl", 0x5E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* lsrl<.f><.cc> 0,limm,limm 0101111011100001F1111111100QQQQQ. */
+{ "lsrl", 0x5EE17F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* lsr_s b,c 01111bbbccc11101. */
+{ "lsr_s", 0x0000781D, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* lsr_s b,b,c 01111bbbccc11001. */
+{ "lsr_s", 0x00007819, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* lsr_s b,b,u5 10111bbb001uuuuu. */
+{ "lsr_s", 0x0000B820, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* lstl<.f> RB,RC 01011bbb00101111FBBBcccccc000010. */
+{ "lstl", 0x582F0002, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* lstl<.f> 0,RC 0101111000101111F111cccccc000010. */
+{ "lstl", 0x5E2F7002, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* lstl<.f> RB,u6 01011bbb01101111FBBBuuuuuu000010. */
+{ "lstl", 0x586F0002, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* lstl<.f> 0,u6 0101111001101111F111uuuuuu000010. */
+{ "lstl", 0x5E6F7002, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* lstl<.f> RB,ximm 01011bbb00101111FBBB111100000010. */
+{ "lstl", 0x582F0F02, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* lstl<.f> 0,ximm 0101111000101111F111111100000010. */
+{ "lstl", 0x5E2F7F02, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* lstl<.f> RB,limm 01011bbb00101111FBBB111110000010. */
+{ "lstl", 0x582F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* lstl<.f> 0,limm 0101111000101111F111111110000010. */
+{ "lstl", 0x5E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* mac<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA. */
+{ "mac", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mac<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110. */
+{ "mac", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* mac<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ. */
+{ "mac", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mac<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA. */
+{ "mac", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mac<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110. */
+{ "mac", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mac<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ. */
+{ "mac", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mac<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS. */
+{ "mac", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mac<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA. */
+{ "mac", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mac<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA. */
+{ "mac", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mac<.f> 0,limm,c 0010111000001110F111CCCCCC111110. */
+{ "mac", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* mac<.f> 0,b,limm 00101bbb00001110FBBB111110111110. */
+{ "mac", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* mac<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ. */
+{ "mac", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mac<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ. */
+{ "mac", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mac<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA. */
+{ "mac", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mac<.f> 0,limm,u6 0010111001001110F111uuuuuu111110. */
+{ "mac", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mac<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ. */
+{ "mac", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mac<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS. */
+{ "mac", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mac<.f> a,limm,limm 0010111000001110F111111110AAAAAA. */
+{ "mac", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mac<.f> 0,limm,limm 0010111000001110F111111110111110. */
+{ "mac", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mac<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ. */
+{ "mac", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macd<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA. */
+{ "macd", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { C_F }},
+
+/* macd<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110. */
+{ "macd", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* macd<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ. */
+{ "macd", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macd<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA. */
+{ "macd", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macd<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110. */
+{ "macd", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macd<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ. */
+{ "macd", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macd<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS. */
+{ "macd", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macd<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA. */
+{ "macd", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macd<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA. */
+{ "macd", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macd<.f> 0,limm,c 0010111000011010F111CCCCCC111110. */
+{ "macd", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* macd<.f> 0,b,limm 00101bbb00011010FBBB111110111110. */
+{ "macd", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* macd<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ. */
+{ "macd", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macd<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ. */
+{ "macd", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macd<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA. */
+{ "macd", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macd<.f> 0,limm,u6 0010111001011010F111uuuuuu111110. */
+{ "macd", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macd<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ. */
+{ "macd", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macd<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS. */
+{ "macd", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macd<.f> a,limm,limm 0010111000011010F111111110AAAAAA. */
+{ "macd", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macd<.f> 0,limm,limm 0010111000011010F111111110111110. */
+{ "macd", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macd<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ. */
+{ "macd", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macdf<.f> a,b,c 00110bbb00010011FBBBCCCCCCAAAAAA. */
+{ "macdf", 0x30130000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macdf<.f> 0,b,c 00110bbb00010011FBBBCCCCCC111110. */
+{ "macdf", 0x3013003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macdf<.f><.cc> b,b,c 00110bbb11010011FBBBCCCCCC0QQQQQ. */
+{ "macdf", 0x30D30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macdf<.f> a,b,u6 00110bbb01010011FBBBuuuuuuAAAAAA. */
+{ "macdf", 0x30530000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macdf<.f> 0,b,u6 00110bbb01010011FBBBuuuuuu111110. */
+{ "macdf", 0x3053003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macdf<.f><.cc> b,b,u6 00110bbb11010011FBBBuuuuuu1QQQQQ. */
+{ "macdf", 0x30D30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdf<.f> b,b,s12 00110bbb10010011FBBBssssssSSSSSS. */
+{ "macdf", 0x30930000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macdf<.f> a,limm,c 0011011000010011F111CCCCCCAAAAAA. */
+{ "macdf", 0x36137000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macdf<.f> a,b,limm 00110bbb00010011FBBB111110AAAAAA. */
+{ "macdf", 0x30130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macdf<.f> 0,limm,c 0011011000010011F111CCCCCC111110. */
+{ "macdf", 0x3613703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macdf<.f> 0,b,limm 00110bbb00010011FBBB111110111110. */
+{ "macdf", 0x30130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macdf<.f><.cc> b,b,limm 00110bbb11010011FBBB1111100QQQQQ. */
+{ "macdf", 0x30D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macdf<.f><.cc> 0,limm,c 0011011011010011F111CCCCCC0QQQQQ. */
+{ "macdf", 0x36D37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macdf<.f> a,limm,u6 0011011001010011F111uuuuuuAAAAAA. */
+{ "macdf", 0x36537000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdf<.f> 0,limm,u6 0011011001010011F111uuuuuu111110. */
+{ "macdf", 0x3653703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdf<.f><.cc> 0,limm,u6 0011011011010011F111uuuuuu1QQQQQ. */
+{ "macdf", 0x36D37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdf<.f> 0,limm,s12 0011011010010011F111ssssssSSSSSS. */
+{ "macdf", 0x36937000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macdf<.f> a,limm,limm 0011011000010011F111111110AAAAAA. */
+{ "macdf", 0x36137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macdf<.f> 0,limm,limm 0011011000010011F111111110111110. */
+{ "macdf", 0x36137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macdf<.f><.cc> 0,limm,limm 0011011011010011F1111111100QQQQQ. */
+{ "macdf", 0x36D37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macdu<.f> a,b,c 00101bbb00011011FBBBCCCCCCAAAAAA. */
+{ "macdu", 0x281B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { C_F }},
+
+/* macdu<.f> 0,b,c 00101bbb00011011FBBBCCCCCC111110. */
+{ "macdu", 0x281B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* macdu<.f><.cc> b,b,c 00101bbb11011011FBBBCCCCCC0QQQQQ. */
+{ "macdu", 0x28DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macdu<.f> a,b,u6 00101bbb01011011FBBBuuuuuuAAAAAA. */
+{ "macdu", 0x285B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macdu<.f> 0,b,u6 00101bbb01011011FBBBuuuuuu111110. */
+{ "macdu", 0x285B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macdu<.f><.cc> b,b,u6 00101bbb11011011FBBBuuuuuu1QQQQQ. */
+{ "macdu", 0x28DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdu<.f> b,b,s12 00101bbb10011011FBBBssssssSSSSSS. */
+{ "macdu", 0x289B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macdu<.f> a,limm,c 0010111000011011F111CCCCCCAAAAAA. */
+{ "macdu", 0x2E1B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macdu<.f> a,b,limm 00101bbb00011011FBBB111110AAAAAA. */
+{ "macdu", 0x281B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macdu<.f> 0,limm,c 0010111000011011F111CCCCCC111110. */
+{ "macdu", 0x2E1B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* macdu<.f> 0,b,limm 00101bbb00011011FBBB111110111110. */
+{ "macdu", 0x281B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* macdu<.f><.cc> b,b,limm 00101bbb11011011FBBB1111100QQQQQ. */
+{ "macdu", 0x28DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macdu<.f><.cc> 0,limm,c 0010111011011011F111CCCCCC0QQQQQ. */
+{ "macdu", 0x2EDB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macdu<.f> a,limm,u6 0010111001011011F111uuuuuuAAAAAA. */
+{ "macdu", 0x2E5B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdu<.f> 0,limm,u6 0010111001011011F111uuuuuu111110. */
+{ "macdu", 0x2E5B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macdu<.f><.cc> 0,limm,u6 0010111011011011F111uuuuuu1QQQQQ. */
+{ "macdu", 0x2EDB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macdu<.f> 0,limm,s12 0010111010011011F111ssssssSSSSSS. */
+{ "macdu", 0x2E9B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macdu<.f> a,limm,limm 0010111000011011F111111110AAAAAA. */
+{ "macdu", 0x2E1B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macdu<.f> 0,limm,limm 0010111000011011F111111110111110. */
+{ "macdu", 0x2E1B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macdu<.f><.cc> 0,limm,limm 0010111011011011F1111111100QQQQQ. */
+{ "macdu", 0x2EDB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macf<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA. */
+{ "macf", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macf<.f> 0,b,c 00110bbb00001100FBBBCCCCCC111110. */
+{ "macf", 0x300C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macf<.f><.cc> b,b,c 00110bbb11001100FBBBCCCCCC0QQQQQ. */
+{ "macf", 0x30CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macf<.f> a,b,u6 00110bbb01001100FBBBuuuuuuAAAAAA. */
+{ "macf", 0x304C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macf<.f> 0,b,u6 00110bbb01001100FBBBuuuuuu111110. */
+{ "macf", 0x304C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macf<.f><.cc> b,b,u6 00110bbb11001100FBBBuuuuuu1QQQQQ. */
+{ "macf", 0x30CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macf<.f> b,b,s12 00110bbb10001100FBBBssssssSSSSSS. */
+{ "macf", 0x308C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macf<.f> a,limm,c 0011011000001100F111CCCCCCAAAAAA. */
+{ "macf", 0x360C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macf<.f> a,b,limm 00110bbb00001100FBBB111110AAAAAA. */
+{ "macf", 0x300C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macf<.f> 0,limm,c 0011011000001100F111CCCCCC111110. */
+{ "macf", 0x360C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macf<.f> 0,b,limm 00110bbb00001100FBBB111110111110. */
+{ "macf", 0x300C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macf<.f><.cc> b,b,limm 00110bbb11001100FBBB1111100QQQQQ. */
+{ "macf", 0x30CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macf<.f><.cc> 0,limm,c 0011011011001100F111CCCCCC0QQQQQ. */
+{ "macf", 0x36CC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macf<.f> a,limm,u6 0011011001001100F111uuuuuuAAAAAA. */
+{ "macf", 0x364C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macf<.f> 0,limm,u6 0011011001001100F111uuuuuu111110. */
+{ "macf", 0x364C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macf<.f><.cc> 0,limm,u6 0011011011001100F111uuuuuu1QQQQQ. */
+{ "macf", 0x36CC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macf<.f> 0,limm,s12 0011011010001100F111ssssssSSSSSS. */
+{ "macf", 0x368C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macf<.f> a,limm,limm 0011011000001100F111111110AAAAAA. */
+{ "macf", 0x360C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macf<.f> 0,limm,limm 0011011000001100F111111110111110. */
+{ "macf", 0x360C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macf<.f><.cc> 0,limm,limm 0011011011001100F1111111100QQQQQ. */
+{ "macf", 0x36CC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macfr<.f> a,b,c 00110bbb00001101FBBBCCCCCCAAAAAA. */
+{ "macfr", 0x300D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macfr<.f> 0,b,c 00110bbb00001101FBBBCCCCCC111110. */
+{ "macfr", 0x300D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macfr<.f><.cc> b,b,c 00110bbb11001101FBBBCCCCCC0QQQQQ. */
+{ "macfr", 0x30CD0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macfr<.f> a,b,u6 00110bbb01001101FBBBuuuuuuAAAAAA. */
+{ "macfr", 0x304D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macfr<.f> 0,b,u6 00110bbb01001101FBBBuuuuuu111110. */
+{ "macfr", 0x304D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macfr<.f><.cc> b,b,u6 00110bbb11001101FBBBuuuuuu1QQQQQ. */
+{ "macfr", 0x30CD0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macfr<.f> b,b,s12 00110bbb10001101FBBBssssssSSSSSS. */
+{ "macfr", 0x308D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macfr<.f> a,limm,c 0011011000001101F111CCCCCCAAAAAA. */
+{ "macfr", 0x360D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macfr<.f> a,b,limm 00110bbb00001101FBBB111110AAAAAA. */
+{ "macfr", 0x300D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macfr<.f> 0,limm,c 0011011000001101F111CCCCCC111110. */
+{ "macfr", 0x360D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macfr<.f> 0,b,limm 00110bbb00001101FBBB111110111110. */
+{ "macfr", 0x300D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macfr<.f><.cc> b,b,limm 00110bbb11001101FBBB1111100QQQQQ. */
+{ "macfr", 0x30CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macfr<.f><.cc> 0,limm,c 0011011011001101F111CCCCCC0QQQQQ. */
+{ "macfr", 0x36CD7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macfr<.f> a,limm,u6 0011011001001101F111uuuuuuAAAAAA. */
+{ "macfr", 0x364D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macfr<.f> 0,limm,u6 0011011001001101F111uuuuuu111110. */
+{ "macfr", 0x364D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macfr<.f><.cc> 0,limm,u6 0011011011001101F111uuuuuu1QQQQQ. */
+{ "macfr", 0x36CD7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macfr<.f> 0,limm,s12 0011011010001101F111ssssssSSSSSS. */
+{ "macfr", 0x368D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macfr<.f> a,limm,limm 0011011000001101F111111110AAAAAA. */
+{ "macfr", 0x360D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macfr<.f> 0,limm,limm 0011011000001101F111111110111110. */
+{ "macfr", 0x360D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macfr<.f><.cc> 0,limm,limm 0011011011001101F1111111100QQQQQ. */
+{ "macfr", 0x36CD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macu<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA. */
+{ "macu", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { C_F }},
+
+/* macu<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110. */
+{ "macu", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { C_F }},
+
+/* macu<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ. */
+{ "macu", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macu<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA. */
+{ "macu", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macu<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110. */
+{ "macu", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macu<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ. */
+{ "macu", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macu<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS. */
+{ "macu", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macu<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA. */
+{ "macu", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macu<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA. */
+{ "macu", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macu<.f> 0,limm,c 0010111000001111F111CCCCCC111110. */
+{ "macu", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F }},
+
+/* macu<.f> 0,b,limm 00101bbb00001111FBBB111110111110. */
+{ "macu", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { C_F }},
+
+/* macu<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ. */
+{ "macu", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macu<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ. */
+{ "macu", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macu<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA. */
+{ "macu", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macu<.f> 0,limm,u6 0010111001001111F111uuuuuu111110. */
+{ "macu", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macu<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ. */
+{ "macu", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macu<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS. */
+{ "macu", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macu<.f> a,limm,limm 0010111000001111F111111110AAAAAA. */
+{ "macu", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macu<.f> 0,limm,limm 0010111000001111F111111110111110. */
+{ "macu", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macu<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ. */
+{ "macu", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhfl<.f> a,b,c 00110bbb00100110FBBBCCCCCCAAAAAA. */
+{ "macwhfl", 0x30260000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macwhfl<.f> 0,b,c 00110bbb00100110FBBBCCCCCC111110. */
+{ "macwhfl", 0x3026003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhfl<.f><.cc> b,b,c 00110bbb11100110FBBBCCCCCC0QQQQQ. */
+{ "macwhfl", 0x30E60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhfl<.f> a,b,u6 00110bbb01100110FBBBuuuuuuAAAAAA. */
+{ "macwhfl", 0x30660000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macwhfl<.f> 0,b,u6 00110bbb01100110FBBBuuuuuu111110. */
+{ "macwhfl", 0x3066003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhfl<.f><.cc> b,b,u6 00110bbb11100110FBBBuuuuuu1QQQQQ. */
+{ "macwhfl", 0x30E60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhfl<.f> b,b,s12 00110bbb10100110FBBBssssssSSSSSS. */
+{ "macwhfl", 0x30A60000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhfl<.f> a,limm,c 0011011000100110F111CCCCCCAAAAAA. */
+{ "macwhfl", 0x36267000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macwhfl<.f> a,b,limm 00110bbb00100110FBBB111110AAAAAA. */
+{ "macwhfl", 0x30260F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macwhfl<.f> 0,limm,c 0011011001100110F111CCCCCC111110. */
+{ "macwhfl", 0x3666703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhfl<.f> 0,b,limm 00110bbb00100110FBBB111110111110. */
+{ "macwhfl", 0x30260FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhfl<.f><.cc> b,b,limm 00110bbb11100110FBBB1111100QQQQQ. */
+{ "macwhfl", 0x30E60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhfl<.f><.cc> 0,limm,c 0011011011100110F111CCCCCC0QQQQQ. */
+{ "macwhfl", 0x36E67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhfl<.f> a,limm,u6 0011011001100110F111uuuuuuAAAAAA. */
+{ "macwhfl", 0x36667000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhfl<.f> 0,limm,u6 0011011001100110F111uuuuuu111110. */
+{ "macwhfl", 0x3666703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhfl<.f><.cc> 0,limm,u6 0011011011100110F111uuuuuu1QQQQQ. */
+{ "macwhfl", 0x36E67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhfl<.f> 0,limm,s12 0011011010100110F111ssssssSSSSSS. */
+{ "macwhfl", 0x36A67000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhfl<.f> a,limm,limm 0011011000100110F111111110AAAAAA. */
+{ "macwhfl", 0x36267F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macwhfl<.f> 0,limm,limm 0011011000100110F111111110111110. */
+{ "macwhfl", 0x36267FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhfl<.f><.cc> 0,limm,limm 0011011011100110F1111111100QQQQQ. */
+{ "macwhfl", 0x36E67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhflr<.f> a,b,c 00110bbb00100111FBBBCCCCCCAAAAAA. */
+{ "macwhflr", 0x30270000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macwhflr<.f> 0,b,c 00110bbb00100111FBBBCCCCCC111110. */
+{ "macwhflr", 0x3027003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhflr<.f><.cc> b,b,c 00110bbb11100111FBBBCCCCCC0QQQQQ. */
+{ "macwhflr", 0x30E70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhflr<.f> a,b,u6 00110bbb01100111FBBBuuuuuuAAAAAA. */
+{ "macwhflr", 0x30670000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macwhflr<.f> 0,b,u6 00110bbb01100111FBBBuuuuuu111110. */
+{ "macwhflr", 0x3067003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhflr<.f><.cc> b,b,u6 00110bbb11100111FBBBuuuuuu1QQQQQ. */
+{ "macwhflr", 0x30E70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhflr<.f> b,b,s12 00110bbb10100111FBBBssssssSSSSSS. */
+{ "macwhflr", 0x30A70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhflr<.f> a,limm,c 0011011000100111F111CCCCCCAAAAAA. */
+{ "macwhflr", 0x36277000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macwhflr<.f> a,b,limm 00110bbb00100111FBBB111110AAAAAA. */
+{ "macwhflr", 0x30270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macwhflr<.f> 0,limm,c 0011011001100111F111CCCCCC111110. */
+{ "macwhflr", 0x3667703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhflr<.f> 0,b,limm 00110bbb00100111FBBB111110111110. */
+{ "macwhflr", 0x30270FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhflr<.f><.cc> b,b,limm 00110bbb11100111FBBB1111100QQQQQ. */
+{ "macwhflr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhflr<.f><.cc> 0,limm,c 0011011011100111F111CCCCCC0QQQQQ. */
+{ "macwhflr", 0x36E77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhflr<.f> a,limm,u6 0011011001100111F111uuuuuuAAAAAA. */
+{ "macwhflr", 0x36677000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhflr<.f> 0,limm,u6 0011011001100111F111uuuuuu111110. */
+{ "macwhflr", 0x3667703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhflr<.f><.cc> 0,limm,u6 0011011011100111F111uuuuuu1QQQQQ. */
+{ "macwhflr", 0x36E77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhflr<.f> 0,limm,s12 0011011010100111F111ssssssSSSSSS. */
+{ "macwhflr", 0x36A77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhflr<.f> a,limm,limm 0011011000100111F111111110AAAAAA. */
+{ "macwhflr", 0x36277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macwhflr<.f> 0,limm,limm 0011011000100111F111111110111110. */
+{ "macwhflr", 0x36277FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhflr<.f><.cc> 0,limm,limm 0011011011100111F1111111100QQQQQ. */
+{ "macwhflr", 0x36E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhfm<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA. */
+{ "macwhfm", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macwhfm<.f> 0,b,c 00110bbb00100010FBBBCCCCCC111110. */
+{ "macwhfm", 0x3022003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhfm<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ. */
+{ "macwhfm", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhfm<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA. */
+{ "macwhfm", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macwhfm<.f> 0,b,u6 00110bbb01100010FBBBuuuuuu111110. */
+{ "macwhfm", 0x3062003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhfm<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ. */
+{ "macwhfm", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhfm<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS. */
+{ "macwhfm", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhfm<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA. */
+{ "macwhfm", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macwhfm<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA. */
+{ "macwhfm", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macwhfm<.f> 0,limm,c 0011011001100010F111CCCCCC111110. */
+{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhfm<.f> 0,b,limm 00110bbb00100010FBBB111110111110. */
+{ "macwhfm", 0x30220FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhfm<.f><.cc> b,b,limm 00110bbb11100010FBBB1111100QQQQQ. */
+{ "macwhfm", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhfm<.f><.cc> 0,limm,c 0011011011100010F111CCCCCC0QQQQQ. */
+{ "macwhfm", 0x36E27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhfm<.f> a,limm,u6 0011011001100010F111uuuuuuAAAAAA. */
+{ "macwhfm", 0x36627000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhfm<.f> 0,limm,u6 0011011001100010F111uuuuuu111110. */
+{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhfm<.f><.cc> 0,limm,u6 0011011011100010F111uuuuuu1QQQQQ. */
+{ "macwhfm", 0x36E27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhfm<.f> 0,limm,s12 0011011010100010F111ssssssSSSSSS. */
+{ "macwhfm", 0x36A27000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhfm<.f> a,limm,limm 0011011000100010F111111110AAAAAA. */
+{ "macwhfm", 0x36227F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macwhfm<.f> 0,limm,limm 0011011000100010F111111110111110. */
+{ "macwhfm", 0x36227FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhfm<.f><.cc> 0,limm,limm 0011011011100010F1111111100QQQQQ. */
+{ "macwhfm", 0x36E27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhfmr<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA. */
+{ "macwhfmr", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macwhfmr<.f> 0,b,c 00110bbb00100011FBBBCCCCCC111110. */
+{ "macwhfmr", 0x3023003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhfmr<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ. */
+{ "macwhfmr", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhfmr<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA. */
+{ "macwhfmr", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macwhfmr<.f> 0,b,u6 00110bbb01100011FBBBuuuuuu111110. */
+{ "macwhfmr", 0x3063003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhfmr<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ. */
+{ "macwhfmr", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhfmr<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS. */
+{ "macwhfmr", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhfmr<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA. */
+{ "macwhfmr", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macwhfmr<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA. */
+{ "macwhfmr", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macwhfmr<.f> 0,limm,c 0011011001100011F111CCCCCC111110. */
+{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhfmr<.f> 0,b,limm 00110bbb00100011FBBB111110111110. */
+{ "macwhfmr", 0x30230FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhfmr<.f><.cc> b,b,limm 00110bbb11100011FBBB1111100QQQQQ. */
+{ "macwhfmr", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhfmr<.f><.cc> 0,limm,c 0011011011100011F111CCCCCC0QQQQQ. */
+{ "macwhfmr", 0x36E37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhfmr<.f> a,limm,u6 0011011001100011F111uuuuuuAAAAAA. */
+{ "macwhfmr", 0x36637000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhfmr<.f> 0,limm,u6 0011011001100011F111uuuuuu111110. */
+{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhfmr<.f><.cc> 0,limm,u6 0011011011100011F111uuuuuu1QQQQQ. */
+{ "macwhfmr", 0x36E37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhfmr<.f> 0,limm,s12 0011011010100011F111ssssssSSSSSS. */
+{ "macwhfmr", 0x36A37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhfmr<.f> a,limm,limm 0011011000100011F111111110AAAAAA. */
+{ "macwhfmr", 0x36237F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macwhfmr<.f> 0,limm,limm 0011011000100011F111111110111110. */
+{ "macwhfmr", 0x36237FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhfmr<.f><.cc> 0,limm,limm 0011011011100011F1111111100QQQQQ. */
+{ "macwhfmr", 0x36E37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhkl<.f> a,b,c 00110bbb00101000FBBBCCCCCCAAAAAA. */
+{ "macwhkl", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macwhkl<.f> 0,b,c 00110bbb00101000FBBBCCCCCC111110. */
+{ "macwhkl", 0x3028003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhkl<.f><.cc> b,b,c 00110bbb11101000FBBBCCCCCC0QQQQQ. */
+{ "macwhkl", 0x30E80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhkl<.f> a,b,u6 00110bbb01101000FBBBuuuuuuAAAAAA. */
+{ "macwhkl", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macwhkl<.f> 0,b,u6 00110bbb01101000FBBBuuuuuu111110. */
+{ "macwhkl", 0x3068003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhkl<.f><.cc> b,b,u6 00110bbb11101000FBBBuuuuuu1QQQQQ. */
+{ "macwhkl", 0x30E80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhkl<.f> b,b,s12 00110bbb10101000FBBBssssssSSSSSS. */
+{ "macwhkl", 0x30A80000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhkl<.f> a,limm,c 0011011000101000F111CCCCCCAAAAAA. */
+{ "macwhkl", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macwhkl<.f> a,b,limm 00110bbb00101000FBBB111110AAAAAA. */
+{ "macwhkl", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macwhkl<.f> 0,limm,c 0011011001101000F111CCCCCC111110. */
+{ "macwhkl", 0x3668703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhkl<.f> 0,b,limm 00110bbb00101000FBBB111110111110. */
+{ "macwhkl", 0x30280FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhkl<.f><.cc> b,b,limm 00110bbb11101000FBBB1111100QQQQQ. */
+{ "macwhkl", 0x30E80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhkl<.f><.cc> 0,limm,c 0011011011101000F111CCCCCC0QQQQQ. */
+{ "macwhkl", 0x36E87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhkl<.f> a,limm,u6 0011011001101000F111uuuuuuAAAAAA. */
+{ "macwhkl", 0x36687000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhkl<.f> 0,limm,u6 0011011001101000F111uuuuuu111110. */
+{ "macwhkl", 0x3668703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhkl<.f><.cc> 0,limm,u6 0011011011101000F111uuuuuu1QQQQQ. */
+{ "macwhkl", 0x36E87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhkl<.f> 0,limm,s12 0011011010101000F111ssssssSSSSSS. */
+{ "macwhkl", 0x36A87000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhkl<.f> a,limm,limm 0011011000101000F111111110AAAAAA. */
+{ "macwhkl", 0x36287F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macwhkl<.f> 0,limm,limm 0011011000101000F111111110111110. */
+{ "macwhkl", 0x36287FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhkl<.f><.cc> 0,limm,limm 0011011011101000F1111111100QQQQQ. */
+{ "macwhkl", 0x36E87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhkul<.f> a,b,c 00110bbb00101001FBBBCCCCCCAAAAAA. */
+{ "macwhkul", 0x30290000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macwhkul<.f> 0,b,c 00110bbb00101001FBBBCCCCCC111110. */
+{ "macwhkul", 0x3029003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhkul<.f><.cc> b,b,c 00110bbb11101001FBBBCCCCCC0QQQQQ. */
+{ "macwhkul", 0x30E90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhkul<.f> a,b,u6 00110bbb01101001FBBBuuuuuuAAAAAA. */
+{ "macwhkul", 0x30690000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macwhkul<.f> 0,b,u6 00110bbb01101001FBBBuuuuuu111110. */
+{ "macwhkul", 0x3069003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhkul<.f><.cc> b,b,u6 00110bbb11101001FBBBuuuuuu1QQQQQ. */
+{ "macwhkul", 0x30E90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhkul<.f> b,b,s12 00110bbb10101001FBBBssssssSSSSSS. */
+{ "macwhkul", 0x30A90000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhkul<.f> a,limm,c 0011011000101001F111CCCCCCAAAAAA. */
+{ "macwhkul", 0x36297000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macwhkul<.f> a,b,limm 00110bbb00101001FBBB111110AAAAAA. */
+{ "macwhkul", 0x30290F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macwhkul<.f> 0,limm,c 0011011001101001F111CCCCCC111110. */
+{ "macwhkul", 0x3669703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhkul<.f> 0,b,limm 00110bbb00101001FBBB111110111110. */
+{ "macwhkul", 0x30290FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhkul<.f><.cc> b,b,limm 00110bbb11101001FBBB1111100QQQQQ. */
+{ "macwhkul", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhkul<.f><.cc> 0,limm,c 0011011011101001F111CCCCCC0QQQQQ. */
+{ "macwhkul", 0x36E97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhkul<.f> a,limm,u6 0011011001101001F111uuuuuuAAAAAA. */
+{ "macwhkul", 0x36697000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhkul<.f> 0,limm,u6 0011011001101001F111uuuuuu111110. */
+{ "macwhkul", 0x3669703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhkul<.f><.cc> 0,limm,u6 0011011011101001F111uuuuuu1QQQQQ. */
+{ "macwhkul", 0x36E97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhkul<.f> 0,limm,s12 0011011010101001F111ssssssSSSSSS. */
+{ "macwhkul", 0x36A97000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhkul<.f> a,limm,limm 0011011000101001F111111110AAAAAA. */
+{ "macwhkul", 0x36297F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macwhkul<.f> 0,limm,limm 0011011000101001F111111110111110. */
+{ "macwhkul", 0x36297FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhkul<.f><.cc> 0,limm,limm 0011011011101001F1111111100QQQQQ. */
+{ "macwhkul", 0x36E97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhl<.f> a,b,c 00110bbb00011101FBBBCCCCCCAAAAAA. */
+{ "macwhl", 0x301D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macwhl<.f> 0,b,c 00110bbb00011101FBBBCCCCCC111110. */
+{ "macwhl", 0x301D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhl<.f><.cc> b,b,c 00110bbb11011101FBBBCCCCCC0QQQQQ. */
+{ "macwhl", 0x30DD0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhl<.f> a,b,u6 00110bbb01011101FBBBuuuuuuAAAAAA. */
+{ "macwhl", 0x305D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macwhl<.f> 0,b,u6 00110bbb01011101FBBBuuuuuu111110. */
+{ "macwhl", 0x305D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhl<.f><.cc> b,b,u6 00110bbb11011101FBBBuuuuuu1QQQQQ. */
+{ "macwhl", 0x30DD0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhl<.f> b,b,s12 00110bbb10011101FBBBssssssSSSSSS. */
+{ "macwhl", 0x309D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhl<.f> a,limm,c 0011011000011101F111CCCCCCAAAAAA. */
+{ "macwhl", 0x361D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macwhl<.f> a,b,limm 00110bbb00011101FBBB111110AAAAAA. */
+{ "macwhl", 0x301D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macwhl<.f> 0,limm,c 0011011000011101F111CCCCCC111110. */
+{ "macwhl", 0x361D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhl<.f> 0,b,limm 00110bbb00011101FBBB111110111110. */
+{ "macwhl", 0x301D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhl<.f><.cc> b,b,limm 00110bbb11011101FBBB1111100QQQQQ. */
+{ "macwhl", 0x30DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhl<.f><.cc> 0,limm,c 0011011011011101F111CCCCCC0QQQQQ. */
+{ "macwhl", 0x36DD7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhl<.f> a,limm,u6 0011011001011101F111uuuuuuAAAAAA. */
+{ "macwhl", 0x365D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhl<.f> 0,limm,u6 0011011001011101F111uuuuuu111110. */
+{ "macwhl", 0x365D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhl<.f><.cc> 0,limm,u6 0011011011011101F111uuuuuu1QQQQQ. */
+{ "macwhl", 0x36DD7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhl<.f> 0,limm,s12 0011011010011101F111ssssssSSSSSS. */
+{ "macwhl", 0x369D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhl<.f> a,limm,limm 0011011000011101F111111110AAAAAA. */
+{ "macwhl", 0x361D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macwhl<.f> 0,limm,limm 0011011000011101F111111110111110. */
+{ "macwhl", 0x361D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhl<.f><.cc> 0,limm,limm 0011011011011101F1111111100QQQQQ. */
+{ "macwhl", 0x36DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* macwhul<.f> a,b,c 00110bbb00011111FBBBCCCCCCAAAAAA. */
+{ "macwhul", 0x301F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* macwhul<.f> 0,b,c 00110bbb00011111FBBBCCCCCC111110. */
+{ "macwhul", 0x301F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* macwhul<.f><.cc> b,b,c 00110bbb11011111FBBBCCCCCC0QQQQQ. */
+{ "macwhul", 0x30DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* macwhul<.f> a,b,u6 00110bbb01011111FBBBuuuuuuAAAAAA. */
+{ "macwhul", 0x305F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* macwhul<.f> 0,b,u6 00110bbb01011111FBBBuuuuuu111110. */
+{ "macwhul", 0x305F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* macwhul<.f><.cc> b,b,u6 00110bbb11011111FBBBuuuuuu1QQQQQ. */
+{ "macwhul", 0x30DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhul<.f> b,b,s12 00110bbb10011111FBBBssssssSSSSSS. */
+{ "macwhul", 0x309F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* macwhul<.f> a,limm,c 0011011000011111F111CCCCCCAAAAAA. */
+{ "macwhul", 0x361F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* macwhul<.f> a,b,limm 00110bbb00011111FBBB111110AAAAAA. */
+{ "macwhul", 0x301F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* macwhul<.f> 0,limm,c 0011011000011111F111CCCCCC111110. */
+{ "macwhul", 0x361F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* macwhul<.f> 0,b,limm 00110bbb00011111FBBB111110111110. */
+{ "macwhul", 0x301F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* macwhul<.f><.cc> b,b,limm 00110bbb11011111FBBB1111100QQQQQ. */
+{ "macwhul", 0x30DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* macwhul<.f><.cc> 0,limm,c 0011011011011111F111CCCCCC0QQQQQ. */
+{ "macwhul", 0x36DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* macwhul<.f> a,limm,u6 0011011001011111F111uuuuuuAAAAAA. */
+{ "macwhul", 0x365F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhul<.f> 0,limm,u6 0011011001011111F111uuuuuu111110. */
+{ "macwhul", 0x365F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* macwhul<.f><.cc> 0,limm,u6 0011011011011111F111uuuuuu1QQQQQ. */
+{ "macwhul", 0x36DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* macwhul<.f> 0,limm,s12 0011011010011111F111ssssssSSSSSS. */
+{ "macwhul", 0x369F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* macwhul<.f> a,limm,limm 0011011000011111F111111110AAAAAA. */
+{ "macwhul", 0x361F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* macwhul<.f> 0,limm,limm 0011011000011111F111111110111110. */
+{ "macwhul", 0x361F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* macwhul<.f><.cc> 0,limm,limm 0011011011011111F1111111100QQQQQ. */
+{ "macwhul", 0x36DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* max<.f> a,b,c 00100bbb00001000FBBBCCCCCCAAAAAA. */
+{ "max", 0x20080000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* max<.f> 0,b,c 00100bbb00001000FBBBCCCCCC111110. */
+{ "max", 0x2008003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* max<.f><.cc> b,b,c 00100bbb11001000FBBBCCCCCC0QQQQQ. */
+{ "max", 0x20C80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* max<.f> a,b,u6 00100bbb01001000FBBBuuuuuuAAAAAA. */
+{ "max", 0x20480000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* max<.f> 0,b,u6 00100bbb01001000FBBBuuuuuu111110. */
+{ "max", 0x2048003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* max<.f><.cc> b,b,u6 00100bbb11001000FBBBuuuuuu1QQQQQ. */
+{ "max", 0x20C80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* max<.f> b,b,s12 00100bbb10001000FBBBssssssSSSSSS. */
+{ "max", 0x20880000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* max<.f> a,limm,c 0010011000001000F111CCCCCCAAAAAA. */
+{ "max", 0x26087000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* max<.f> a,b,limm 00100bbb00001000FBBB111110AAAAAA. */
+{ "max", 0x20080F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* max<.f> 0,limm,c 0010011000001000F111CCCCCC111110. */
+{ "max", 0x2608703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* max<.f> 0,b,limm 00100bbb00001000FBBB111110111110. */
+{ "max", 0x20080FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* max<.f><.cc> b,b,limm 00100bbb11001000FBBB1111100QQQQQ. */
+{ "max", 0x20C80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* max<.f><.cc> 0,limm,c 0010011011001000F111CCCCCC0QQQQQ. */
+{ "max", 0x26C87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* max<.f> a,limm,u6 0010011001001000F111uuuuuuAAAAAA. */
+{ "max", 0x26487000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* max<.f> 0,limm,u6 0010011001001000F111uuuuuu111110. */
+{ "max", 0x2648703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* max<.f><.cc> 0,limm,u6 0010011011001000F111uuuuuu1QQQQQ. */
+{ "max", 0x26C87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* max<.f> 0,limm,s12 0010011010001000F111ssssssSSSSSS. */
+{ "max", 0x26887000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* max<.f> a,limm,limm 0010011000001000F111111110AAAAAA. */
+{ "max", 0x26087F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* max<.f> 0,limm,limm 0010011000001000F111111110111110. */
+{ "max", 0x26087FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* max<.f><.cc> 0,limm,limm 0010011011001000F1111111100QQQQQ. */
+{ "max", 0x26C87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* maxl<.f> RA,RB,RC 01011bbb00001000FBBBccccccaaaaaa. */
+{ "maxl", 0x58080000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* maxl<.f> 0,RB,RC 01011bbb00001000FBBBcccccc111110. */
+{ "maxl", 0x5808003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* maxl<.f><.cc> RB,RB,RC 01011bbb11001000FBBBcccccc0QQQQQ. */
+{ "maxl", 0x58C80000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* maxl<.f> RA,RB,u6 01011bbb01001000FBBBuuuuuuaaaaaa. */
+{ "maxl", 0x58480000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* maxl<.f> 0,RB,u6 01011bbb01001000FBBBuuuuuu111110. */
+{ "maxl", 0x5848003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* maxl<.f><.cc> RB,RB,u6 01011bbb11001000FBBBuuuuuu1QQQQQ. */
+{ "maxl", 0x58C80020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* maxl<.f> RB,RB,s12 01011bbb10001000FBBBssssssSSSSSS. */
+{ "maxl", 0x58880000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* maxl<.f> RA,ximm,RC 0101110000001000F111ccccccaaaaaa. */
+{ "maxl", 0x5C087000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* maxl<.f> RA,RB,ximm 01011bbb00001000FBBB111100aaaaaa. */
+{ "maxl", 0x58080F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* maxl<.f> 0,ximm,RC 0101110000001000F111cccccc111110. */
+{ "maxl", 0x5C08703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* maxl<.f> 0,RB,ximm 01011bbb00001000FBBB111100111110. */
+{ "maxl", 0x58080F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* maxl<.f><.cc> 0,ximm,RC 0101110011001000F111cccccc0QQQQQ. */
+{ "maxl", 0x5CC87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* maxl<.f><.cc> RB,RB,ximm 01011bbb11001000FBBB1111000QQQQQ. */
+{ "maxl", 0x58C80F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* maxl<.f> RA,ximm,u6 0101110001001000F111uuuuuuaaaaaa. */
+{ "maxl", 0x5C487000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* maxl<.f> 0,ximm,u6 0101110001001000F111uuuuuu111110. */
+{ "maxl", 0x5C48703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* maxl<.f><.cc> 0,ximm,u6 0101110011001000F111uuuuuu1QQQQQ. */
+{ "maxl", 0x5CC87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* maxl<.f> RA,limm,RC 0101111000001000F111ccccccaaaaaa. */
+{ "maxl", 0x5E087000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* maxl<.f> RA,RB,limm 01011bbb00001000FBBB111110aaaaaa. */
+{ "maxl", 0x58080F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* maxl<.f> 0,limm,RC 0101111000001000F111cccccc111110. */
+{ "maxl", 0x5E08703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* maxl<.f> 0,RB,limm 01011bbb00001000FBBB111110111110. */
+{ "maxl", 0x58080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* maxl<.f><.cc> 0,limm,RC 0101111011001000F111cccccc0QQQQQ. */
+{ "maxl", 0x5EC87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* maxl<.f><.cc> RB,RB,limm 01011bbb11001000FBBB1111100QQQQQ. */
+{ "maxl", 0x58C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* maxl<.f> RA,limm,u6 0101111001001000F111uuuuuuaaaaaa. */
+{ "maxl", 0x5E487000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* maxl<.f> 0,limm,u6 0101111001001000F111uuuuuu111110. */
+{ "maxl", 0x5E48703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* maxl<.f><.cc> 0,limm,u6 0101111011001000F111uuuuuu1QQQQQ. */
+{ "maxl", 0x5EC87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* maxl<.f> 0,ximm,s12 0101110010001000F111ssssssSSSSSS. */
+{ "maxl", 0x5C887000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* maxl<.f> 0,limm,s12 0101111010001000F111ssssssSSSSSS. */
+{ "maxl", 0x5E887000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* maxl<.f> RA,ximm,ximm 0101110000001000F111111100aaaaaa. */
+{ "maxl", 0x5C087F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* maxl<.f> 0,ximm,ximm 0101110000001000F111111100111110. */
+{ "maxl", 0x5C087F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* maxl<.f><.cc> 0,ximm,ximm 0101110011001000F1111111000QQQQQ. */
+{ "maxl", 0x5CC87F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* maxl<.f> RA,limm,limm 0101111000001000F111111110aaaaaa. */
+{ "maxl", 0x5E087F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* maxl<.f> 0,limm,limm 0101111000001000F111111110111110. */
+{ "maxl", 0x5E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* maxl<.f><.cc> 0,limm,limm 0101111011001000F1111111100QQQQQ. */
+{ "maxl", 0x5EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* min<.f> a,b,c 00100bbb00001001FBBBCCCCCCAAAAAA. */
+{ "min", 0x20090000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* min<.f> 0,b,c 00100bbb00001001FBBBCCCCCC111110. */
+{ "min", 0x2009003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* min<.f><.cc> b,b,c 00100bbb11001001FBBBCCCCCC0QQQQQ. */
+{ "min", 0x20C90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* min<.f> a,b,u6 00100bbb01001001FBBBuuuuuuAAAAAA. */
+{ "min", 0x20490000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* min<.f> 0,b,u6 00100bbb01001001FBBBuuuuuu111110. */
+{ "min", 0x2049003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* min<.f><.cc> b,b,u6 00100bbb11001001FBBBuuuuuu1QQQQQ. */
+{ "min", 0x20C90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* min<.f> b,b,s12 00100bbb10001001FBBBssssssSSSSSS. */
+{ "min", 0x20890000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* min<.f> a,limm,c 0010011000001001F111CCCCCCAAAAAA. */
+{ "min", 0x26097000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* min<.f> a,b,limm 00100bbb00001001FBBB111110AAAAAA. */
+{ "min", 0x20090F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* min<.f> 0,limm,c 0010011000001001F111CCCCCC111110. */
+{ "min", 0x2609703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* min<.f> 0,b,limm 00100bbb00001001FBBB111110111110. */
+{ "min", 0x20090FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* min<.f><.cc> b,b,limm 00100bbb11001001FBBB1111100QQQQQ. */
+{ "min", 0x20C90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* min<.f><.cc> 0,limm,c 0010011011001001F111CCCCCC0QQQQQ. */
+{ "min", 0x26C97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* min<.f> a,limm,u6 0010011001001001F111uuuuuuAAAAAA. */
+{ "min", 0x26497000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* min<.f> 0,limm,u6 0010011001001001F111uuuuuu111110. */
+{ "min", 0x2649703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* min<.f><.cc> 0,limm,u6 0010011011001001F111uuuuuu1QQQQQ. */
+{ "min", 0x26C97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* min<.f> 0,limm,s12 0010011010001001F111ssssssSSSSSS. */
+{ "min", 0x26897000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* min<.f> a,limm,limm 0010011000001001F111111110AAAAAA. */
+{ "min", 0x26097F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* min<.f> 0,limm,limm 0010011000001001F111111110111110. */
+{ "min", 0x26097FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* min<.f><.cc> 0,limm,limm 0010011011001001F1111111100QQQQQ. */
+{ "min", 0x26C97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* minl<.f> RA,RB,RC 01011bbb00001001FBBBccccccaaaaaa. */
+{ "minl", 0x58090000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* minl<.f> 0,RB,RC 01011bbb00001001FBBBcccccc111110. */
+{ "minl", 0x5809003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* minl<.f><.cc> RB,RB,RC 01011bbb11001001FBBBcccccc0QQQQQ. */
+{ "minl", 0x58C90000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* minl<.f> RA,RB,u6 01011bbb01001001FBBBuuuuuuaaaaaa. */
+{ "minl", 0x58490000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* minl<.f> 0,RB,u6 01011bbb01001001FBBBuuuuuu111110. */
+{ "minl", 0x5849003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* minl<.f><.cc> RB,RB,u6 01011bbb11001001FBBBuuuuuu1QQQQQ. */
+{ "minl", 0x58C90020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* minl<.f> RB,RB,s12 01011bbb10001001FBBBssssssSSSSSS. */
+{ "minl", 0x58890000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* minl<.f> RA,ximm,RC 0101110000001001F111ccccccaaaaaa. */
+{ "minl", 0x5C097000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* minl<.f> RA,RB,ximm 01011bbb00001001FBBB111100aaaaaa. */
+{ "minl", 0x58090F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* minl<.f> 0,ximm,RC 0101110000001001F111cccccc111110. */
+{ "minl", 0x5C09703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* minl<.f> 0,RB,ximm 01011bbb00001001FBBB111100111110. */
+{ "minl", 0x58090F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* minl<.f><.cc> 0,ximm,RC 0101110011001001F111cccccc0QQQQQ. */
+{ "minl", 0x5CC97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* minl<.f><.cc> RB,RB,ximm 01011bbb11001001FBBB1111000QQQQQ. */
+{ "minl", 0x58C90F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* minl<.f> RA,ximm,u6 0101110001001001F111uuuuuuaaaaaa. */
+{ "minl", 0x5C497000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* minl<.f> 0,ximm,u6 0101110001001001F111uuuuuu111110. */
+{ "minl", 0x5C49703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* minl<.f><.cc> 0,ximm,u6 0101110011001001F111uuuuuu1QQQQQ. */
+{ "minl", 0x5CC97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* minl<.f> RA,limm,RC 0101111000001001F111ccccccaaaaaa. */
+{ "minl", 0x5E097000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* minl<.f> RA,RB,limm 01011bbb00001001FBBB111110aaaaaa. */
+{ "minl", 0x58090F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* minl<.f> 0,limm,RC 0101111000001001F111cccccc111110. */
+{ "minl", 0x5E09703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* minl<.f> 0,RB,limm 01011bbb00001001FBBB111110111110. */
+{ "minl", 0x58090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* minl<.f><.cc> 0,limm,RC 0101111011001001F111cccccc0QQQQQ. */
+{ "minl", 0x5EC97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* minl<.f><.cc> RB,RB,limm 01011bbb11001001FBBB1111100QQQQQ. */
+{ "minl", 0x58C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* minl<.f> RA,limm,u6 0101111001001001F111uuuuuuaaaaaa. */
+{ "minl", 0x5E497000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* minl<.f> 0,limm,u6 0101111001001001F111uuuuuu111110. */
+{ "minl", 0x5E49703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* minl<.f><.cc> 0,limm,u6 0101111011001001F111uuuuuu1QQQQQ. */
+{ "minl", 0x5EC97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* minl<.f> 0,ximm,s12 0101110010001001F111ssssssSSSSSS. */
+{ "minl", 0x5C897000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* minl<.f> 0,limm,s12 0101111010001001F111ssssssSSSSSS. */
+{ "minl", 0x5E897000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* minl<.f> RA,ximm,ximm 0101110000001001F111111100aaaaaa. */
+{ "minl", 0x5C097F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* minl<.f> 0,ximm,ximm 0101110000001001F111111100111110. */
+{ "minl", 0x5C097F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* minl<.f><.cc> 0,ximm,ximm 0101110011001001F1111111000QQQQQ. */
+{ "minl", 0x5CC97F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* minl<.f> RA,limm,limm 0101111000001001F111111110aaaaaa. */
+{ "minl", 0x5E097F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* minl<.f> 0,limm,limm 0101111000001001F111111110111110. */
+{ "minl", 0x5E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* minl<.f><.cc> 0,limm,limm 0101111011001001F1111111100QQQQQ. */
+{ "minl", 0x5EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* nop 00100110010010100111000000000000. */
+{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR. */
+{ "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RB, RC }, { C_F }},
+
+/* mov<.f> 0,c 0010011000001010F111CCCCCCRRRRRR. */
+{ "mov", 0x260A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RC }, { C_F }},
+
+/* mov<.f><.cc> b,c 00100bbb11001010FBBBCCCCCC0QQQQQ. */
+{ "mov", 0x20CA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RB, RC }, { C_F, C_CC }},
+
+/* mov<.f><.cc> 0,c 0010011011001010F111CCCCCC0QQQQQ. */
+{ "mov", 0x26CA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RC }, { C_F, C_CC }},
+
+/* mov<.f> b,u6 00100bbb01001010FBBBuuuuuuRRRRRR. */
+{ "mov", 0x204A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* mov<.f> 0,u6 0010011001001010F111uuuuuuRRRRRR. */
+{ "mov", 0x264A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
+{ "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RB, UIMM6_20 }, { C_F, C_CC }},
+
+/* mov<.f><.cc> 0,u6 0010011011001010F111uuuuuu1QQQQQ. */
+{ "mov", 0x26CA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, UIMM6_20 }, { C_F, C_CC }},
+
+/* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
+{ "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RB, SIMM12_20 }, { C_F }},
+
+/* mov<.f> 0,s12 0010011010001010F111ssssssSSSSSS. */
+{ "mov", 0x268A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, SIMM12_20 }, { C_F }},
+
+/* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
+{ "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RB, LIMM }, { C_F }},
+
+/* mov<.f> 0,limm 0010011000001010F111111110RRRRRR. */
+{ "mov", 0x260A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM }, { C_F }},
+
+/* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
+{ "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RB, LIMM }, { C_F, C_CC }},
+
+/* mov<.f><.cc> 0,limm 0010011011001010F1111111100QQQQQ. */
+{ "mov", 0x26CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM }, { C_F, C_CC }},
+
+/* movhl RB,RC 01011bbb000010110BBBccccccRRRRRR. */
+{ "movhl", 0x580B0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* movhl<.cc> RB,RC 01011bbb110010110BBBcccccc0QQQQQ. */
+{ "movhl", 0x58CB0000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* movhl RB,u6 01011bbb010010110BBBuuuuuuRRRRRR. */
+{ "movhl", 0x584B0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* movhl<.cc> RB,u6 01011bbb110010110BBBuuuuuu1QQQQQ. */
+{ "movhl", 0x58CB0020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* movhl RB,s12 01011bbb100010110BBBssssssSSSSSS. */
+{ "movhl", 0x588B0000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* movhl RB,limm 01011bbb000010110BBB111110RRRRRR. */
+{ "movhl", 0x580B0F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, HI32 }, { 0 }},
+
+/* movhl<.cc> RB,limm 01011bbb110010110BBB1111100QQQQQ. */
+{ "movhl", 0x58CB0F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, HI32 }, { C_CC }},
+
+/* movhl_s h,limm 01110000hhh010HH. */
+{ "movhl_s", 0x00007008, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, HI32 }, { 0 }},
+
+/* movl<.f> RB,RC 01011bbb00001010FBBBccccccRRRRRR. */
+{ "movl", 0x580A0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* movl<.f><.cc> RB,RC 01011bbb11001010FBBBcccccc0QQQQQ. */
+{ "movl", 0x58CA0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F, C_CC }},
+
+/* movl<.f> RB,u6 01011bbb01001010FBBBuuuuuuRRRRRR. */
+{ "movl", 0x584A0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* movl<.f><.cc> RB,u6 01011bbb11001010FBBBuuuuuu1QQQQQ. */
+{ "movl", 0x58CA0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F, C_CC }},
+
+/* movl<.f> RB,s12 01011bbb10001010FBBBssssssSSSSSS. */
+{ "movl", 0x588A0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { C_F }},
+
+/* movl<.f> RB,ximm 01011bbb00001010FBBB111100RRRRRR. */
+{ "movl", 0x580A0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* movl<.f><.cc> RB,ximm 01011bbb11001010FBBB1111000QQQQQ. */
+{ "movl", 0x58CA0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F, C_CC }},
+
+/* movl<.f> RB,limm 01011bbb00001010FBBB111110RRRRRR. */
+{ "movl", 0x580A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* movl<.f><.cc> RB,limm 01011bbb11001010FBBB1111100QQQQQ. */
+{ "movl", 0x58CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F, C_CC }},
+
+/* movl_s g,h 01000ggghhhGG1HH. */
+{ "movl_s", 0x00004004, 0x0000F804, ARC_OPCODE_ARC64, ARITH, NONE, { G_S, RH_S }, { 0 }},
+
+/* movl_s b,u8 11011bbbuuuuuuuu. */
+{ "movl_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, UIMM8_8_S }, { 0 }},
+
+/* movl_s g,limm 01000ggg110GG111. */
+{ "movl_s", 0x000040C7, 0x0000F8E7, ARC_OPCODE_ARC64, MOVE, NONE, { G_S, LIMM_S }, { 0 }},
+
+/* mov_s.NE b,h 01110bbbhhh111HH. */
+{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RB_S, RH_S }, { C_NE, C_CC_NE}},
+
+/* mov_s g,h 01000ggghhhGG0HH. */
+{ "mov_s", 0x00004000, 0x0000F804, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { G_S, RH_S }, { 0 }},
+
+/* mov_s 0,h 01000110hhh110HH. */
+{ "mov_s", 0x00004618, 0x0000FF1C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { ZA_S, RH_S }, { 0 }},
+
+/* mov_s h,s3 01110ssshhh011HH. */
+{ "mov_s", 0x0000700C, 0x0000F81C, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RH_S, SIMM3_5_S }, { 0 }},
+
+/* mov_s 0,s3 01110sss11001111. */
+{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { ZA_S, SIMM3_5_S }, { 0 }},
+
+/* mov_s b,u8 11011bbbuuuuuuuu. */
+{ "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RB_S, UIMM8_8_S }, { 0 }},
+
+/* mov_s.NE b,limm 01110bbb11011111. */
+{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { RB_S, LIMM_S }, { C_NE, C_CC_NE}},
+
+/* mov_s g,limm 01000ggg110GG011. */
+{ "mov_s", 0x000040C3, 0x0000F8E7, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { G_S, LIMM_S }, { 0 }},
+
+/* mov_s 0,limm 0100011011011011. */
+{ "mov_s", 0x000046DB, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MOVE, NONE, { ZA_S, LIMM_S }, { 0 }},
+
+/* mpy<.f> a,b,c 00100bbb00011010FBBBCCCCCCAAAAAA. */
+{ "mpy", 0x201A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpy<.f> 0,b,c 00100bbb00011010FBBBCCCCCC111110. */
+{ "mpy", 0x201A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpy<.f><.cc> b,b,c 00100bbb11011010FBBBCCCCCC0QQQQQ. */
+{ "mpy", 0x20DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
+{ "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpy<.f> 0,b,u6 00100bbb01011010FBBBuuuuuu111110. */
+{ "mpy", 0x205A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpy<.f><.cc> b,b,u6 00100bbb11011010FBBBuuuuuu1QQQQQ. */
+{ "mpy", 0x20DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpy<.f> b,b,s12 00100bbb10011010FBBBssssssSSSSSS. */
+{ "mpy", 0x209A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpy<.f> a,limm,c 0010011000011010F111CCCCCCAAAAAA. */
+{ "mpy", 0x261A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
+{ "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpy<.f> 0,limm,c 0010011000011010F111CCCCCC111110. */
+{ "mpy", 0x261A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpy<.f> 0,b,limm 00100bbb00011010FBBB111110111110. */
+{ "mpy", 0x201A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpy<.f><.cc> b,b,limm 00100bbb11011010FBBB1111100QQQQQ. */
+{ "mpy", 0x20DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpy<.f><.cc> 0,limm,c 0010011011011010F111CCCCCC0QQQQQ. */
+{ "mpy", 0x26DA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpy<.f> a,limm,u6 0010011001011010F111uuuuuuAAAAAA. */
+{ "mpy", 0x265A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpy<.f> 0,limm,u6 0010011001011010F111uuuuuu111110. */
+{ "mpy", 0x265A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpy<.f><.cc> 0,limm,u6 0010011011011010F111uuuuuu1QQQQQ. */
+{ "mpy", 0x26DA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpy<.f> 0,limm,s12 0010011010011010F111ssssssSSSSSS. */
+{ "mpy", 0x269A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpy<.f> a,limm,limm 0010011000011010F111111110AAAAAA. */
+{ "mpy", 0x261A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpy<.f> 0,limm,limm 0010011000011010F111111110111110. */
+{ "mpy", 0x261A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpy<.f><.cc> 0,limm,limm 0010011011011010F1111111100QQQQQ. */
+{ "mpy", 0x26DA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyd<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA. */
+{ "mpyd", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpyd<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110. */
+{ "mpyd", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* mpyd<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ. */
+{ "mpyd", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyd<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA. */
+{ "mpyd", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110. */
+{ "mpyd", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ. */
+{ "mpyd", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyd<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS. */
+{ "mpyd", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyd<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA. */
+{ "mpyd", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpyd<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA. */
+{ "mpyd", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpyd<.f> 0,limm,c 0010111000011000F111CCCCCC111110. */
+{ "mpyd", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyd<.f> 0,b,limm 00101bbb00011000FBBB111110111110. */
+{ "mpyd", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyd<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ. */
+{ "mpyd", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyd<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ. */
+{ "mpyd", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyd<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA. */
+{ "mpyd", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f> 0,limm,u6 0010111001011000F111uuuuuu111110. */
+{ "mpyd", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyd<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ. */
+{ "mpyd", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyd<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS. */
+{ "mpyd", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyd<.f> a,limm,limm 0010111000011000F111111110AAAAAA. */
+{ "mpyd", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpyd<.f> 0,limm,limm 0010111000011000F111111110111110. */
+{ "mpyd", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyd<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ. */
+{ "mpyd", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpydf<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA. */
+{ "mpydf", 0x30120000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpydf<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110. */
+{ "mpydf", 0x3012003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpydf<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ. */
+{ "mpydf", 0x30D20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpydf<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA. */
+{ "mpydf", 0x30520000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110. */
+{ "mpydf", 0x3052003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ. */
+{ "mpydf", 0x30D20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydf<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS. */
+{ "mpydf", 0x30920000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpydf<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA. */
+{ "mpydf", 0x36127000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpydf<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA. */
+{ "mpydf", 0x30120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpydf<.f> 0,limm,c 0011011000010010F111CCCCCC111110. */
+{ "mpydf", 0x3612703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpydf<.f> 0,b,limm 00110bbb00010010FBBB111110111110. */
+{ "mpydf", 0x30120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpydf<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ. */
+{ "mpydf", 0x30D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpydf<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ. */
+{ "mpydf", 0x36D27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpydf<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA. */
+{ "mpydf", 0x36527000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f> 0,limm,u6 0011011001010010F111uuuuuu111110. */
+{ "mpydf", 0x3652703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydf<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ. */
+{ "mpydf", 0x36D27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydf<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS. */
+{ "mpydf", 0x36927000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpydf<.f> a,limm,limm 0011011000010010F111111110AAAAAA. */
+{ "mpydf", 0x36127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpydf<.f> 0,limm,limm 0011011000010010F111111110111110. */
+{ "mpydf", 0x36127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpydf<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ. */
+{ "mpydf", 0x36D27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpydu<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA. */
+{ "mpydu", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpydu<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110. */
+{ "mpydu", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { C_F }},
+
+/* mpydu<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ. */
+{ "mpydu", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpydu<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA. */
+{ "mpydu", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110. */
+{ "mpydu", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ. */
+{ "mpydu", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydu<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS. */
+{ "mpydu", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpydu<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA. */
+{ "mpydu", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpydu<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA. */
+{ "mpydu", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpydu<.f> 0,limm,c 0010111000011001F111CCCCCC111110. */
+{ "mpydu", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpydu<.f> 0,b,limm 00101bbb00011001FBBB111110111110. */
+{ "mpydu", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpydu<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ. */
+{ "mpydu", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpydu<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ. */
+{ "mpydu", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpydu<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA. */
+{ "mpydu", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f> 0,limm,u6 0010111001011001F111uuuuuu111110. */
+{ "mpydu", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpydu<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ. */
+{ "mpydu", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpydu<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS. */
+{ "mpydu", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpydu<.f> a,limm,limm 0010111000011001F111111110AAAAAA. */
+{ "mpydu", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpydu<.f> 0,limm,limm 0010111000011001F111111110111110. */
+{ "mpydu", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpydu<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ. */
+{ "mpydu", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyf<.f> a,b,c 00110bbb00001010FBBBCCCCCCAAAAAA. */
+{ "mpyf", 0x300A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpyf<.f> 0,b,c 00110bbb00001010FBBBCCCCCC111110. */
+{ "mpyf", 0x300A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpyf<.f><.cc> b,b,c 00110bbb11001010FBBBCCCCCC0QQQQQ. */
+{ "mpyf", 0x30CA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyf<.f> a,b,u6 00110bbb01001010FBBBuuuuuuAAAAAA. */
+{ "mpyf", 0x304A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpyf<.f> 0,b,u6 00110bbb01001010FBBBuuuuuu111110. */
+{ "mpyf", 0x304A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyf<.f><.cc> b,b,u6 00110bbb11001010FBBBuuuuuu1QQQQQ. */
+{ "mpyf", 0x30CA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyf<.f> b,b,s12 00110bbb10001010FBBBssssssSSSSSS. */
+{ "mpyf", 0x308A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyf<.f> a,limm,c 0011011000001010F111CCCCCCAAAAAA. */
+{ "mpyf", 0x360A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpyf<.f> a,b,limm 00110bbb00001010FBBB111110AAAAAA. */
+{ "mpyf", 0x300A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpyf<.f> 0,limm,c 0011011000001010F111CCCCCC111110. */
+{ "mpyf", 0x360A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyf<.f> 0,b,limm 00110bbb00001010FBBB111110111110. */
+{ "mpyf", 0x300A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyf<.f><.cc> b,b,limm 00110bbb11001010FBBB1111100QQQQQ. */
+{ "mpyf", 0x30CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyf<.f><.cc> 0,limm,c 0011011011001010F111CCCCCC0QQQQQ. */
+{ "mpyf", 0x36CA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyf<.f> a,limm,u6 0011011001001010F111uuuuuuAAAAAA. */
+{ "mpyf", 0x364A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyf<.f> 0,limm,u6 0011011001001010F111uuuuuu111110. */
+{ "mpyf", 0x364A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyf<.f><.cc> 0,limm,u6 0011011011001010F111uuuuuu1QQQQQ. */
+{ "mpyf", 0x36CA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyf<.f> 0,limm,s12 0011011010001010F111ssssssSSSSSS. */
+{ "mpyf", 0x368A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyf<.f> a,limm,limm 0011011000001010F111111110AAAAAA. */
+{ "mpyf", 0x360A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpyf<.f> 0,limm,limm 0011011000001010F111111110111110. */
+{ "mpyf", 0x360A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyf<.f><.cc> 0,limm,limm 0011011011001010F1111111100QQQQQ. */
+{ "mpyf", 0x36CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyfr<.f> a,b,c 00110bbb00001011FBBBCCCCCCAAAAAA. */
+{ "mpyfr", 0x300B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpyfr<.f> 0,b,c 00110bbb00001011FBBBCCCCCC111110. */
+{ "mpyfr", 0x300B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpyfr<.f><.cc> b,b,c 00110bbb11001011FBBBCCCCCC0QQQQQ. */
+{ "mpyfr", 0x30CB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyfr<.f> a,b,u6 00110bbb01001011FBBBuuuuuuAAAAAA. */
+{ "mpyfr", 0x304B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpyfr<.f> 0,b,u6 00110bbb01001011FBBBuuuuuu111110. */
+{ "mpyfr", 0x304B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyfr<.f><.cc> b,b,u6 00110bbb11001011FBBBuuuuuu1QQQQQ. */
+{ "mpyfr", 0x30CB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyfr<.f> b,b,s12 00110bbb10001011FBBBssssssSSSSSS. */
+{ "mpyfr", 0x308B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyfr<.f> a,limm,c 0011011000001011F111CCCCCCAAAAAA. */
+{ "mpyfr", 0x360B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpyfr<.f> a,b,limm 00110bbb00001011FBBB111110AAAAAA. */
+{ "mpyfr", 0x300B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpyfr<.f> 0,limm,c 0011011000001011F111CCCCCC111110. */
+{ "mpyfr", 0x360B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyfr<.f> 0,b,limm 00110bbb00001011FBBB111110111110. */
+{ "mpyfr", 0x300B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyfr<.f><.cc> b,b,limm 00110bbb11001011FBBB1111100QQQQQ. */
+{ "mpyfr", 0x30CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyfr<.f><.cc> 0,limm,c 0011011011001011F111CCCCCC0QQQQQ. */
+{ "mpyfr", 0x36CB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyfr<.f> a,limm,u6 0011011001001011F111uuuuuuAAAAAA. */
+{ "mpyfr", 0x364B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyfr<.f> 0,limm,u6 0011011001001011F111uuuuuu111110. */
+{ "mpyfr", 0x364B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyfr<.f><.cc> 0,limm,u6 0011011011001011F111uuuuuu1QQQQQ. */
+{ "mpyfr", 0x36CB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyfr<.f> 0,limm,s12 0011011010001011F111ssssssSSSSSS. */
+{ "mpyfr", 0x368B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyfr<.f> a,limm,limm 0011011000001011F111111110AAAAAA. */
+{ "mpyfr", 0x360B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpyfr<.f> 0,limm,limm 0011011000001011F111111110111110. */
+{ "mpyfr", 0x360B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyfr<.f><.cc> 0,limm,limm 0011011011001011F1111111100QQQQQ. */
+{ "mpyfr", 0x36CB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyl<.f> RA,RB,RC 01011bbb00110000FBBBccccccaaaaaa. */
+{ "mpyl", 0x58300000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* mpyl<.f> 0,RB,RC 01011bbb00110000FBBBcccccc111110. */
+{ "mpyl", 0x5830003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpyl<.f><.cc> RB,RB,RC 01011bbb11110000FBBBcccccc0QQQQQ. */
+{ "mpyl", 0x58F00000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyl<.f> RA,RB,u6 01011bbb01110000FBBBuuuuuuaaaaaa. */
+{ "mpyl", 0x58700000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyl<.f> 0,RB,u6 01011bbb01110000FBBBuuuuuu111110. */
+{ "mpyl", 0x5870003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyl<.f><.cc> RB,RB,u6 01011bbb11110000FBBBuuuuuu1QQQQQ. */
+{ "mpyl", 0x58F00020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyl<.f> RB,RB,s12 01011bbb10110000FBBBssssssSSSSSS. */
+{ "mpyl", 0x58B00000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyl<.f> RA,ximm,RC 0101110000110000F111ccccccaaaaaa. */
+{ "mpyl", 0x5C307000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* mpyl<.f> RA,RB,ximm 01011bbb00110000FBBB111100aaaaaa. */
+{ "mpyl", 0x58300F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* mpyl<.f> 0,ximm,RC 0101110000110000F111cccccc111110. */
+{ "mpyl", 0x5C30703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* mpyl<.f> 0,RB,ximm 01011bbb00110000FBBB111100111110. */
+{ "mpyl", 0x58300F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* mpyl<.f><.cc> 0,ximm,RC 0101110011110000F111cccccc0QQQQQ. */
+{ "mpyl", 0x5CF07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* mpyl<.f><.cc> RB,RB,ximm 01011bbb11110000FBBB1111000QQQQQ. */
+{ "mpyl", 0x58F00F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* mpyl<.f> RA,ximm,u6 0101110001110000F111uuuuuuaaaaaa. */
+{ "mpyl", 0x5C707000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* mpyl<.f> 0,ximm,u6 0101110001110000F111uuuuuu111110. */
+{ "mpyl", 0x5C70703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* mpyl<.f><.cc> 0,ximm,u6 0101110011110000F111uuuuuu1QQQQQ. */
+{ "mpyl", 0x5CF07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyl<.f> RA,limm,RC 0101111000110000F111ccccccaaaaaa. */
+{ "mpyl", 0x5E307000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* mpyl<.f> RA,RB,limm 01011bbb00110000FBBB111110aaaaaa. */
+{ "mpyl", 0x58300F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* mpyl<.f> 0,limm,RC 0101111000110000F111cccccc111110. */
+{ "mpyl", 0x5E30703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyl<.f> 0,RB,limm 01011bbb00110000FBBB111110111110. */
+{ "mpyl", 0x58300FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyl<.f><.cc> 0,limm,RC 0101111011110000F111cccccc0QQQQQ. */
+{ "mpyl", 0x5EF07000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyl<.f><.cc> RB,RB,limm 01011bbb11110000FBBB1111100QQQQQ. */
+{ "mpyl", 0x58F00F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyl<.f> RA,limm,u6 0101111001110000F111uuuuuuaaaaaa. */
+{ "mpyl", 0x5E707000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyl<.f> 0,limm,u6 0101111001110000F111uuuuuu111110. */
+{ "mpyl", 0x5E70703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyl<.f><.cc> 0,limm,u6 0101111011110000F111uuuuuu1QQQQQ. */
+{ "mpyl", 0x5EF07020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyl<.f> 0,ximm,s12 0101110010110000F111ssssssSSSSSS. */
+{ "mpyl", 0x5CB07000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* mpyl<.f> 0,limm,s12 0101111010110000F111ssssssSSSSSS. */
+{ "mpyl", 0x5EB07000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyl<.f> RA,ximm,ximm 0101110000110000F111111100aaaaaa. */
+{ "mpyl", 0x5C307F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* mpyl<.f> 0,ximm,ximm 0101110000110000F111111100111110. */
+{ "mpyl", 0x5C307F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* mpyl<.f><.cc> 0,ximm,ximm 0101110011110000F1111111000QQQQQ. */
+{ "mpyl", 0x5CF07F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* mpyl<.f> RA,limm,limm 0101111000110000F111111110aaaaaa. */
+{ "mpyl", 0x5E307F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyl<.f> 0,limm,limm 0101111000110000F111111110111110. */
+{ "mpyl", 0x5E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyl<.f><.cc> 0,limm,limm 0101111011110000F1111111100QQQQQ. */
+{ "mpyl", 0x5EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpym<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA. */
+{ "mpym", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpym<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110. */
+{ "mpym", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpym<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ. */
+{ "mpym", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpym<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA. */
+{ "mpym", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpym<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110. */
+{ "mpym", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpym<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ. */
+{ "mpym", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpym<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS. */
+{ "mpym", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpym<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA. */
+{ "mpym", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpym<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA. */
+{ "mpym", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpym<.f> 0,limm,c 0010011000011011F111CCCCCC111110. */
+{ "mpym", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpym<.f> 0,b,limm 00100bbb00011011FBBB111110111110. */
+{ "mpym", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpym<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ. */
+{ "mpym", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpym<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ. */
+{ "mpym", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpym<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA. */
+{ "mpym", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpym<.f> 0,limm,u6 0010011001011011F111uuuuuu111110. */
+{ "mpym", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpym<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ. */
+{ "mpym", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpym<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS. */
+{ "mpym", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpym<.f> a,limm,limm 0010011000011011F111111110AAAAAA. */
+{ "mpym", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpym<.f> 0,limm,limm 0010011000011011F111111110111110. */
+{ "mpym", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpym<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ. */
+{ "mpym", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyml RA,RB,RC 01011bbb001100010BBBccccccaaaaaa. */
+{ "mpyml", 0x58310000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { 0 }},
+
+/* mpyml 0,RB,RC 01011bbb001100010BBBcccccc111110. */
+{ "mpyml", 0x5831003E, 0xF8FF803F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* mpyml<.cc> RB,RB,RC 01011bbb111100010BBBcccccc0QQQQQ. */
+{ "mpyml", 0x58F10000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* mpyml RA,RB,u6 01011bbb011100010BBBuuuuuuaaaaaa. */
+{ "mpyml", 0x58710000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* mpyml 0,RB,u6 01011bbb011100010BBBuuuuuu111110. */
+{ "mpyml", 0x5871003E, 0xF8FF803F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* mpyml<.cc> RB,RB,u6 01011bbb111100010BBBuuuuuu1QQQQQ. */
+{ "mpyml", 0x58F10020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* mpyml RB,RB,s12 01011bbb101100010BBBssssssSSSSSS. */
+{ "mpyml", 0x58B10000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* mpyml RA,ximm,RC 01011100001100010111ccccccaaaaaa. */
+{ "mpyml", 0x5C317000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { 0 }},
+
+/* mpyml RA,RB,ximm 01011bbb001100010BBB111100aaaaaa. */
+{ "mpyml", 0x58310F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { 0 }},
+
+/* mpyml 0,ximm,RC 01011100001100010111cccccc111110. */
+{ "mpyml", 0x5C31703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { 0 }},
+
+/* mpyml 0,RB,ximm 01011bbb001100010BBB111100111110. */
+{ "mpyml", 0x58310F3E, 0xF8FF8FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { 0 }},
+
+/* mpyml<.cc> 0,ximm,RC 01011100111100010111cccccc0QQQQQ. */
+{ "mpyml", 0x5CF17000, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_CC }},
+
+/* mpyml<.cc> RB,RB,ximm 01011bbb111100010BBB1111000QQQQQ. */
+{ "mpyml", 0x58F10F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_CC }},
+
+/* mpyml RA,ximm,u6 01011100011100010111uuuuuuaaaaaa. */
+{ "mpyml", 0x5C717000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { 0 }},
+
+/* mpyml 0,ximm,u6 01011100011100010111uuuuuu111110. */
+{ "mpyml", 0x5C71703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { 0 }},
+
+/* mpyml<.cc> 0,ximm,u6 01011100111100010111uuuuuu1QQQQQ. */
+{ "mpyml", 0x5CF17020, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_CC }},
+
+/* mpyml RA,limm,RC 01011110001100010111ccccccaaaaaa. */
+{ "mpyml", 0x5E317000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* mpyml RA,RB,limm 01011bbb001100010BBB111110aaaaaa. */
+{ "mpyml", 0x58310F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* mpyml 0,limm,RC 01011110001100010111cccccc111110. */
+{ "mpyml", 0x5E31703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* mpyml 0,RB,limm 01011bbb001100010BBB111110111110. */
+{ "mpyml", 0x58310FBE, 0xF8FF8FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* mpyml<.cc> 0,limm,RC 01011110111100010111cccccc0QQQQQ. */
+{ "mpyml", 0x5EF17000, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* mpyml<.cc> RB,RB,limm 01011bbb111100010BBB1111100QQQQQ. */
+{ "mpyml", 0x58F10F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* mpyml RA,limm,u6 01011110011100010111uuuuuuaaaaaa. */
+{ "mpyml", 0x5E717000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* mpyml 0,limm,u6 01011110011100010111uuuuuu111110. */
+{ "mpyml", 0x5E71703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* mpyml<.cc> 0,limm,u6 01011110111100010111uuuuuu1QQQQQ. */
+{ "mpyml", 0x5EF17020, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* mpyml 0,ximm,s12 01011100101100010111ssssssSSSSSS. */
+{ "mpyml", 0x5CB17000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { 0 }},
+
+/* mpyml 0,limm,s12 01011110101100010111ssssssSSSSSS. */
+{ "mpyml", 0x5EB17000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* mpyml RA,ximm,ximm 01011100001100010111111100aaaaaa. */
+{ "mpyml", 0x5C317F00, 0xFFFFFFC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { 0 }},
+
+/* mpyml 0,ximm,ximm 01011100001100010111111100111110. */
+{ "mpyml", 0x5C317F3E, 0xFFFFFFFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { 0 }},
+
+/* mpyml<.cc> 0,ximm,ximm 010111001111000101111111000QQQQQ. */
+{ "mpyml", 0x5CF17F00, 0xFFFFFFE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_CC }},
+
+/* mpyml RA,limm,limm 01011110001100010111111110aaaaaa. */
+{ "mpyml", 0x5E317F80, 0xFFFFFFC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* mpyml 0,limm,limm 01011110001100010111111110111110. */
+{ "mpyml", 0x5E317FBE, 0xFFFFFFFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* mpyml<.cc> 0,limm,limm 010111101111000101111111100QQQQQ. */
+{ "mpyml", 0x5EF17F80, 0xFFFFFFE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* mpymsul RA,RB,RC 01011bbb001100110BBBccccccaaaaaa. */
+{ "mpymsul", 0x58330000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { 0 }},
+
+/* mpymsul 0,RB,RC 01011bbb001100110BBBcccccc111110. */
+{ "mpymsul", 0x5833003E, 0xF8FF803F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* mpymsul<.cc> RB,RB,RC 01011bbb111100110BBBcccccc0QQQQQ. */
+{ "mpymsul", 0x58F30000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* mpymsul RA,RB,u6 01011bbb011100110BBBuuuuuuaaaaaa. */
+{ "mpymsul", 0x58730000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* mpymsul 0,RB,u6 01011bbb011100110BBBuuuuuu111110. */
+{ "mpymsul", 0x5873003E, 0xF8FF803F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* mpymsul<.cc> RB,RB,u6 01011bbb111100110BBBuuuuuu1QQQQQ. */
+{ "mpymsul", 0x58F30020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* mpymsul RB,RB,s12 01011bbb101100110BBBssssssSSSSSS. */
+{ "mpymsul", 0x58B30000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* mpymsul RA,ximm,RC 01011100001100110111ccccccaaaaaa. */
+{ "mpymsul", 0x5C337000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { 0 }},
+
+/* mpymsul RA,RB,ximm 01011bbb001100110BBB111100aaaaaa. */
+{ "mpymsul", 0x58330F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { 0 }},
+
+/* mpymsul 0,ximm,RC 01011100001100110111cccccc111110. */
+{ "mpymsul", 0x5C33703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { 0 }},
+
+/* mpymsul 0,RB,ximm 01011bbb001100110BBB111100111110. */
+{ "mpymsul", 0x58330F3E, 0xF8FF8FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { 0 }},
+
+/* mpymsul<.cc> 0,ximm,RC 01011100111100110111cccccc0QQQQQ. */
+{ "mpymsul", 0x5CF37000, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_CC }},
+
+/* mpymsul<.cc> RB,RB,ximm 01011bbb111100110BBB1111000QQQQQ. */
+{ "mpymsul", 0x58F30F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_CC }},
+
+/* mpymsul RA,ximm,u6 01011100011100110111uuuuuuaaaaaa. */
+{ "mpymsul", 0x5C737000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { 0 }},
+
+/* mpymsul 0,ximm,u6 01011100011100110111uuuuuu111110. */
+{ "mpymsul", 0x5C73703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { 0 }},
+
+/* mpymsul<.cc> 0,ximm,u6 01011100111100110111uuuuuu1QQQQQ. */
+{ "mpymsul", 0x5CF37020, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_CC }},
+
+/* mpymsul RA,limm,RC 01011110001100110111ccccccaaaaaa. */
+{ "mpymsul", 0x5E337000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* mpymsul RA,RB,limm 01011bbb001100110BBB111110aaaaaa. */
+{ "mpymsul", 0x58330F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* mpymsul 0,limm,RC 01011110001100110111cccccc111110. */
+{ "mpymsul", 0x5E33703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* mpymsul 0,RB,limm 01011bbb001100110BBB111110111110. */
+{ "mpymsul", 0x58330FBE, 0xF8FF8FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* mpymsul<.cc> 0,limm,RC 01011110111100110111cccccc0QQQQQ. */
+{ "mpymsul", 0x5EF37000, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* mpymsul<.cc> RB,RB,limm 01011bbb111100110BBB1111100QQQQQ. */
+{ "mpymsul", 0x58F30F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* mpymsul RA,limm,u6 01011110011100110111uuuuuuaaaaaa. */
+{ "mpymsul", 0x5E737000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* mpymsul 0,limm,u6 01011110011100110111uuuuuu111110. */
+{ "mpymsul", 0x5E73703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* mpymsul<.cc> 0,limm,u6 01011110111100110111uuuuuu1QQQQQ. */
+{ "mpymsul", 0x5EF37020, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* mpymsul 0,ximm,s12 01011100101100110111ssssssSSSSSS. */
+{ "mpymsul", 0x5CB37000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { 0 }},
+
+/* mpymsul 0,limm,s12 01011110101100110111ssssssSSSSSS. */
+{ "mpymsul", 0x5EB37000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* mpymsul RA,ximm,ximm 01011100001100110111111100aaaaaa. */
+{ "mpymsul", 0x5C337F00, 0xFFFFFFC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { 0 }},
+
+/* mpymsul 0,ximm,ximm 01011100001100110111111100111110. */
+{ "mpymsul", 0x5C337F3E, 0xFFFFFFFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { 0 }},
+
+/* mpymsul<.cc> 0,ximm,ximm 010111001111001101111111000QQQQQ. */
+{ "mpymsul", 0x5CF37F00, 0xFFFFFFE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_CC }},
+
+/* mpymsul RA,limm,limm 01011110001100110111111110aaaaaa. */
+{ "mpymsul", 0x5E337F80, 0xFFFFFFC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* mpymsul 0,limm,limm 01011110001100110111111110111110. */
+{ "mpymsul", 0x5E337FBE, 0xFFFFFFFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* mpymsul<.cc> 0,limm,limm 010111101111001101111111100QQQQQ. */
+{ "mpymsul", 0x5EF37F80, 0xFFFFFFE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* mpymu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA. */
+{ "mpymu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpymu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110. */
+{ "mpymu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpymu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ. */
+{ "mpymu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpymu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA. */
+{ "mpymu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110. */
+{ "mpymu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ. */
+{ "mpymu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpymu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS. */
+{ "mpymu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpymu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA. */
+{ "mpymu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpymu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA. */
+{ "mpymu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpymu<.f> 0,limm,c 0010011000011100F111CCCCCC111110. */
+{ "mpymu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpymu<.f> 0,b,limm 00100bbb00011100FBBB111110111110. */
+{ "mpymu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpymu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ. */
+{ "mpymu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpymu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ. */
+{ "mpymu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpymu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA. */
+{ "mpymu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110. */
+{ "mpymu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpymu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ. */
+{ "mpymu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpymu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS. */
+{ "mpymu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpymu<.f> a,limm,limm 0010011000011100F111111110AAAAAA. */
+{ "mpymu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpymu<.f> 0,limm,limm 0010011000011100F111111110111110. */
+{ "mpymu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpymu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ. */
+{ "mpymu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpymul RA,RB,RC 01011bbb001100100BBBccccccaaaaaa. */
+{ "mpymul", 0x58320000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { 0 }},
+
+/* mpymul 0,RB,RC 01011bbb001100100BBBcccccc111110. */
+{ "mpymul", 0x5832003E, 0xF8FF803F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+
+/* mpymul<.cc> RB,RB,RC 01011bbb111100100BBBcccccc0QQQQQ. */
+{ "mpymul", 0x58F20000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_CC }},
+
+/* mpymul RA,RB,u6 01011bbb011100100BBBuuuuuuaaaaaa. */
+{ "mpymul", 0x58720000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+
+/* mpymul 0,RB,u6 01011bbb011100100BBBuuuuuu111110. */
+{ "mpymul", 0x5872003E, 0xF8FF803F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* mpymul<.cc> RB,RB,u6 01011bbb111100100BBBuuuuuu1QQQQQ. */
+{ "mpymul", 0x58F20020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }},
+
+/* mpymul RB,RB,s12 01011bbb101100100BBBssssssSSSSSS. */
+{ "mpymul", 0x58B20000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { 0 }},
+
+/* mpymul RA,ximm,RC 01011100001100100111ccccccaaaaaa. */
+{ "mpymul", 0x5C327000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { 0 }},
+
+/* mpymul RA,RB,ximm 01011bbb001100100BBB111100aaaaaa. */
+{ "mpymul", 0x58320F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { 0 }},
+
+/* mpymul 0,ximm,RC 01011100001100100111cccccc111110. */
+{ "mpymul", 0x5C32703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { 0 }},
+
+/* mpymul 0,RB,ximm 01011bbb001100100BBB111100111110. */
+{ "mpymul", 0x58320F3E, 0xF8FF8FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { 0 }},
+
+/* mpymul<.cc> 0,ximm,RC 01011100111100100111cccccc0QQQQQ. */
+{ "mpymul", 0x5CF27000, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_CC }},
+
+/* mpymul<.cc> RB,RB,ximm 01011bbb111100100BBB1111000QQQQQ. */
+{ "mpymul", 0x58F20F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_CC }},
+
+/* mpymul RA,ximm,u6 01011100011100100111uuuuuuaaaaaa. */
+{ "mpymul", 0x5C727000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { 0 }},
+
+/* mpymul 0,ximm,u6 01011100011100100111uuuuuu111110. */
+{ "mpymul", 0x5C72703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { 0 }},
+
+/* mpymul<.cc> 0,ximm,u6 01011100111100100111uuuuuu1QQQQQ. */
+{ "mpymul", 0x5CF27020, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_CC }},
+
+/* mpymul RA,limm,RC 01011110001100100111ccccccaaaaaa. */
+{ "mpymul", 0x5E327000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { 0 }},
+
+/* mpymul RA,RB,limm 01011bbb001100100BBB111110aaaaaa. */
+{ "mpymul", 0x58320F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { 0 }},
+
+/* mpymul 0,limm,RC 01011110001100100111cccccc111110. */
+{ "mpymul", 0x5E32703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* mpymul 0,RB,limm 01011bbb001100100BBB111110111110. */
+{ "mpymul", 0x58320FBE, 0xF8FF8FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* mpymul<.cc> 0,limm,RC 01011110111100100111cccccc0QQQQQ. */
+{ "mpymul", 0x5EF27000, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* mpymul<.cc> RB,RB,limm 01011bbb111100100BBB1111100QQQQQ. */
+{ "mpymul", 0x58F20F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_CC }},
+
+/* mpymul RA,limm,u6 01011110011100100111uuuuuuaaaaaa. */
+{ "mpymul", 0x5E727000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+
+/* mpymul 0,limm,u6 01011110011100100111uuuuuu111110. */
+{ "mpymul", 0x5E72703E, 0xFFFFF03F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* mpymul<.cc> 0,limm,u6 01011110111100100111uuuuuu1QQQQQ. */
+{ "mpymul", 0x5EF27020, 0xFFFFF020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* mpymul 0,ximm,s12 01011100101100100111ssssssSSSSSS. */
+{ "mpymul", 0x5CB27000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { 0 }},
+
+/* mpymul 0,limm,s12 01011110101100100111ssssssSSSSSS. */
+{ "mpymul", 0x5EB27000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* mpymul RA,ximm,ximm 01011100001100100111111100aaaaaa. */
+{ "mpymul", 0x5C327F00, 0xFFFFFFC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { 0 }},
+
+/* mpymul 0,ximm,ximm 01011100001100100111111100111110. */
+{ "mpymul", 0x5C327F3E, 0xFFFFFFFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { 0 }},
+
+/* mpymul<.cc> 0,ximm,ximm 010111001111001001111111000QQQQQ. */
+{ "mpymul", 0x5CF27F00, 0xFFFFFFE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_CC }},
+
+/* mpymul RA,limm,limm 01011110001100100111111110aaaaaa. */
+{ "mpymul", 0x5E327F80, 0xFFFFFFC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+
+/* mpymul 0,limm,limm 01011110001100100111111110111110. */
+{ "mpymul", 0x5E327FBE, 0xFFFFFFFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* mpymul<.cc> 0,limm,limm 010111101111001001111111100QQQQQ. */
+{ "mpymul", 0x5EF27F80, 0xFFFFFFE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* mpyu<.f> a,b,c 00100bbb00011101FBBBCCCCCCAAAAAA. */
+{ "mpyu", 0x201D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpyu<.f> 0,b,c 00100bbb00011101FBBBCCCCCC111110. */
+{ "mpyu", 0x201D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, RC }, { C_F }},
+
+/* mpyu<.f><.cc> b,b,c 00100bbb11011101FBBBCCCCCC0QQQQQ. */
+{ "mpyu", 0x20DD0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyu<.f> a,b,u6 00100bbb01011101FBBBuuuuuuAAAAAA. */
+{ "mpyu", 0x205D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f> 0,b,u6 00100bbb01011101FBBBuuuuuu111110. */
+{ "mpyu", 0x205D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f><.cc> b,b,u6 00100bbb11011101FBBBuuuuuu1QQQQQ. */
+{ "mpyu", 0x20DD0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyu<.f> b,b,s12 00100bbb10011101FBBBssssssSSSSSS. */
+{ "mpyu", 0x209D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyu<.f> a,limm,c 0010011000011101F111CCCCCCAAAAAA. */
+{ "mpyu", 0x261D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpyu<.f> a,b,limm 00100bbb00011101FBBB111110AAAAAA. */
+{ "mpyu", 0x201D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpyu<.f> 0,limm,c 0010011000011101F111CCCCCC111110. */
+{ "mpyu", 0x261D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyu<.f> 0,b,limm 00100bbb00011101FBBB111110111110. */
+{ "mpyu", 0x201D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyu<.f><.cc> b,b,limm 00100bbb11011101FBBB1111100QQQQQ. */
+{ "mpyu", 0x20DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyu<.f><.cc> 0,limm,c 0010011011011101F111CCCCCC0QQQQQ. */
+{ "mpyu", 0x26DD7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyu<.f> a,limm,u6 0010011001011101F111uuuuuuAAAAAA. */
+{ "mpyu", 0x265D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f> 0,limm,u6 0010011001011101F111uuuuuu111110. */
+{ "mpyu", 0x265D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyu<.f><.cc> 0,limm,u6 0010011011011101F111uuuuuu1QQQQQ. */
+{ "mpyu", 0x26DD7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyu<.f> 0,limm,s12 0010011010011101F111ssssssSSSSSS. */
+{ "mpyu", 0x269D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyu<.f> a,limm,limm 0010011000011101F111111110AAAAAA. */
+{ "mpyu", 0x261D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpyu<.f> 0,limm,limm 0010011000011101F111111110111110. */
+{ "mpyu", 0x261D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyu<.f><.cc> 0,limm,limm 0010011011011101F1111111100QQQQQ. */
+{ "mpyu", 0x26DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,b,c 00100bbb00011111FBBBCCCCCCAAAAAA. */
+{ "mpyuw", 0x201F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpyuw<.f> 0,b,c 00100bbb00011111FBBBCCCCCC111110. */
+{ "mpyuw", 0x201F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, RC }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,c 00100bbb11011111FBBBCCCCCC0QQQQQ. */
+{ "mpyuw", 0x20DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,b,u6 00100bbb01011111FBBBuuuuuuAAAAAA. */
+{ "mpyuw", 0x205F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f> 0,b,u6 00100bbb01011111FBBBuuuuuu111110. */
+{ "mpyuw", 0x205F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,u6 00100bbb11011111FBBBuuuuuu1QQQQQ. */
+{ "mpyuw", 0x20DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyuw<.f> b,b,s12 00100bbb10011111FBBBssssssSSSSSS. */
+{ "mpyuw", 0x209F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyuw<.f> a,limm,c 0010011000011111F111CCCCCCAAAAAA. */
+{ "mpyuw", 0x261F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpyuw<.f> a,b,limm 00100bbb00011111FBBB111110AAAAAA. */
+{ "mpyuw", 0x201F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpyuw<.f> 0,limm,c 0010011000011111F111CCCCCC111110. */
+{ "mpyuw", 0x261F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyuw<.f> 0,b,limm 00100bbb00011111FBBB111110111110. */
+{ "mpyuw", 0x201F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyuw<.f><.cc> b,b,limm 00100bbb11011111FBBB1111100QQQQQ. */
+{ "mpyuw", 0x20DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyuw<.f><.cc> 0,limm,c 0010011011011111F111CCCCCC0QQQQQ. */
+{ "mpyuw", 0x26DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyuw<.f> a,limm,u6 0010011001011111F111uuuuuuAAAAAA. */
+{ "mpyuw", 0x265F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f> 0,limm,u6 0010011001011111F111uuuuuu111110. */
+{ "mpyuw", 0x265F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyuw<.f><.cc> 0,limm,u6 0010011011011111F111uuuuuu1QQQQQ. */
+{ "mpyuw", 0x26DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyuw<.f> 0,limm,s12 0010011010011111F111ssssssSSSSSS. */
+{ "mpyuw", 0x269F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyuw<.f> a,limm,limm 0010011000011111F111111110AAAAAA. */
+{ "mpyuw", 0x261F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpyuw<.f> 0,limm,limm 0010011000011111F111111110111110. */
+{ "mpyuw", 0x261F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyuw<.f><.cc> 0,limm,limm 0010011011011111F1111111100QQQQQ. */
+{ "mpyuw", 0x26DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyuw_s b,b,c 01111bbbccc01010. */
+{ "mpyuw_s", 0x0000780A, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* mpyw<.f> a,b,c 00100bbb00011110FBBBCCCCCCAAAAAA. */
+{ "mpyw", 0x201E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpyw<.f> 0,b,c 00100bbb00011110FBBBCCCCCC111110. */
+{ "mpyw", 0x201E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, RC }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,c 00100bbb11011110FBBBCCCCCC0QQQQQ. */
+{ "mpyw", 0x20DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpyw<.f> a,b,u6 00100bbb01011110FBBBuuuuuuAAAAAA. */
+{ "mpyw", 0x205E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f> 0,b,u6 00100bbb01011110FBBBuuuuuu111110. */
+{ "mpyw", 0x205E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,u6 00100bbb11011110FBBBuuuuuu1QQQQQ. */
+{ "mpyw", 0x20DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyw<.f> b,b,s12 00100bbb10011110FBBBssssssSSSSSS. */
+{ "mpyw", 0x209E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpyw<.f> a,limm,c 0010011000011110F111CCCCCCAAAAAA. */
+{ "mpyw", 0x261E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpyw<.f> a,b,limm 00100bbb00011110FBBB111110AAAAAA. */
+{ "mpyw", 0x201E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpyw<.f> 0,limm,c 0010011000011110F111CCCCCC111110. */
+{ "mpyw", 0x261E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, RC }, { C_F }},
+
+/* mpyw<.f> 0,b,limm 00100bbb00011110FBBB111110111110. */
+{ "mpyw", 0x201E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, RB, LIMM }, { C_F }},
+
+/* mpyw<.f><.cc> b,b,limm 00100bbb11011110FBBB1111100QQQQQ. */
+{ "mpyw", 0x20DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpyw<.f><.cc> 0,limm,c 0010011011011110F111CCCCCC0QQQQQ. */
+{ "mpyw", 0x26DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpyw<.f> a,limm,u6 0010011001011110F111uuuuuuAAAAAA. */
+{ "mpyw", 0x265E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f> 0,limm,u6 0010011001011110F111uuuuuu111110. */
+{ "mpyw", 0x265E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpyw<.f><.cc> 0,limm,u6 0010011011011110F111uuuuuu1QQQQQ. */
+{ "mpyw", 0x26DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpyw<.f> 0,limm,s12 0010011010011110F111ssssssSSSSSS. */
+{ "mpyw", 0x269E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpyw<.f> a,limm,limm 0010011000011110F111111110AAAAAA. */
+{ "mpyw", 0x261E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpyw<.f> 0,limm,limm 0010011000011110F111111110111110. */
+{ "mpyw", 0x261E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpyw<.f><.cc> 0,limm,limm 0010011011011110F1111111100QQQQQ. */
+{ "mpyw", 0x26DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhfl<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA. */
+{ "mpywhfl", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpywhfl<.f> 0,b,c 00110bbb00100100FBBBCCCCCC111110. */
+{ "mpywhfl", 0x3024003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhfl<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ. */
+{ "mpywhfl", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhfl<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA. */
+{ "mpywhfl", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfl<.f> 0,b,u6 00110bbb01100100FBBBuuuuuu111110. */
+{ "mpywhfl", 0x3064003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfl<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ. */
+{ "mpywhfl", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfl<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS. */
+{ "mpywhfl", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhfl<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA. */
+{ "mpywhfl", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpywhfl<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA. */
+{ "mpywhfl", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpywhfl<.f> 0,limm,c 0011011001100100F111CCCCCC111110. */
+{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhfl<.f> 0,b,limm 00110bbb00100100FBBB111110111110. */
+{ "mpywhfl", 0x30240FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhfl<.f><.cc> b,b,limm 00110bbb11100100FBBB1111100QQQQQ. */
+{ "mpywhfl", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhfl<.f><.cc> 0,limm,c 0011011011100100F111CCCCCC0QQQQQ. */
+{ "mpywhfl", 0x36E47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhfl<.f> a,limm,u6 0011011001100100F111uuuuuuAAAAAA. */
+{ "mpywhfl", 0x36647000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfl<.f> 0,limm,u6 0011011001100100F111uuuuuu111110. */
+{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfl<.f><.cc> 0,limm,u6 0011011011100100F111uuuuuu1QQQQQ. */
+{ "mpywhfl", 0x36E47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfl<.f> 0,limm,s12 0011011010100100F111ssssssSSSSSS. */
+{ "mpywhfl", 0x36A47000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhfl<.f> a,limm,limm 0011011000100100F111111110AAAAAA. */
+{ "mpywhfl", 0x36247F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfl<.f> 0,limm,limm 0011011000100100F111111110111110. */
+{ "mpywhfl", 0x36247FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfl<.f><.cc> 0,limm,limm 0011011011100100F1111111100QQQQQ. */
+{ "mpywhfl", 0x36E47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhflr<.f> a,b,c 00110bbb00100101FBBBCCCCCCAAAAAA. */
+{ "mpywhflr", 0x30250000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpywhflr<.f> 0,b,c 00110bbb00100101FBBBCCCCCC111110. */
+{ "mpywhflr", 0x3025003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhflr<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ. */
+{ "mpywhflr", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhflr<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA. */
+{ "mpywhflr", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhflr<.f> 0,b,u6 00110bbb01100101FBBBuuuuuu111110. */
+{ "mpywhflr", 0x3065003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhflr<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ. */
+{ "mpywhflr", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhflr<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS. */
+{ "mpywhflr", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhflr<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA. */
+{ "mpywhflr", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpywhflr<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA. */
+{ "mpywhflr", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpywhflr<.f> 0,limm,c 0011011001100101F111CCCCCC111110. */
+{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhflr<.f> 0,b,limm 00110bbb00100101FBBB111110111110. */
+{ "mpywhflr", 0x30250FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhflr<.f><.cc> b,b,limm 00110bbb11100101FBBB1111100QQQQQ. */
+{ "mpywhflr", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhflr<.f><.cc> 0,limm,c 0011011011100101F111CCCCCC0QQQQQ. */
+{ "mpywhflr", 0x36E57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhflr<.f> a,limm,u6 0011011001100101F111uuuuuuAAAAAA. */
+{ "mpywhflr", 0x36657000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhflr<.f> 0,limm,u6 0011011001100101F111uuuuuu111110. */
+{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhflr<.f><.cc> 0,limm,u6 0011011011100101F111uuuuuu1QQQQQ. */
+{ "mpywhflr", 0x36E57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhflr<.f> 0,limm,s12 0011011010100101F111ssssssSSSSSS. */
+{ "mpywhflr", 0x36A57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhflr<.f> a,limm,limm 0011011000100101F111111110AAAAAA. */
+{ "mpywhflr", 0x36257F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhflr<.f> 0,limm,limm 0011011000100101F111111110111110. */
+{ "mpywhflr", 0x36257FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhflr<.f><.cc> 0,limm,limm 0011011011100101F1111111100QQQQQ. */
+{ "mpywhflr", 0x36E57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhfm<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA. */
+{ "mpywhfm", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpywhfm<.f> 0,b,c 00110bbb00100000FBBBCCCCCC111110. */
+{ "mpywhfm", 0x3020003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhfm<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ. */
+{ "mpywhfm", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhfm<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA. */
+{ "mpywhfm", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfm<.f> 0,b,u6 00110bbb01100000FBBBuuuuuu111110. */
+{ "mpywhfm", 0x3060003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfm<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ. */
+{ "mpywhfm", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfm<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS. */
+{ "mpywhfm", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhfm<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA. */
+{ "mpywhfm", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpywhfm<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA. */
+{ "mpywhfm", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpywhfm<.f> 0,limm,c 0011011001100000F111CCCCCC111110. */
+{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhfm<.f> 0,b,limm 00110bbb00100000FBBB111110111110. */
+{ "mpywhfm", 0x30200FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhfm<.f><.cc> b,b,limm 00110bbb11100000FBBB1111100QQQQQ. */
+{ "mpywhfm", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhfm<.f><.cc> 0,limm,c 0011011011100000F111CCCCCC0QQQQQ. */
+{ "mpywhfm", 0x36E07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhfm<.f> a,limm,u6 0011011001100000F111uuuuuuAAAAAA. */
+{ "mpywhfm", 0x36607000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfm<.f> 0,limm,u6 0011011001100000F111uuuuuu111110. */
+{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfm<.f><.cc> 0,limm,u6 0011011011100000F111uuuuuu1QQQQQ. */
+{ "mpywhfm", 0x36E07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfm<.f> 0,limm,s12 0011011010100000F111ssssssSSSSSS. */
+{ "mpywhfm", 0x36A07000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhfm<.f> a,limm,limm 0011011000100000F111111110AAAAAA. */
+{ "mpywhfm", 0x36207F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfm<.f> 0,limm,limm 0011011000100000F111111110111110. */
+{ "mpywhfm", 0x36207FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfm<.f><.cc> 0,limm,limm 0011011011100000F1111111100QQQQQ. */
+{ "mpywhfm", 0x36E07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhfmr<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA. */
+{ "mpywhfmr", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpywhfmr<.f> 0,b,c 00110bbb00100001FBBBCCCCCC111110. */
+{ "mpywhfmr", 0x3021003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhfmr<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ. */
+{ "mpywhfmr", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhfmr<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA. */
+{ "mpywhfmr", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfmr<.f> 0,b,u6 00110bbb01100001FBBBuuuuuu111110. */
+{ "mpywhfmr", 0x3061003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhfmr<.f><.cc> b,b,u6 00110bbb11100001FBBBuuuuuu1QQQQQ. */
+{ "mpywhfmr", 0x30E10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfmr<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS. */
+{ "mpywhfmr", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhfmr<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA. */
+{ "mpywhfmr", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpywhfmr<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA. */
+{ "mpywhfmr", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpywhfmr<.f> 0,limm,c 0011011001100001F111CCCCCC111110. */
+{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhfmr<.f> 0,b,limm 00110bbb00100001FBBB111110111110. */
+{ "mpywhfmr", 0x30210FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhfmr<.f><.cc> b,b,limm 00110bbb11100001FBBB1111100QQQQQ. */
+{ "mpywhfmr", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhfmr<.f><.cc> 0,limm,c 0011011011100001F111CCCCCC0QQQQQ. */
+{ "mpywhfmr", 0x36E17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhfmr<.f> a,limm,u6 0011011001100001F111uuuuuuAAAAAA. */
+{ "mpywhfmr", 0x36617000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfmr<.f> 0,limm,u6 0011011001100001F111uuuuuu111110. */
+{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhfmr<.f><.cc> 0,limm,u6 0011011011100001F111uuuuuu1QQQQQ. */
+{ "mpywhfmr", 0x36E17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhfmr<.f> 0,limm,s12 0011011010100001F111ssssssSSSSSS. */
+{ "mpywhfmr", 0x36A17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhfmr<.f> a,limm,limm 0011011000100001F111111110AAAAAA. */
+{ "mpywhfmr", 0x36217F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfmr<.f> 0,limm,limm 0011011000100001F111111110111110. */
+{ "mpywhfmr", 0x36217FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhfmr<.f><.cc> 0,limm,limm 0011011011100001F1111111100QQQQQ. */
+{ "mpywhfmr", 0x36E17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhkl<.f> a,b,c 00110bbb00101010FBBBCCCCCCAAAAAA. */
+{ "mpywhkl", 0x302A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpywhkl<.f> 0,b,c 00110bbb00101010FBBBCCCCCC111110. */
+{ "mpywhkl", 0x302A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhkl<.f><.cc> b,b,c 00110bbb11101010FBBBCCCCCC0QQQQQ. */
+{ "mpywhkl", 0x30EA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhkl<.f> a,b,u6 00110bbb01101010FBBBuuuuuuAAAAAA. */
+{ "mpywhkl", 0x306A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhkl<.f> 0,b,u6 00110bbb01101010FBBBuuuuuu111110. */
+{ "mpywhkl", 0x306A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhkl<.f><.cc> b,b,u6 00110bbb11101010FBBBuuuuuu1QQQQQ. */
+{ "mpywhkl", 0x30EA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhkl<.f> b,b,s12 00110bbb10101010FBBBssssssSSSSSS. */
+{ "mpywhkl", 0x30AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhkl<.f> a,limm,c 0011011000101010F111CCCCCCAAAAAA. */
+{ "mpywhkl", 0x362A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpywhkl<.f> a,b,limm 00110bbb00101010FBBB111110AAAAAA. */
+{ "mpywhkl", 0x302A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpywhkl<.f> 0,limm,c 0011011001101010F111CCCCCC111110. */
+{ "mpywhkl", 0x366A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhkl<.f> 0,b,limm 00110bbb00101010FBBB111110111110. */
+{ "mpywhkl", 0x302A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhkl<.f><.cc> b,b,limm 00110bbb11101010FBBB1111100QQQQQ. */
+{ "mpywhkl", 0x30EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhkl<.f><.cc> 0,limm,c 0011011011101010F111CCCCCC0QQQQQ. */
+{ "mpywhkl", 0x36EA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhkl<.f> a,limm,u6 0011011001101010F111uuuuuuAAAAAA. */
+{ "mpywhkl", 0x366A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhkl<.f> 0,limm,u6 0011011001101010F111uuuuuu111110. */
+{ "mpywhkl", 0x366A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhkl<.f><.cc> 0,limm,u6 0011011011101010F111uuuuuu1QQQQQ. */
+{ "mpywhkl", 0x36EA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhkl<.f> 0,limm,s12 0011011010101010F111ssssssSSSSSS. */
+{ "mpywhkl", 0x36AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhkl<.f> a,limm,limm 0011011000101010F111111110AAAAAA. */
+{ "mpywhkl", 0x362A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhkl<.f> 0,limm,limm 0011011000101010F111111110111110. */
+{ "mpywhkl", 0x362A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhkl<.f><.cc> 0,limm,limm 0011011011101010F1111111100QQQQQ. */
+{ "mpywhkl", 0x36EA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhkul<.f> a,b,c 00110bbb00101011FBBBCCCCCCAAAAAA. */
+{ "mpywhkul", 0x302B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpywhkul<.f> 0,b,c 00110bbb00101011FBBBCCCCCC111110. */
+{ "mpywhkul", 0x302B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhkul<.f><.cc> b,b,c 00110bbb11101011FBBBCCCCCC0QQQQQ. */
+{ "mpywhkul", 0x30EB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhkul<.f> a,b,u6 00110bbb01101011FBBBuuuuuuAAAAAA. */
+{ "mpywhkul", 0x306B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhkul<.f> 0,b,u6 00110bbb01101011FBBBuuuuuu111110. */
+{ "mpywhkul", 0x306B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhkul<.f><.cc> b,b,u6 00110bbb11101011FBBBuuuuuu1QQQQQ. */
+{ "mpywhkul", 0x30EB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhkul<.f> b,b,s12 00110bbb10101011FBBBssssssSSSSSS. */
+{ "mpywhkul", 0x30AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhkul<.f> a,limm,c 0011011000101011F111CCCCCCAAAAAA. */
+{ "mpywhkul", 0x362B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpywhkul<.f> a,b,limm 00110bbb00101011FBBB111110AAAAAA. */
+{ "mpywhkul", 0x302B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpywhkul<.f> 0,limm,c 0011011001101011F111CCCCCC111110. */
+{ "mpywhkul", 0x366B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhkul<.f> 0,b,limm 00110bbb00101011FBBB111110111110. */
+{ "mpywhkul", 0x302B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhkul<.f><.cc> b,b,limm 00110bbb11101011FBBB1111100QQQQQ. */
+{ "mpywhkul", 0x30EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhkul<.f><.cc> 0,limm,c 0011011011101011F111CCCCCC0QQQQQ. */
+{ "mpywhkul", 0x36EB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhkul<.f> a,limm,u6 0011011001101011F111uuuuuuAAAAAA. */
+{ "mpywhkul", 0x366B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhkul<.f> 0,limm,u6 0011011001101011F111uuuuuu111110. */
+{ "mpywhkul", 0x366B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhkul<.f><.cc> 0,limm,u6 0011011011101011F111uuuuuu1QQQQQ. */
+{ "mpywhkul", 0x36EB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhkul<.f> 0,limm,s12 0011011010101011F111ssssssSSSSSS. */
+{ "mpywhkul", 0x36AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhkul<.f> a,limm,limm 0011011000101011F111111110AAAAAA. */
+{ "mpywhkul", 0x362B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhkul<.f> 0,limm,limm 0011011000101011F111111110111110. */
+{ "mpywhkul", 0x362B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhkul<.f><.cc> 0,limm,limm 0011011011101011F1111111100QQQQQ. */
+{ "mpywhkul", 0x36EB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhl<.f> a,b,c 00110bbb00011100FBBBCCCCCCAAAAAA. */
+{ "mpywhl", 0x301C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpywhl<.f> 0,b,c 00110bbb00011100FBBBCCCCCC111110. */
+{ "mpywhl", 0x301C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhl<.f><.cc> b,b,c 00110bbb11011100FBBBCCCCCC0QQQQQ. */
+{ "mpywhl", 0x30DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhl<.f> a,b,u6 00110bbb01011100FBBBuuuuuuAAAAAA. */
+{ "mpywhl", 0x305C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhl<.f> 0,b,u6 00110bbb01011100FBBBuuuuuu111110. */
+{ "mpywhl", 0x305C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhl<.f><.cc> b,b,u6 00110bbb11011100FBBBuuuuuu1QQQQQ. */
+{ "mpywhl", 0x30DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhl<.f> b,b,s12 00110bbb10011100FBBBssssssSSSSSS. */
+{ "mpywhl", 0x309C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhl<.f> a,limm,c 0011011000011100F111CCCCCCAAAAAA. */
+{ "mpywhl", 0x361C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpywhl<.f> a,b,limm 00110bbb00011100FBBB111110AAAAAA. */
+{ "mpywhl", 0x301C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpywhl<.f> 0,limm,c 0011011000011100F111CCCCCC111110. */
+{ "mpywhl", 0x361C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhl<.f> 0,b,limm 00110bbb00011100FBBB111110111110. */
+{ "mpywhl", 0x301C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhl<.f><.cc> b,b,limm 00110bbb11011100FBBB1111100QQQQQ. */
+{ "mpywhl", 0x30DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhl<.f><.cc> 0,limm,c 0011011011011100F111CCCCCC0QQQQQ. */
+{ "mpywhl", 0x36DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhl<.f> a,limm,u6 0011011001011100F111uuuuuuAAAAAA. */
+{ "mpywhl", 0x365C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhl<.f> 0,limm,u6 0011011001011100F111uuuuuu111110. */
+{ "mpywhl", 0x365C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhl<.f><.cc> 0,limm,u6 0011011011011100F111uuuuuu1QQQQQ. */
+{ "mpywhl", 0x36DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhl<.f> 0,limm,s12 0011011010011100F111ssssssSSSSSS. */
+{ "mpywhl", 0x369C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhl<.f> a,limm,limm 0011011000011100F111111110AAAAAA. */
+{ "mpywhl", 0x361C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhl<.f> 0,limm,limm 0011011000011100F111111110111110. */
+{ "mpywhl", 0x361C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhl<.f><.cc> 0,limm,limm 0011011011011100F1111111100QQQQQ. */
+{ "mpywhl", 0x36DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpywhul<.f> a,b,c 00110bbb00011110FBBBCCCCCCAAAAAA. */
+{ "mpywhul", 0x301E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* mpywhul<.f> 0,b,c 00110bbb00011110FBBBCCCCCC111110. */
+{ "mpywhul", 0x301E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* mpywhul<.f><.cc> b,b,c 00110bbb11011110FBBBCCCCCC0QQQQQ. */
+{ "mpywhul", 0x30DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* mpywhul<.f> a,b,u6 00110bbb01011110FBBBuuuuuuAAAAAA. */
+{ "mpywhul", 0x305E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhul<.f> 0,b,u6 00110bbb01011110FBBBuuuuuu111110. */
+{ "mpywhul", 0x305E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* mpywhul<.f><.cc> b,b,u6 00110bbb11011110FBBBuuuuuu1QQQQQ. */
+{ "mpywhul", 0x30DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhul<.f> b,b,s12 00110bbb10011110FBBBssssssSSSSSS. */
+{ "mpywhul", 0x309E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* mpywhul<.f> a,limm,c 0011011000011110F111CCCCCCAAAAAA. */
+{ "mpywhul", 0x361E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* mpywhul<.f> a,b,limm 00110bbb00011110FBBB111110AAAAAA. */
+{ "mpywhul", 0x301E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* mpywhul<.f> 0,limm,c 0011011000011110F111CCCCCC111110. */
+{ "mpywhul", 0x361E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* mpywhul<.f> 0,b,limm 00110bbb00011110FBBB111110111110. */
+{ "mpywhul", 0x301E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* mpywhul<.f><.cc> b,b,limm 00110bbb11011110FBBB1111100QQQQQ. */
+{ "mpywhul", 0x30DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* mpywhul<.f><.cc> 0,limm,c 0011011011011110F111CCCCCC0QQQQQ. */
+{ "mpywhul", 0x36DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* mpywhul<.f> a,limm,u6 0011011001011110F111uuuuuuAAAAAA. */
+{ "mpywhul", 0x365E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhul<.f> 0,limm,u6 0011011001011110F111uuuuuu111110. */
+{ "mpywhul", 0x365E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* mpywhul<.f><.cc> 0,limm,u6 0011011011011110F111uuuuuu1QQQQQ. */
+{ "mpywhul", 0x36DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* mpywhul<.f> 0,limm,s12 0011011010011110F111ssssssSSSSSS. */
+{ "mpywhul", 0x369E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* mpywhul<.f> a,limm,limm 0011011000011110F111111110AAAAAA. */
+{ "mpywhul", 0x361E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhul<.f> 0,limm,limm 0011011000011110F111111110111110. */
+{ "mpywhul", 0x361E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* mpywhul<.f><.cc> 0,limm,limm 0011011011011110F1111111100QQQQQ. */
+{ "mpywhul", 0x36DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* mpyw_s b,b,c 01111bbbccc01001. */
+{ "mpyw_s", 0x00007809, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY1E, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* mpy_s b,b,c 01111bbbccc01100. */
+{ "mpy_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY6E, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* msubdf<.f> a,b,c 00110bbb00010101FBBBCCCCCCAAAAAA. */
+{ "msubdf", 0x30150000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* msubdf<.f> 0,b,c 00110bbb00010101FBBBCCCCCC111110. */
+{ "msubdf", 0x3015003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubdf<.f><.cc> b,b,c 00110bbb11010101FBBBCCCCCC0QQQQQ. */
+{ "msubdf", 0x30D50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* msubdf<.f> a,b,u6 00110bbb01010101FBBBuuuuuuAAAAAA. */
+{ "msubdf", 0x30550000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* msubdf<.f> 0,b,u6 00110bbb01010101FBBBuuuuuu111110. */
+{ "msubdf", 0x3055003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubdf<.f><.cc> b,b,u6 00110bbb11010101FBBBuuuuuu1QQQQQ. */
+{ "msubdf", 0x30D50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubdf<.f> b,b,s12 00110bbb10010101FBBBssssssSSSSSS. */
+{ "msubdf", 0x30950000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubdf<.f> a,limm,c 0011011000010101F111CCCCCCAAAAAA. */
+{ "msubdf", 0x36157000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* msubdf<.f> a,b,limm 00110bbb00010101FBBB111110AAAAAA. */
+{ "msubdf", 0x30150F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* msubdf<.f> 0,limm,c 0011011000010101F111CCCCCC111110. */
+{ "msubdf", 0x3615703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubdf<.f> 0,b,limm 00110bbb00010101FBBB111110111110. */
+{ "msubdf", 0x30150FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubdf<.f><.cc> b,b,limm 00110bbb11010101FBBB1111100QQQQQ. */
+{ "msubdf", 0x30D50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubdf<.f><.cc> 0,limm,c 0011011011010101F111CCCCCC0QQQQQ. */
+{ "msubdf", 0x36D57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubdf<.f> a,limm,u6 0011011001010101F111uuuuuuAAAAAA. */
+{ "msubdf", 0x36557000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubdf<.f> 0,limm,u6 0011011001010101F111uuuuuu111110. */
+{ "msubdf", 0x3655703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubdf<.f><.cc> 0,limm,u6 0011011011010101F111uuuuuu1QQQQQ. */
+{ "msubdf", 0x36D57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubdf<.f> 0,limm,s12 0011011010010101F111ssssssSSSSSS. */
+{ "msubdf", 0x36957000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubdf<.f> a,limm,limm 0011011000010101F111111110AAAAAA. */
+{ "msubdf", 0x36157F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* msubdf<.f> 0,limm,limm 0011011000010101F111111110111110. */
+{ "msubdf", 0x36157FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubdf<.f><.cc> 0,limm,limm 0011011011010101F1111111100QQQQQ. */
+{ "msubdf", 0x36D57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* msubf<.f> a,b,c 00110bbb00001110FBBBCCCCCCAAAAAA. */
+{ "msubf", 0x300E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* msubf<.f> 0,b,c 00110bbb00001110FBBBCCCCCC111110. */
+{ "msubf", 0x300E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubf<.f><.cc> b,b,c 00110bbb11001110FBBBCCCCCC0QQQQQ. */
+{ "msubf", 0x30CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* msubf<.f> a,b,u6 00110bbb01001110FBBBuuuuuuAAAAAA. */
+{ "msubf", 0x304E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* msubf<.f> 0,b,u6 00110bbb01001110FBBBuuuuuu111110. */
+{ "msubf", 0x304E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubf<.f><.cc> b,b,u6 00110bbb11001110FBBBuuuuuu1QQQQQ. */
+{ "msubf", 0x30CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubf<.f> b,b,s12 00110bbb10001110FBBBssssssSSSSSS. */
+{ "msubf", 0x308E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubf<.f> a,limm,c 0011011000001110F111CCCCCCAAAAAA. */
+{ "msubf", 0x360E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* msubf<.f> a,b,limm 00110bbb00001110FBBB111110AAAAAA. */
+{ "msubf", 0x300E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* msubf<.f> 0,limm,c 0011011000001110F111CCCCCC111110. */
+{ "msubf", 0x360E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubf<.f> 0,b,limm 00110bbb00001110FBBB111110111110. */
+{ "msubf", 0x300E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubf<.f><.cc> b,b,limm 00110bbb11001110FBBB1111100QQQQQ. */
+{ "msubf", 0x30CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubf<.f><.cc> 0,limm,c 0011011011001110F111CCCCCC0QQQQQ. */
+{ "msubf", 0x36CE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubf<.f> a,limm,u6 0011011001001110F111uuuuuuAAAAAA. */
+{ "msubf", 0x364E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubf<.f> 0,limm,u6 0011011001001110F111uuuuuu111110. */
+{ "msubf", 0x364E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubf<.f><.cc> 0,limm,u6 0011011011001110F111uuuuuu1QQQQQ. */
+{ "msubf", 0x36CE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubf<.f> 0,limm,s12 0011011010001110F111ssssssSSSSSS. */
+{ "msubf", 0x368E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubf<.f> a,limm,limm 0011011000001110F111111110AAAAAA. */
+{ "msubf", 0x360E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* msubf<.f> 0,limm,limm 0011011000001110F111111110111110. */
+{ "msubf", 0x360E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubf<.f><.cc> 0,limm,limm 0011011011001110F1111111100QQQQQ. */
+{ "msubf", 0x36CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* msubfr<.f> a,b,c 00110bbb00001111FBBBCCCCCCAAAAAA. */
+{ "msubfr", 0x300F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* msubfr<.f> 0,b,c 00110bbb00001111FBBBCCCCCC111110. */
+{ "msubfr", 0x300F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubfr<.f><.cc> b,b,c 00110bbb11001111FBBBCCCCCC0QQQQQ. */
+{ "msubfr", 0x30CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* msubfr<.f> a,b,u6 00110bbb01001111FBBBuuuuuuAAAAAA. */
+{ "msubfr", 0x304F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* msubfr<.f> 0,b,u6 00110bbb01001111FBBBuuuuuu111110. */
+{ "msubfr", 0x304F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubfr<.f><.cc> b,b,u6 00110bbb11001111FBBBuuuuuu1QQQQQ. */
+{ "msubfr", 0x30CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubfr<.f> b,b,s12 00110bbb10001111FBBBssssssSSSSSS. */
+{ "msubfr", 0x308F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubfr<.f> a,limm,c 0011011000001111F111CCCCCCAAAAAA. */
+{ "msubfr", 0x360F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* msubfr<.f> a,b,limm 00110bbb00001111FBBB111110AAAAAA. */
+{ "msubfr", 0x300F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* msubfr<.f> 0,limm,c 0011011000001111F111CCCCCC111110. */
+{ "msubfr", 0x360F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubfr<.f> 0,b,limm 00110bbb00001111FBBB111110111110. */
+{ "msubfr", 0x300F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubfr<.f><.cc> b,b,limm 00110bbb11001111FBBB1111100QQQQQ. */
+{ "msubfr", 0x30CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubfr<.f><.cc> 0,limm,c 0011011011001111F111CCCCCC0QQQQQ. */
+{ "msubfr", 0x36CF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubfr<.f> a,limm,u6 0011011001001111F111uuuuuuAAAAAA. */
+{ "msubfr", 0x364F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubfr<.f> 0,limm,u6 0011011001001111F111uuuuuu111110. */
+{ "msubfr", 0x364F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubfr<.f><.cc> 0,limm,u6 0011011011001111F111uuuuuu1QQQQQ. */
+{ "msubfr", 0x36CF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubfr<.f> 0,limm,s12 0011011010001111F111ssssssSSSSSS. */
+{ "msubfr", 0x368F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubfr<.f> a,limm,limm 0011011000001111F111111110AAAAAA. */
+{ "msubfr", 0x360F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* msubfr<.f> 0,limm,limm 0011011000001111F111111110111110. */
+{ "msubfr", 0x360F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubfr<.f><.cc> 0,limm,limm 0011011011001111F1111111100QQQQQ. */
+{ "msubfr", 0x36CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* msubwhfl<.f> a,b,c 00110bbb00010100FBBBCCCCCCAAAAAA. */
+{ "msubwhfl", 0x30140000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* msubwhfl<.f> 0,b,c 00110bbb00010100FBBBCCCCCC111110. */
+{ "msubwhfl", 0x3014003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubwhfl<.f><.cc> b,b,c 00110bbb11010100FBBBCCCCCC0QQQQQ. */
+{ "msubwhfl", 0x30D40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* msubwhfl<.f> a,b,u6 00110bbb01010100FBBBuuuuuuAAAAAA. */
+{ "msubwhfl", 0x30540000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* msubwhfl<.f> 0,b,u6 00110bbb01010100FBBBuuuuuu111110. */
+{ "msubwhfl", 0x3054003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubwhfl<.f><.cc> b,b,u6 00110bbb11010100FBBBuuuuuu1QQQQQ. */
+{ "msubwhfl", 0x30D40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubwhfl<.f> b,b,s12 00110bbb10010100FBBBssssssSSSSSS. */
+{ "msubwhfl", 0x30940000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubwhfl<.f> a,limm,c 0011011000010100F111CCCCCCAAAAAA. */
+{ "msubwhfl", 0x36147000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* msubwhfl<.f> a,b,limm 00110bbb00010100FBBB111110AAAAAA. */
+{ "msubwhfl", 0x30140F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* msubwhfl<.f> 0,limm,c 0011011000010100F111CCCCCC111110. */
+{ "msubwhfl", 0x3614703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubwhfl<.f> 0,b,limm 00110bbb00010100FBBB111110111110. */
+{ "msubwhfl", 0x30140FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubwhfl<.f><.cc> b,b,limm 00110bbb11010100FBBB1111100QQQQQ. */
+{ "msubwhfl", 0x30D40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubwhfl<.f><.cc> 0,limm,c 0011011011010100F111CCCCCC0QQQQQ. */
+{ "msubwhfl", 0x36D47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubwhfl<.f> a,limm,u6 0011011001010100F111uuuuuuAAAAAA. */
+{ "msubwhfl", 0x36547000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubwhfl<.f> 0,limm,u6 0011011001010100F111uuuuuu111110. */
+{ "msubwhfl", 0x3654703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubwhfl<.f><.cc> 0,limm,u6 0011011011010100F111uuuuuu1QQQQQ. */
+{ "msubwhfl", 0x36D47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubwhfl<.f> 0,limm,s12 0011011010010100F111ssssssSSSSSS. */
+{ "msubwhfl", 0x36947000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubwhfl<.f> a,limm,limm 0011011000010100F111111110AAAAAA. */
+{ "msubwhfl", 0x36147F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* msubwhfl<.f> 0,limm,limm 0011011000010100F111111110111110. */
+{ "msubwhfl", 0x36147FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubwhfl<.f><.cc> 0,limm,limm 0011011011010100F1111111100QQQQQ. */
+{ "msubwhfl", 0x36D47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* msubwhflr<.f> a,b,c 00110bbb00011010FBBBCCCCCCAAAAAA. */
+{ "msubwhflr", 0x301A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* msubwhflr<.f> 0,b,c 00110bbb00011010FBBBCCCCCC111110. */
+{ "msubwhflr", 0x301A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubwhflr<.f><.cc> b,b,c 00110bbb11011010FBBBCCCCCC0QQQQQ. */
+{ "msubwhflr", 0x30DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* msubwhflr<.f> a,b,u6 00110bbb01011010FBBBuuuuuuAAAAAA. */
+{ "msubwhflr", 0x305A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* msubwhflr<.f> 0,b,u6 00110bbb01011010FBBBuuuuuu111110. */
+{ "msubwhflr", 0x305A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubwhflr<.f><.cc> b,b,u6 00110bbb11011010FBBBuuuuuu1QQQQQ. */
+{ "msubwhflr", 0x30DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubwhflr<.f> b,b,s12 00110bbb10011010FBBBssssssSSSSSS. */
+{ "msubwhflr", 0x309A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubwhflr<.f> a,limm,c 0011011000011010F111CCCCCCAAAAAA. */
+{ "msubwhflr", 0x361A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* msubwhflr<.f> a,b,limm 00110bbb00011010FBBB111110AAAAAA. */
+{ "msubwhflr", 0x301A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* msubwhflr<.f> 0,limm,c 0011011000011010F111CCCCCC111110. */
+{ "msubwhflr", 0x361A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubwhflr<.f> 0,b,limm 00110bbb00011010FBBB111110111110. */
+{ "msubwhflr", 0x301A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubwhflr<.f><.cc> b,b,limm 00110bbb11011010FBBB1111100QQQQQ. */
+{ "msubwhflr", 0x30DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubwhflr<.f><.cc> 0,limm,c 0011011011011010F111CCCCCC0QQQQQ. */
+{ "msubwhflr", 0x36DA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubwhflr<.f> a,limm,u6 0011011001011010F111uuuuuuAAAAAA. */
+{ "msubwhflr", 0x365A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubwhflr<.f> 0,limm,u6 0011011001011010F111uuuuuu111110. */
+{ "msubwhflr", 0x365A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubwhflr<.f><.cc> 0,limm,u6 0011011011011010F111uuuuuu1QQQQQ. */
+{ "msubwhflr", 0x36DA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubwhflr<.f> 0,limm,s12 0011011010011010F111ssssssSSSSSS. */
+{ "msubwhflr", 0x369A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubwhflr<.f> a,limm,limm 0011011000011010F111111110AAAAAA. */
+{ "msubwhflr", 0x361A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* msubwhflr<.f> 0,limm,limm 0011011000011010F111111110111110. */
+{ "msubwhflr", 0x361A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubwhflr<.f><.cc> 0,limm,limm 0011011011011010F1111111100QQQQQ. */
+{ "msubwhflr", 0x36DA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* msubwhfm<.f> a,b,c 00110bbb00101100FBBBCCCCCCAAAAAA. */
+{ "msubwhfm", 0x302C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* msubwhfm<.f> 0,b,c 00110bbb00101100FBBBCCCCCC111110. */
+{ "msubwhfm", 0x302C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubwhfm<.f><.cc> b,b,c 00110bbb11101100FBBBCCCCCC0QQQQQ. */
+{ "msubwhfm", 0x30EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* msubwhfm<.f> a,b,u6 00110bbb01101100FBBBuuuuuuAAAAAA. */
+{ "msubwhfm", 0x306C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* msubwhfm<.f> 0,b,u6 00110bbb01101100FBBBuuuuuu111110. */
+{ "msubwhfm", 0x306C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubwhfm<.f><.cc> b,b,u6 00110bbb11101100FBBBuuuuuu1QQQQQ. */
+{ "msubwhfm", 0x30EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubwhfm<.f> b,b,s12 00110bbb10101100FBBBssssssSSSSSS. */
+{ "msubwhfm", 0x30AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubwhfm<.f> a,limm,c 0011011000101100F111CCCCCCAAAAAA. */
+{ "msubwhfm", 0x362C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* msubwhfm<.f> a,b,limm 00110bbb00101100FBBB111110AAAAAA. */
+{ "msubwhfm", 0x302C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* msubwhfm<.f> 0,limm,c 0011011001101100F111CCCCCC111110. */
+{ "msubwhfm", 0x366C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubwhfm<.f> 0,b,limm 00110bbb00101100FBBB111110111110. */
+{ "msubwhfm", 0x302C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubwhfm<.f><.cc> b,b,limm 00110bbb11101100FBBB1111100QQQQQ. */
+{ "msubwhfm", 0x30EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubwhfm<.f><.cc> 0,limm,c 0011011011101100F111CCCCCC0QQQQQ. */
+{ "msubwhfm", 0x36EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubwhfm<.f> a,limm,u6 0011011001101100F111uuuuuuAAAAAA. */
+{ "msubwhfm", 0x366C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubwhfm<.f> 0,limm,u6 0011011001101100F111uuuuuu111110. */
+{ "msubwhfm", 0x366C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubwhfm<.f><.cc> 0,limm,u6 0011011011101100F111uuuuuu1QQQQQ. */
+{ "msubwhfm", 0x36EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubwhfm<.f> 0,limm,s12 0011011010101100F111ssssssSSSSSS. */
+{ "msubwhfm", 0x36AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubwhfm<.f> a,limm,limm 0011011000101100F111111110AAAAAA. */
+{ "msubwhfm", 0x362C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* msubwhfm<.f> 0,limm,limm 0011011000101100F111111110111110. */
+{ "msubwhfm", 0x362C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubwhfm<.f><.cc> 0,limm,limm 0011011011101100F1111111100QQQQQ. */
+{ "msubwhfm", 0x36EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* msubwhfmr<.f> a,b,c 00110bbb00101101FBBBCCCCCCAAAAAA. */
+{ "msubwhfmr", 0x302D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { C_F }},
+
+/* msubwhfmr<.f> 0,b,c 00110bbb00101101FBBBCCCCCC111110. */
+{ "msubwhfmr", 0x302D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { C_F }},
+
+/* msubwhfmr<.f><.cc> b,b,c 00110bbb11101101FBBBCCCCCC0QQQQQ. */
+{ "msubwhfmr", 0x30ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* msubwhfmr<.f> a,b,u6 00110bbb01101101FBBBuuuuuuAAAAAA. */
+{ "msubwhfmr", 0x306D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* msubwhfmr<.f> 0,b,u6 00110bbb01101101FBBBuuuuuu111110. */
+{ "msubwhfmr", 0x306D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* msubwhfmr<.f><.cc> b,b,u6 00110bbb11101101FBBBuuuuuu1QQQQQ. */
+{ "msubwhfmr", 0x30ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubwhfmr<.f> b,b,s12 00110bbb10101101FBBBssssssSSSSSS. */
+{ "msubwhfmr", 0x30AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* msubwhfmr<.f> a,limm,c 0011011000101101F111CCCCCCAAAAAA. */
+{ "msubwhfmr", 0x362D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* msubwhfmr<.f> a,b,limm 00110bbb00101101FBBB111110AAAAAA. */
+{ "msubwhfmr", 0x302D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* msubwhfmr<.f> 0,limm,c 0011011001101101F111CCCCCC111110. */
+{ "msubwhfmr", 0x366D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* msubwhfmr<.f> 0,b,limm 00110bbb00101101FBBB111110111110. */
+{ "msubwhfmr", 0x302D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* msubwhfmr<.f><.cc> b,b,limm 00110bbb11101101FBBB1111100QQQQQ. */
+{ "msubwhfmr", 0x30ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* msubwhfmr<.f><.cc> 0,limm,c 0011011011101101F111CCCCCC0QQQQQ. */
+{ "msubwhfmr", 0x36ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* msubwhfmr<.f> a,limm,u6 0011011001101101F111uuuuuuAAAAAA. */
+{ "msubwhfmr", 0x366D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubwhfmr<.f> 0,limm,u6 0011011001101101F111uuuuuu111110. */
+{ "msubwhfmr", 0x366D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* msubwhfmr<.f><.cc> 0,limm,u6 0011011011101101F111uuuuuu1QQQQQ. */
+{ "msubwhfmr", 0x36ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* msubwhfmr<.f> 0,limm,s12 0011011010101101F111ssssssSSSSSS. */
+{ "msubwhfmr", 0x36AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* msubwhfmr<.f> a,limm,limm 0011011000101101F111111110AAAAAA. */
+{ "msubwhfmr", 0x362D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* msubwhfmr<.f> 0,limm,limm 0011011000101101F111111110111110. */
+{ "msubwhfmr", 0x362D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* msubwhfmr<.f><.cc> 0,limm,limm 0011011011101101F1111111100QQQQQ. */
+{ "msubwhfmr", 0x36ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* neg<.f> a,b 00100bbb01001110FBBB000000AAAAAA. */
+{ "neg", 0x204E0000, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB }, { C_F }},
+
+/* neg<.f><.cc> b,b 00100bbb11001110FBBB0000001QQQQQ. */
+{ "neg", 0x20CE0020, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup }, { C_F, C_CC }},
+
+/* neg<.f> a,limm 0010011001001110F111000000AAAAAA. */
+{ "neg", 0x264E7000, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM }, { C_F }},
+
+/* neg<.f><.cc> 0,limm 0010011011001110F1110000001QQQQQ. */
+{ "neg", 0x26CE7020, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F, C_CC }},
+
+/* negs<.f> b,c 00101bbb00101111FBBBCCCCCC000111. */
+{ "negs", 0x282F0007, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* negs<.f> 0,c 0010111000101111F111CCCCCC000111. */
+{ "negs", 0x2E2F7007, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* negs<.f> b,u6 00101bbb01101111FBBBuuuuuu000111. */
+{ "negs", 0x286F0007, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* negs<.f> 0,u6 0010111001101111F111uuuuuu000111. */
+{ "negs", 0x2E6F7007, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* negs<.f> b,limm 00101bbb00101111FBBB111110000111. */
+{ "negs", 0x282F0F87, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* negs<.f> 0,limm 0010111000101111F111111110000111. */
+{ "negs", 0x2E2F7F87, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* negsh<.f> b,c 00101bbb00101111FBBBCCCCCC000110. */
+{ "negsh", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { C_F }},
+
+/* negsh<.f> 0,c 0010111000101111F111CCCCCC000110. */
+{ "negsh", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* negsh<.f> b,u6 00101bbb01101111FBBBuuuuuu000110. */
+{ "negsh", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { C_F }},
+
+/* negsh<.f> 0,u6 0010111001101111F111uuuuuu000110. */
+{ "negsh", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* negsh<.f> b,limm 00101bbb00101111FBBB111110000110. */
+{ "negsh", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { C_F }},
+
+/* negsh<.f> 0,limm 0010111000101111F111111110000110. */
+{ "negsh", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* neg_s b,c 01111bbbccc10011. */
+{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* nop_s 0111100011100000. */
+{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001. */
+{ "norm", 0x282F0001, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, RC }, { C_F }},
+
+/* norm<.f> 0,c 0010111000101111F111CCCCCC000001. */
+{ "norm", 0x2E2F7001, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, RC }, { C_F }},
+
+/* norm<.f> b,u6 00101bbb01101111FBBBuuuuuu000001. */
+{ "norm", 0x286F0001, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }},
+
+/* norm<.f> 0,u6 0010111001101111F111uuuuuu000001. */
+{ "norm", 0x2E6F7001, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }},
+
+/* norm<.f> b,limm 00101bbb00101111FBBB111110000001. */
+{ "norm", 0x282F0F81, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, LIMM }, { C_F }},
+
+/* norm<.f> 0,limm 0010111000101111F111111110000001. */
+{ "norm", 0x2E2F7F81, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, LIMM }, { C_F }},
+
+/* normacc b,c 00101bbb001011110BBBCCCCCC011001. */
+{ "normacc", 0x282F0019, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* normacc 0,c 00101110001011110111CCCCCC011001. */
+{ "normacc", 0x2E2F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* normacc b,u6 00101bbb011011110BBBuuuuuu011001. */
+{ "normacc", 0x286F0019, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* normacc 0,u6 00101110011011110111uuuuuu011001. */
+{ "normacc", 0x2E6F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* normacc b,limm 00101bbb001011110BBB111110011001. */
+{ "normacc", 0x282F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* normacc 0,limm 00101110001011110111111110011001. */
+{ "normacc", 0x2E2F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* normh<.f> b,c 00101bbb00101111FBBBCCCCCC001000. */
+{ "normh", 0x282F0008, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, RC }, { C_F }},
+
+/* normh<.f> 0,c 0010111000101111F111CCCCCC001000. */
+{ "normh", 0x2E2F7008, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, RC }, { C_F }},
+
+/* normh<.f> b,u6 00101bbb01101111FBBBuuuuuu001000. */
+{ "normh", 0x286F0008, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }},
+
+/* normh<.f> 0,u6 0010111001101111F111uuuuuu001000. */
+{ "normh", 0x2E6F7008, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }},
+
+/* normh<.f> b,limm 00101bbb00101111FBBB111110001000. */
+{ "normh", 0x282F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { RB, LIMM }, { C_F }},
+
+/* normh<.f> 0,limm 0010111000101111F111111110001000. */
+{ "normh", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, BTSCN, { ZA, LIMM }, { C_F }},
+
+/* norml<.f> RB,RC 01011bbb00101111FBBBcccccc100001. */
+{ "norml", 0x582F0021, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* norml<.f> 0,RC 0101111000101111F111cccccc100001. */
+{ "norml", 0x5E2F7021, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* norml<.f> RB,u6 01011bbb01101111FBBBuuuuuu100001. */
+{ "norml", 0x586F0021, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* norml<.f> 0,u6 0101111001101111F111uuuuuu100001. */
+{ "norml", 0x5E6F7021, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* norml<.f> RB,ximm 01011bbb00101111FBBB111100100001. */
+{ "norml", 0x582F0F21, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* norml<.f> 0,ximm 0101111000101111F111111100100001. */
+{ "norml", 0x5E2F7F21, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* norml<.f> RB,limm 01011bbb00101111FBBB111110100001. */
+{ "norml", 0x582F0FA1, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* norml<.f> 0,limm 0101111000101111F111111110100001. */
+{ "norml", 0x5E2F7FA1, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* not<.f> b,c 00100bbb00101111FBBBCCCCCC001010. */
+{ "not", 0x202F000A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* not<.f> 0,c 0010011000101111F111CCCCCC001010. */
+{ "not", 0x262F700A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* not<.f> b,u6 00100bbb01101111FBBBuuuuuu001010. */
+{ "not", 0x206F000A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* not<.f> 0,u6 0010011001101111F111uuuuuu001010. */
+{ "not", 0x266F700A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* not<.f> b,limm 00100bbb00101111FBBB111110001010. */
+{ "not", 0x202F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* not<.f> 0,limm 0010011000101111F111111110001010. */
+{ "not", 0x262F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* notl<.f> RB,RC 01011bbb00101111FBBBcccccc001010. */
+{ "notl", 0x582F000A, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* notl<.f> 0,RC 0101111000101111F111cccccc001010. */
+{ "notl", 0x5E2F700A, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* notl<.f> RB,u6 01011bbb01101111FBBBuuuuuu001010. */
+{ "notl", 0x586F000A, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* notl<.f> 0,u6 0101111001101111F111uuuuuu001010. */
+{ "notl", 0x5E6F700A, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* notl<.f> RB,ximm 01011bbb00101111FBBB111100001010. */
+{ "notl", 0x582F0F0A, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* notl<.f> 0,ximm 0101111000101111F111111100001010. */
+{ "notl", 0x5E2F7F0A, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* notl<.f> RB,limm 01011bbb00101111FBBB111110001010. */
+{ "notl", 0x582F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* notl<.f> 0,limm 0101111000101111F111111110001010. */
+{ "notl", 0x5E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* not_s b,c 01111bbbccc10010. */
+{ "not_s", 0x00007812, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* or<.f> a,b,c 00100bbb00000101FBBBCCCCCCAAAAAA. */
+{ "or", 0x20050000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* or<.f> 0,b,c 00100bbb00000101FBBBCCCCCC111110. */
+{ "or", 0x2005003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* or<.f><.cc> b,b,c 00100bbb11000101FBBBCCCCCC0QQQQQ. */
+{ "or", 0x20C50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* or<.f> a,b,u6 00100bbb01000101FBBBuuuuuuAAAAAA. */
+{ "or", 0x20450000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* or<.f> 0,b,u6 00100bbb01000101FBBBuuuuuu111110. */
+{ "or", 0x2045003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* or<.f><.cc> b,b,u6 00100bbb11000101FBBBuuuuuu1QQQQQ. */
+{ "or", 0x20C50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* or<.f> b,b,s12 00100bbb10000101FBBBssssssSSSSSS. */
+{ "or", 0x20850000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* or<.f> a,limm,c 0010011000000101F111CCCCCCAAAAAA. */
+{ "or", 0x26057000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* or<.f> a,b,limm 00100bbb00000101FBBB111110AAAAAA. */
+{ "or", 0x20050F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* or<.f> 0,limm,c 0010011000000101F111CCCCCC111110. */
+{ "or", 0x2605703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* or<.f> 0,b,limm 00100bbb00000101FBBB111110111110. */
+{ "or", 0x20050FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* or<.f><.cc> b,b,limm 00100bbb11000101FBBB1111100QQQQQ. */
+{ "or", 0x20C50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* or<.f><.cc> 0,limm,c 0010011011000101F111CCCCCC0QQQQQ. */
+{ "or", 0x26C57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* or<.f> a,limm,u6 0010011001000101F111uuuuuuAAAAAA. */
+{ "or", 0x26457000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* or<.f> 0,limm,u6 0010011001000101F111uuuuuu111110. */
+{ "or", 0x2645703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* or<.f><.cc> 0,limm,u6 0010011011000101F111uuuuuu1QQQQQ. */
+{ "or", 0x26C57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* or<.f> 0,limm,s12 0010011010000101F111ssssssSSSSSS. */
+{ "or", 0x26857000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* or<.f> a,limm,limm 0010011000000101F111111110AAAAAA. */
+{ "or", 0x26057F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* or<.f> 0,limm,limm 0010011000000101F111111110111110. */
+{ "or", 0x26057FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* or<.f><.cc> 0,limm,limm 0010011011000101F1111111100QQQQQ. */
+{ "or", 0x26C57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* orl<.f> RA,RB,RC 01011bbb00000101FBBBccccccaaaaaa. */
+{ "orl", 0x58050000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* orl<.f> 0,RB,RC 01011bbb00000101FBBBcccccc111110. */
+{ "orl", 0x5805003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* orl<.f><.cc> RB,RB,RC 01011bbb11000101FBBBcccccc0QQQQQ. */
+{ "orl", 0x58C50000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* orl<.f> RA,RB,u6 01011bbb01000101FBBBuuuuuuaaaaaa. */
+{ "orl", 0x58450000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* orl<.f> 0,RB,u6 01011bbb01000101FBBBuuuuuu111110. */
+{ "orl", 0x5845003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* orl<.f><.cc> RB,RB,u6 01011bbb11000101FBBBuuuuuu1QQQQQ. */
+{ "orl", 0x58C50020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* orl<.f> RB,RB,s12 01011bbb10000101FBBBssssssSSSSSS. */
+{ "orl", 0x58850000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* orl<.f> RA,ximm,RC 0101110000000101F111ccccccaaaaaa. */
+{ "orl", 0x5C057000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* orl<.f> RA,RB,ximm 01011bbb00000101FBBB111100aaaaaa. */
+{ "orl", 0x58050F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* orl<.f> 0,ximm,RC 0101110000000101F111cccccc111110. */
+{ "orl", 0x5C05703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* orl<.f> 0,RB,ximm 01011bbb00000101FBBB111100111110. */
+{ "orl", 0x58050F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* orl<.f><.cc> 0,ximm,RC 0101110011000101F111cccccc0QQQQQ. */
+{ "orl", 0x5CC57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* orl<.f><.cc> RB,RB,ximm 01011bbb11000101FBBB1111000QQQQQ. */
+{ "orl", 0x58C50F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* orl<.f> RA,ximm,u6 0101110001000101F111uuuuuuaaaaaa. */
+{ "orl", 0x5C457000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* orl<.f> 0,ximm,u6 0101110001000101F111uuuuuu111110. */
+{ "orl", 0x5C45703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* orl<.f><.cc> 0,ximm,u6 0101110011000101F111uuuuuu1QQQQQ. */
+{ "orl", 0x5CC57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* orl<.f> RA,limm,RC 0101111000000101F111ccccccaaaaaa. */
+{ "orl", 0x5E057000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* orl<.f> RA,RB,limm 01011bbb00000101FBBB111110aaaaaa. */
+{ "orl", 0x58050F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* orl<.f> 0,limm,RC 0101111000000101F111cccccc111110. */
+{ "orl", 0x5E05703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* orl<.f> 0,RB,limm 01011bbb00000101FBBB111110111110. */
+{ "orl", 0x58050FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* orl<.f><.cc> 0,limm,RC 0101111011000101F111cccccc0QQQQQ. */
+{ "orl", 0x5EC57000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* orl<.f><.cc> RB,RB,limm 01011bbb11000101FBBB1111100QQQQQ. */
+{ "orl", 0x58C50F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* orl<.f> RA,limm,u6 0101111001000101F111uuuuuuaaaaaa. */
+{ "orl", 0x5E457000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* orl<.f> 0,limm,u6 0101111001000101F111uuuuuu111110. */
+{ "orl", 0x5E45703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* orl<.f><.cc> 0,limm,u6 0101111011000101F111uuuuuu1QQQQQ. */
+{ "orl", 0x5EC57020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* orl<.f> 0,ximm,s12 0101110010000101F111ssssssSSSSSS. */
+{ "orl", 0x5C857000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* orl<.f> 0,limm,s12 0101111010000101F111ssssssSSSSSS. */
+{ "orl", 0x5E857000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* orl<.f> RA,ximm,ximm 0101110000000101F111111100aaaaaa. */
+{ "orl", 0x5C057F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* orl<.f> 0,ximm,ximm 0101110000000101F111111100111110. */
+{ "orl", 0x5C057F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* orl<.f><.cc> 0,ximm,ximm 0101110011000101F1111111000QQQQQ. */
+{ "orl", 0x5CC57F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* orl<.f> RA,limm,limm 0101111000000101F111111110aaaaaa. */
+{ "orl", 0x5E057F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* orl<.f> 0,limm,limm 0101111000000101F111111110111110. */
+{ "orl", 0x5E057FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* orl<.f><.cc> 0,limm,limm 0101111011000101F1111111100QQQQQ. */
+{ "orl", 0x5EC57F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* orl_s b,b,c 01111bbbccc10111. */
+{ "orl_s", 0x00007817, 0x0000F81F, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* orl_s h,h,ximm 01110000hhh110HH. */
+{ "orl_s", 0x00007018, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, RH_Sdup, LO32 }, { 0 }},
+
+/* orl_s h,PCL,ximm 01110010hhh110HH. */
+{ "orl_s", 0x00007218, 0x0000FF1C, ARC_OPCODE_ARC64, ARITH, NONE, { RH_S, PCL_S, LO32 }, { 0 }},
+
+/* or_s b,b,c 01111bbbccc00101. */
+{ "or_s", 0x00007805, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* popdl_s b 11000bbb1101BBB1. */
+{ "popdl_s", 0x0000C0D1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
+
+/* popl_s b 11000bbb1100BBB1. */
+{ "popl_s", 0x0000C0C1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
+
+/* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110. */
+{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+
+/* prealloc<.aa> b,s9 00010bbbssssssssSBBB0aa001111110. */
+{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+
+/* prealloc<.aa> b,limm 00100bbbaa1100010BBB111110111110. */
+{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+
+/* prealloc limm,c 00100110RR1100010111CCCCCC111110. */
+{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+
+/* prealloc limm 000101100000000001110RR001111110. */
+{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* prealloc limm,s9 00010110ssssssssS1110RR001111110. */
+{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+
+/* prefetch<.aa> b,c 00100bbbaa1100000BBBCCCCCC111110. */
+{ "prefetch", 0x2030003E, 0xF83F803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+
+/* prefetch<.aa> b,s9 00010bbbssssssssSBBB0aa000111110. */
+{ "prefetch", 0x1000003E, 0xF80009FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+
+/* prefetch<.aa> b,limm 00100bbbaa1100000BBB111110111110. */
+{ "prefetch", 0x20300FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+
+/* prefetch limm,c 00100110RR1100000111CCCCCC111110. */
+{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+
+/* prefetch limm 000101100000000001110RR000111110. */
+{ "prefetch", 0x1600703E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* prefetch limm,s9 00010110ssssssssS1110RR000111110. */
+{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+
+/* prefetchw<.aa> b,c 00100bbbaa1100001BBBCCCCCC111110. */
+{ "prefetchw", 0x2030803E, 0xF83F803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }},
+
+/* prefetchw<.aa> b,s9 00010bbbssssssssSBBB1aa000111110. */
+{ "prefetchw", 0x1000083E, 0xF80009FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }},
+
+/* prefetchw<.aa> b,limm 00100bbbaa1100001BBB111110111110. */
+{ "prefetchw", 0x20308FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }},
+
+/* prefetchw limm,c 00100110RR1100001111CCCCCC111110. */
+{ "prefetchw", 0x2630F03E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }},
+
+/* prefetchw limm 000101100000000001111RR000111110. */
+{ "prefetchw", 0x1600783E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* prefetchw limm,s9 00010110ssssssssS1111RR000111110. */
+{ "prefetchw", 0x1600783E, 0xFF0079FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }},
+
+/* pushdl_s b 11000bbb1111BBB1. */
+{ "pushdl_s", 0x0000C0F1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
+
+/* pushl_s b 11000bbb1110BBB1. */
+{ "pushl_s", 0x0000C0E1, 0x0000F8F1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 }},
+
+/* qmach<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */
+{ "qmach", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* qmach<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110. */
+{ "qmach", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmach<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ. */
+{ "qmach", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* qmach<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA. */
+{ "qmach", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* qmach<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110. */
+{ "qmach", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmach<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ. */
+{ "qmach", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmach<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS. */
+{ "qmach", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmach<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA. */
+{ "qmach", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* qmach<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA. */
+{ "qmach", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* qmach<.f> 0,limm,c 0010111000110100F111CCCCCC111110. */
+{ "qmach", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmach<.f> 0,b,limm 00101bbb00110100FBBB111110111110. */
+{ "qmach", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmach<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ. */
+{ "qmach", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmach<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ. */
+{ "qmach", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmach<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA. */
+{ "qmach", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmach<.f> 0,limm,u6 0010111001110100F111uuuuuu111110. */
+{ "qmach", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmach<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ. */
+{ "qmach", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmach<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS. */
+{ "qmach", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmach<.f> a,limm,limm 0010111000110100F111111110AAAAAA. */
+{ "qmach", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* qmach<.f> 0,limm,limm 0010111000110100F111111110111110. */
+{ "qmach", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmach<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ. */
+{ "qmach", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmachf<.f> a,b,c 00110bbb00110101FBBBCCCCCCAAAAAA. */
+{ "qmachf", 0x30350000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* qmachf<.f> 0,b,c 00110bbb00110101FBBBCCCCCC111110. */
+{ "qmachf", 0x3035003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmachf<.f><.cc> b,b,c 00110bbb11110101FBBBCCCCCC0QQQQQ. */
+{ "qmachf", 0x30F50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* qmachf<.f> a,b,u6 00110bbb01110101FBBBuuuuuuAAAAAA. */
+{ "qmachf", 0x30750000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* qmachf<.f> 0,b,u6 00110bbb01110101FBBBuuuuuu111110. */
+{ "qmachf", 0x3075003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmachf<.f><.cc> b,b,u6 00110bbb11110101FBBBuuuuuu1QQQQQ. */
+{ "qmachf", 0x30F50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmachf<.f> b,b,s12 00110bbb10110101FBBBssssssSSSSSS. */
+{ "qmachf", 0x30B50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmachf<.f> a,limm,c 0011011000110101F111CCCCCCAAAAAA. */
+{ "qmachf", 0x36357000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* qmachf<.f> a,b,limm 00110bbb00110101FBBB111110AAAAAA. */
+{ "qmachf", 0x30350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* qmachf<.f> 0,limm,c 0011011000110101F111CCCCCC111110. */
+{ "qmachf", 0x3635703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmachf<.f> 0,b,limm 00110bbb00110101FBBB111110111110. */
+{ "qmachf", 0x30350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmachf<.f><.cc> b,b,limm 00110bbb11110101FBBB1111100QQQQQ. */
+{ "qmachf", 0x30F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmachf<.f><.cc> 0,limm,c 0011011011110101F111CCCCCC0QQQQQ. */
+{ "qmachf", 0x36F57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmachf<.f> a,limm,u6 0011011001110101F111uuuuuuAAAAAA. */
+{ "qmachf", 0x36757000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmachf<.f> 0,limm,u6 0011011001110101F111uuuuuu111110. */
+{ "qmachf", 0x3675703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmachf<.f><.cc> 0,limm,u6 0011011011110101F111uuuuuu1QQQQQ. */
+{ "qmachf", 0x36F57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmachf<.f> 0,limm,s12 0011011010110101F111ssssssSSSSSS. */
+{ "qmachf", 0x36B57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmachf<.f> a,limm,limm 0011011000110101F111111110AAAAAA. */
+{ "qmachf", 0x36357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* qmachf<.f> 0,limm,limm 0011011000110101F111111110111110. */
+{ "qmachf", 0x36357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmachf<.f><.cc> 0,limm,limm 0011011011110101F1111111100QQQQQ. */
+{ "qmachf", 0x36F57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmachu<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA. */
+{ "qmachu", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* qmachu<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110. */
+{ "qmachu", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmachu<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ. */
+{ "qmachu", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* qmachu<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA. */
+{ "qmachu", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110. */
+{ "qmachu", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ. */
+{ "qmachu", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmachu<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS. */
+{ "qmachu", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmachu<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA. */
+{ "qmachu", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* qmachu<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA. */
+{ "qmachu", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* qmachu<.f> 0,limm,c 0010111000110101F111CCCCCC111110. */
+{ "qmachu", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmachu<.f> 0,b,limm 00101bbb00110101FBBB111110111110. */
+{ "qmachu", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmachu<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ. */
+{ "qmachu", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmachu<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ. */
+{ "qmachu", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmachu<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA. */
+{ "qmachu", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f> 0,limm,u6 0010111001110101F111uuuuuu111110. */
+{ "qmachu", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmachu<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ. */
+{ "qmachu", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmachu<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS. */
+{ "qmachu", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmachu<.f> a,limm,limm 0010111000110101F111111110AAAAAA. */
+{ "qmachu", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* qmachu<.f> 0,limm,limm 0010111000110101F111111110111110. */
+{ "qmachu", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmachu<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ. */
+{ "qmachu", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmpyh<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA. */
+{ "qmpyh", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* qmpyh<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110. */
+{ "qmpyh", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmpyh<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ. */
+{ "qmpyh", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* qmpyh<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA. */
+{ "qmpyh", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110. */
+{ "qmpyh", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ. */
+{ "qmpyh", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyh<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS. */
+{ "qmpyh", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmpyh<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA. */
+{ "qmpyh", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* qmpyh<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA. */
+{ "qmpyh", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* qmpyh<.f> 0,limm,c 0010111000110000F111CCCCCC111110. */
+{ "qmpyh", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmpyh<.f> 0,b,limm 00101bbb00110000FBBB111110111110. */
+{ "qmpyh", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmpyh<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ. */
+{ "qmpyh", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmpyh<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ. */
+{ "qmpyh", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmpyh<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA. */
+{ "qmpyh", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f> 0,limm,u6 0010111001110000F111uuuuuu111110. */
+{ "qmpyh", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyh<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ. */
+{ "qmpyh", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyh<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS. */
+{ "qmpyh", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmpyh<.f> a,limm,limm 0010111000110000F111111110AAAAAA. */
+{ "qmpyh", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyh<.f> 0,limm,limm 0010111000110000F111111110111110. */
+{ "qmpyh", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyh<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ. */
+{ "qmpyh", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmpyhf<.f> a,b,c 00110bbb00110001FBBBCCCCCCAAAAAA. */
+{ "qmpyhf", 0x30310000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* qmpyhf<.f> 0,b,c 00110bbb00110001FBBBCCCCCC111110. */
+{ "qmpyhf", 0x3031003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmpyhf<.f><.cc> b,b,c 00110bbb11110001FBBBCCCCCC0QQQQQ. */
+{ "qmpyhf", 0x30F10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* qmpyhf<.f> a,b,u6 00110bbb01110001FBBBuuuuuuAAAAAA. */
+{ "qmpyhf", 0x30710000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyhf<.f> 0,b,u6 00110bbb01110001FBBBuuuuuu111110. */
+{ "qmpyhf", 0x3071003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyhf<.f><.cc> b,b,u6 00110bbb11110001FBBBuuuuuu1QQQQQ. */
+{ "qmpyhf", 0x30F10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyhf<.f> b,b,s12 00110bbb10110001FBBBssssssSSSSSS. */
+{ "qmpyhf", 0x30B10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmpyhf<.f> a,limm,c 0011011000110001F111CCCCCCAAAAAA. */
+{ "qmpyhf", 0x36317000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* qmpyhf<.f> a,b,limm 00110bbb00110001FBBB111110AAAAAA. */
+{ "qmpyhf", 0x30310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* qmpyhf<.f> 0,limm,c 0011011000110001F111CCCCCC111110. */
+{ "qmpyhf", 0x3631703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmpyhf<.f> 0,b,limm 00110bbb00110001FBBB111110111110. */
+{ "qmpyhf", 0x30310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmpyhf<.f><.cc> b,b,limm 00110bbb11110001FBBB1111100QQQQQ. */
+{ "qmpyhf", 0x30F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmpyhf<.f><.cc> 0,limm,c 0011011011110001F111CCCCCC0QQQQQ. */
+{ "qmpyhf", 0x36F17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmpyhf<.f> a,limm,u6 0011011001110001F111uuuuuuAAAAAA. */
+{ "qmpyhf", 0x36717000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyhf<.f> 0,limm,u6 0011011001110001F111uuuuuu111110. */
+{ "qmpyhf", 0x3671703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyhf<.f><.cc> 0,limm,u6 0011011011110001F111uuuuuu1QQQQQ. */
+{ "qmpyhf", 0x36F17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyhf<.f> 0,limm,s12 0011011010110001F111ssssssSSSSSS. */
+{ "qmpyhf", 0x36B17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmpyhf<.f> a,limm,limm 0011011000110001F111111110AAAAAA. */
+{ "qmpyhf", 0x36317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyhf<.f> 0,limm,limm 0011011000110001F111111110111110. */
+{ "qmpyhf", 0x36317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyhf<.f><.cc> 0,limm,limm 0011011011110001F1111111100QQQQQ. */
+{ "qmpyhf", 0x36F17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* qmpyhu<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA. */
+{ "qmpyhu", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { C_F }},
+
+/* qmpyhu<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110. */
+{ "qmpyhu", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { C_F }},
+
+/* qmpyhu<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ. */
+{ "qmpyhu", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* qmpyhu<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA. */
+{ "qmpyhu", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110. */
+{ "qmpyhu", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ. */
+{ "qmpyhu", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyhu<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS. */
+{ "qmpyhu", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* qmpyhu<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA. */
+{ "qmpyhu", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* qmpyhu<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA. */
+{ "qmpyhu", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* qmpyhu<.f> 0,limm,c 0010111000110001F111CCCCCC111110. */
+{ "qmpyhu", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F }},
+
+/* qmpyhu<.f> 0,b,limm 00101bbb00110001FBBB111110111110. */
+{ "qmpyhu", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { C_F }},
+
+/* qmpyhu<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ. */
+{ "qmpyhu", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* qmpyhu<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ. */
+{ "qmpyhu", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* qmpyhu<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA. */
+{ "qmpyhu", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f> 0,limm,u6 0010111001110001F111uuuuuu111110. */
+{ "qmpyhu", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* qmpyhu<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ. */
+{ "qmpyhu", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* qmpyhu<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS. */
+{ "qmpyhu", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* qmpyhu<.f> a,limm,limm 0010111000110001F111111110AAAAAA. */
+{ "qmpyhu", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyhu<.f> 0,limm,limm 0010111000110001F111111110111110. */
+{ "qmpyhu", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* qmpyhu<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ. */
+{ "qmpyhu", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rcmp b,c 00100bbb000011011BBBCCCCCCRRRRRR. */
+{ "rcmp", 0x200D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* rcmp<.cc> b,c 00100bbb110011011BBBCCCCCC0QQQQQ. */
+{ "rcmp", 0x20CD8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* rcmp b,u6 00100bbb010011011BBBuuuuuuRRRRRR. */
+{ "rcmp", 0x204D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* rcmp<.cc> b,u6 00100bbb110011011BBBuuuuuu1QQQQQ. */
+{ "rcmp", 0x20CD8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* rcmp b,s12 00100bbb100011011BBBssssssSSSSSS. */
+{ "rcmp", 0x208D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* rcmp limm,c 00100110000011011111CCCCCCRRRRRR. */
+{ "rcmp", 0x260DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* rcmp b,limm 00100bbb000011011BBB111110RRRRRR. */
+{ "rcmp", 0x200D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* rcmp<.cc> limm,c 00100110110011011111CCCCCC0QQQQQ. */
+{ "rcmp", 0x26CDF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { C_CC }},
+
+/* rcmp<.cc> b,limm 00100bbb110011011BBB1111100QQQQQ. */
+{ "rcmp", 0x20CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* rcmp limm,u6 00100110010011011111uuuuuuRRRRRR. */
+{ "rcmp", 0x264DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* rcmp<.cc> limm,u6 00100110110011011111uuuuuu1QQQQQ. */
+{ "rcmp", 0x26CDF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* rcmp limm,s12 00100110100011011111ssssssSSSSSS. */
+{ "rcmp", 0x268DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* rcmp limm,limm 00100110000011011111111110RRRRRR. */
+{ "rcmp", 0x260DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* rcmp<.cc> limm,limm 001001101100110111111111100QQQQQ. */
+{ "rcmp", 0x26CDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* rcmpl RB,RC 01011bbb000011011BBBccccccRRRRRR. */
+{ "rcmpl", 0x580D8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* rcmpl<.cc> RB,RC 01011bbb110011011BBBcccccc0QQQQQ. */
+{ "rcmpl", 0x58CD8000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* rcmpl RB,u6 01011bbb010011011BBBuuuuuuRRRRRR. */
+{ "rcmpl", 0x584D8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* rcmpl<.cc> RB,u6 01011bbb110011011BBBuuuuuu1QQQQQ. */
+{ "rcmpl", 0x58CD8020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* rcmpl RB,s12 01011bbb100011011BBBssssssSSSSSS. */
+{ "rcmpl", 0x588D8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* rcmpl ximm,RC 01011100000011011111ccccccRRRRRR. */
+{ "rcmpl", 0x5C0DF000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { XIMM, RC }, { 0 }},
+
+/* rcmpl RB,ximm 01011bbb000011011BBB111100RRRRRR. */
+{ "rcmpl", 0x580D8F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 }},
+
+/* rcmpl<.cc> RB,ximm 01011bbb110011011BBB1111000QQQQQ. */
+{ "rcmpl", 0x58CD8F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC }},
+
+/* rcmpl limm,RC 01011110000011011111ccccccRRRRRR. */
+{ "rcmpl", 0x5E0DF000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, RC }, { 0 }},
+
+/* rcmpl RB,limm 01011bbb000011011BBB111110RRRRRR. */
+{ "rcmpl", 0x580D8F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* rcmpl<.cc> RB,limm 01011bbb110011011BBB1111100QQQQQ. */
+{ "rcmpl", 0x58CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* rcmpl limm,u6 01011110010011011111uuuuuuRRRRRR. */
+{ "rcmpl", 0x5E4DF000, 0xFFFFF000, ARC_OPCODE_ARC64, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* rem<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */
+{ "rem", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* rem<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */
+{ "rem", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
+
+/* rem<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */
+{ "rem", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* rem<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */
+{ "rem", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* rem<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */
+{ "rem", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, RB, RC }, { C_F }},
+
+/* rem<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */
+{ "rem", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* rem<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */
+{ "rem", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* rem<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */
+{ "rem", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* rem<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */
+{ "rem", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* rem<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */
+{ "rem", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* rem<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */
+{ "rem", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* rem<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */
+{ "rem", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* rem<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */
+{ "rem", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* rem<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */
+{ "rem", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* rem<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */
+{ "rem", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* rem<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */
+{ "rem", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* rem<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */
+{ "rem", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* rem<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */
+{ "rem", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* rem<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */
+{ "rem", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* rem<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */
+{ "rem", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* rem<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */
+{ "rem", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* rem<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */
+{ "rem", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* rem<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */
+{ "rem", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* rem<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */
+{ "rem", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* rem<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */
+{ "rem", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* rem<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */
+{ "rem", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* rem<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */
+{ "rem", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* rem<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */
+{ "rem", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rem<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */
+{ "rem", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rem<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */
+{ "rem", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* rem<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */
+{ "rem", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rem<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */
+{ "rem", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rem<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */
+{ "rem", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* rem<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */
+{ "rem", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* rem<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */
+{ "rem", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* rem<.f> 0,limm,limm 0010111000001000F111111110111110. */
+{ "rem", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* rem<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */
+{ "rem", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rem<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */
+{ "rem", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* rem<.f> 0,limm,limm 0010111000001000F111111110111110. */
+{ "rem", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* rem<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */
+{ "rem", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* reml<.f> RA,RB,RC 01011bbb00101000FBBBccccccaaaaaa. */
+{ "reml", 0x58280000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* reml<.f> 0,RB,RC 01011bbb00101000FBBBcccccc111110. */
+{ "reml", 0x5828003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* reml<.f><.cc> RB,RB,RC 01011bbb11101000FBBBcccccc0QQQQQ. */
+{ "reml", 0x58E80000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* reml<.f> RA,RB,u6 01011bbb01101000FBBBuuuuuuaaaaaa. */
+{ "reml", 0x58680000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* reml<.f> 0,RB,u6 01011bbb01101000FBBBuuuuuu111110. */
+{ "reml", 0x5868003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* reml<.f><.cc> RB,RB,u6 01011bbb11101000FBBBuuuuuu1QQQQQ. */
+{ "reml", 0x58E80020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* reml<.f> RB,RB,s12 01011bbb10101000FBBBssssssSSSSSS. */
+{ "reml", 0x58A80000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* reml<.f> RA,ximm,RC 0101110000101000F111ccccccaaaaaa. */
+{ "reml", 0x5C287000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* reml<.f> RA,RB,ximm 01011bbb00101000FBBB111100aaaaaa. */
+{ "reml", 0x58280F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* reml<.f> 0,ximm,RC 0101110000101000F111cccccc111110. */
+{ "reml", 0x5C28703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* reml<.f> 0,RB,ximm 01011bbb00101000FBBB111100111110. */
+{ "reml", 0x58280F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* reml<.f><.cc> 0,ximm,RC 0101110011101000F111cccccc0QQQQQ. */
+{ "reml", 0x5CE87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* reml<.f><.cc> RB,RB,ximm 01011bbb11101000FBBB1111000QQQQQ. */
+{ "reml", 0x58E80F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* reml<.f> RA,ximm,u6 0101110001101000F111uuuuuuaaaaaa. */
+{ "reml", 0x5C687000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* reml<.f> 0,ximm,u6 0101110001101000F111uuuuuu111110. */
+{ "reml", 0x5C68703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* reml<.f><.cc> 0,ximm,u6 0101110011101000F111uuuuuu1QQQQQ. */
+{ "reml", 0x5CE87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* reml<.f> RA,limm,RC 0101111000101000F111ccccccaaaaaa. */
+{ "reml", 0x5E287000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* reml<.f> RA,RB,limm 01011bbb00101000FBBB111110aaaaaa. */
+{ "reml", 0x58280F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* reml<.f> 0,limm,RC 0101111000101000F111cccccc111110. */
+{ "reml", 0x5E28703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* reml<.f> 0,RB,limm 01011bbb00101000FBBB111110111110. */
+{ "reml", 0x58280FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* reml<.f><.cc> 0,limm,RC 0101111011101000F111cccccc0QQQQQ. */
+{ "reml", 0x5EE87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* reml<.f><.cc> RB,RB,limm 01011bbb11101000FBBB1111100QQQQQ. */
+{ "reml", 0x58E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* reml<.f> RA,limm,u6 0101111001101000F111uuuuuuaaaaaa. */
+{ "reml", 0x5E687000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* reml<.f> 0,limm,u6 0101111001101000F111uuuuuu111110. */
+{ "reml", 0x5E68703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* reml<.f><.cc> 0,limm,u6 0101111011101000F111uuuuuu1QQQQQ. */
+{ "reml", 0x5EE87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* reml<.f> 0,ximm,s12 0101110010101000F111ssssssSSSSSS. */
+{ "reml", 0x5CA87000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* reml<.f> 0,limm,s12 0101111010101000F111ssssssSSSSSS. */
+{ "reml", 0x5EA87000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* reml<.f> RA,ximm,ximm 0101110000101000F111111100aaaaaa. */
+{ "reml", 0x5C287F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* reml<.f> 0,ximm,ximm 0101110000101000F111111100111110. */
+{ "reml", 0x5C287F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* reml<.f><.cc> 0,ximm,ximm 0101110011101000F1111111000QQQQQ. */
+{ "reml", 0x5CE87F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* reml<.f> RA,limm,limm 0101111000101000F111111110aaaaaa. */
+{ "reml", 0x5E287F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* reml<.f> 0,limm,limm 0101111000101000F111111110111110. */
+{ "reml", 0x5E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* reml<.f><.cc> 0,limm,limm 0101111011101000F1111111100QQQQQ. */
+{ "reml", 0x5EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* remu<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */
+{ "remu", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* remu<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */
+{ "remu", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, RC }, { C_F }},
+
+/* remu<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */
+{ "remu", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* remu<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */
+{ "remu", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, RB, RC }, { C_F }},
+
+/* remu<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */
+{ "remu", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, RB, RC }, { C_F }},
+
+/* remu<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */
+{ "remu", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, RC }, { C_F, C_CC }},
+
+/* remu<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */
+{ "remu", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* remu<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */
+{ "remu", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* remu<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */
+{ "remu", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* remu<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */
+{ "remu", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, RB, UIMM6_20 }, { C_F }},
+
+/* remu<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */
+{ "remu", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* remu<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */
+{ "remu", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* remu<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */
+{ "remu", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* remu<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */
+{ "remu", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, SIMM12_20 }, { C_F }},
+
+/* remu<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */
+{ "remu", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* remu<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */
+{ "remu", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* remu<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */
+{ "remu", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* remu<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */
+{ "remu", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* remu<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */
+{ "remu", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* remu<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */
+{ "remu", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* remu<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */
+{ "remu", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, LIMM, RC }, { C_F }},
+
+/* remu<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */
+{ "remu", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, RB, LIMM }, { C_F }},
+
+/* remu<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */
+{ "remu", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, RC }, { C_F }},
+
+/* remu<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */
+{ "remu", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, RB, LIMM }, { C_F }},
+
+/* remu<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */
+{ "remu", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RB_CHK, RBdup, LIMM }, { C_F, C_CC }},
+
+/* remu<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */
+{ "remu", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* remu<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */
+{ "remu", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* remu<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */
+{ "remu", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* remu<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */
+{ "remu", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* remu<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */
+{ "remu", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, LIMM, UIMM6_20 }, { C_F }},
+
+/* remu<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */
+{ "remu", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* remu<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */
+{ "remu", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* remu<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */
+{ "remu", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* remu<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */
+{ "remu", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* remu<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */
+{ "remu", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* remu<.f> 0,limm,limm 0010111000001001F111111110111110. */
+{ "remu", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* remu<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */
+{ "remu", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DIVREM, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* remu<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */
+{ "remu", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { RA_CHK, LIMM, LIMMdup }, { C_F }},
+
+/* remu<.f> 0,limm,limm 0010111000001001F111111110111110. */
+{ "remu", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* remu<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */
+{ "remu", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* remul<.f> RA,RB,RC 01011bbb00101001FBBBccccccaaaaaa. */
+{ "remul", 0x58290000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* remul<.f> 0,RB,RC 01011bbb00101001FBBBcccccc111110. */
+{ "remul", 0x5829003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* remul<.f><.cc> RB,RB,RC 01011bbb11101001FBBBcccccc0QQQQQ. */
+{ "remul", 0x58E90000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* remul<.f> RA,RB,u6 01011bbb01101001FBBBuuuuuuaaaaaa. */
+{ "remul", 0x58690000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* remul<.f> 0,RB,u6 01011bbb01101001FBBBuuuuuu111110. */
+{ "remul", 0x5869003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* remul<.f><.cc> RB,RB,u6 01011bbb11101001FBBBuuuuuu1QQQQQ. */
+{ "remul", 0x58E90020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* remul<.f> RB,RB,s12 01011bbb10101001FBBBssssssSSSSSS. */
+{ "remul", 0x58A90000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* remul<.f> RA,ximm,RC 0101110000101001F111ccccccaaaaaa. */
+{ "remul", 0x5C297000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* remul<.f> RA,RB,ximm 01011bbb00101001FBBB111100aaaaaa. */
+{ "remul", 0x58290F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* remul<.f> 0,ximm,RC 0101110000101001F111cccccc111110. */
+{ "remul", 0x5C29703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* remul<.f> 0,RB,ximm 01011bbb00101001FBBB111100111110. */
+{ "remul", 0x58290F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* remul<.f><.cc> 0,ximm,RC 0101110011101001F111cccccc0QQQQQ. */
+{ "remul", 0x5CE97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* remul<.f><.cc> RB,RB,ximm 01011bbb11101001FBBB1111000QQQQQ. */
+{ "remul", 0x58E90F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* remul<.f> RA,ximm,u6 0101110001101001F111uuuuuuaaaaaa. */
+{ "remul", 0x5C697000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* remul<.f> 0,ximm,u6 0101110001101001F111uuuuuu111110. */
+{ "remul", 0x5C69703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* remul<.f><.cc> 0,ximm,u6 0101110011101001F111uuuuuu1QQQQQ. */
+{ "remul", 0x5CE97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* remul<.f> RA,limm,RC 0101111000101001F111ccccccaaaaaa. */
+{ "remul", 0x5E297000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* remul<.f> RA,RB,limm 01011bbb00101001FBBB111110aaaaaa. */
+{ "remul", 0x58290F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* remul<.f> 0,limm,RC 0101111000101001F111cccccc111110. */
+{ "remul", 0x5E29703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* remul<.f> 0,RB,limm 01011bbb00101001FBBB111110111110. */
+{ "remul", 0x58290FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* remul<.f><.cc> 0,limm,RC 0101111011101001F111cccccc0QQQQQ. */
+{ "remul", 0x5EE97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* remul<.f><.cc> RB,RB,limm 01011bbb11101001FBBB1111100QQQQQ. */
+{ "remul", 0x58E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* remul<.f> RA,limm,u6 0101111001101001F111uuuuuuaaaaaa. */
+{ "remul", 0x5E697000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* remul<.f> 0,limm,u6 0101111001101001F111uuuuuu111110. */
+{ "remul", 0x5E69703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* remul<.f><.cc> 0,limm,u6 0101111011101001F111uuuuuu1QQQQQ. */
+{ "remul", 0x5EE97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* remul<.f> 0,ximm,s12 0101110010101001F111ssssssSSSSSS. */
+{ "remul", 0x5CA97000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* remul<.f> 0,limm,s12 0101111010101001F111ssssssSSSSSS. */
+{ "remul", 0x5EA97000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* remul<.f> RA,ximm,ximm 0101110000101001F111111100aaaaaa. */
+{ "remul", 0x5C297F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* remul<.f> 0,ximm,ximm 0101110000101001F111111100111110. */
+{ "remul", 0x5C297F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* remul<.f><.cc> 0,ximm,ximm 0101110011101001F1111111000QQQQQ. */
+{ "remul", 0x5CE97F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* remul<.f> RA,limm,limm 0101111000101001F111111110aaaaaa. */
+{ "remul", 0x5E297F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* remul<.f> 0,limm,limm 0101111000101001F111111110111110. */
+{ "remul", 0x5E297FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* remul<.f><.cc> 0,limm,limm 0101111011101001F1111111100QQQQQ. */
+{ "remul", 0x5EE97F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rlc<.f> b,c 00100bbb00101111FBBBCCCCCC001011. */
+{ "rlc", 0x202F000B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* rlc<.f> 0,c 0010011000101111F111CCCCCC001011. */
+{ "rlc", 0x262F700B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* rlc<.f> b,u6 00100bbb01101111FBBBuuuuuu001011. */
+{ "rlc", 0x206F000B, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rlc<.f> 0,u6 0010011001101111F111uuuuuu001011. */
+{ "rlc", 0x266F700B, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rlc<.f> b,limm 00100bbb00101111FBBB111110001011. */
+{ "rlc", 0x202F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* rlc<.f> 0,limm 0010011000101111F111111110001011. */
+{ "rlc", 0x262F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* rndh<.f> b,c 00101bbb00101111FBBBCCCCCC000011. */
+{ "rndh", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { C_F }},
+
+/* rndh<.f> 0,c 0010111000101111F111CCCCCC000011. */
+{ "rndh", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* rndh<.f> b,u6 00101bbb01101111FBBBuuuuuu000011. */
+{ "rndh", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { C_F }},
+
+/* rndh<.f> 0,u6 0010111001101111F111uuuuuu000011. */
+{ "rndh", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rndh<.f> b,limm 00101bbb00101111FBBB111110000011. */
+{ "rndh", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { C_F }},
+
+/* rndh<.f> 0,limm 0010111000101111F111111110000011. */
+{ "rndh", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* rol<.f> b,c 00100bbb00101111FBBBCCCCCC001101. */
+{ "rol", 0x202F000D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* rol<.f> 0,c 0010011000101111F111CCCCCC001101. */
+{ "rol", 0x262F700D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* rol<.f> b,u6 00100bbb01101111FBBBuuuuuu001101. */
+{ "rol", 0x206F000D, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rol<.f> 0,u6 0010011001101111F111uuuuuu001101. */
+{ "rol", 0x266F700D, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rol<.f> b,limm 00100bbb00101111FBBB111110001101. */
+{ "rol", 0x202F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* rol<.f> 0,limm 0010011000101111F111111110001101. */
+{ "rol", 0x262F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* rol8<.f> b,c 00101bbb00101111FBBBCCCCCC010000. */
+{ "rol8", 0x282F0010, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, RC }, { C_F }},
+
+/* rol8<.f> 0,c 0010111000101111F111CCCCCC010000. */
+{ "rol8", 0x2E2F7010, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, RC }, { C_F }},
+
+/* rol8<.f> b,u6 00101bbb01101111FBBBuuuuuu010000. */
+{ "rol8", 0x286F0010, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* rol8<.f> 0,u6 0010111001101111F111uuuuuu010000. */
+{ "rol8", 0x2E6F7010, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* rol8<.f> b,limm 00101bbb00101111FBBB111110010000. */
+{ "rol8", 0x282F0F90, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, LIMM }, { C_F }},
+
+/* rol8<.f> 0,limm 0010111000101111F111111110010000. */
+{ "rol8", 0x2E2F7F90, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* ror<.f> b,c 00100bbb00101111FBBBCCCCCC000011. */
+{ "ror", 0x202F0003, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* ror<.f> 0,c 0010011000101111F111CCCCCC000011. */
+{ "ror", 0x262F7003, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* ror<.f> a,b,c 00101bbb00000011FBBBCCCCCCAAAAAA. */
+{ "ror", 0x28030000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* ror<.f> 0,b,c 00101bbb00000011FBBBCCCCCC111110. */
+{ "ror", 0x2803003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* ror<.f><.cc> b,b,c 00101bbb11000011FBBBCCCCCC0QQQQQ. */
+{ "ror", 0x28C30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* ror<.f> b,u6 00100bbb01101111FBBBuuuuuu000011. */
+{ "ror", 0x206F0003, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* ror<.f> 0,u6 0010011001101111F111uuuuuu000011. */
+{ "ror", 0x266F7003, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* ror<.f> a,b,u6 00101bbb01000011FBBBuuuuuuAAAAAA. */
+{ "ror", 0x28430000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* ror<.f> 0,b,u6 00101bbb01000011FBBBuuuuuu111110. */
+{ "ror", 0x2843003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* ror<.f><.cc> b,b,u6 00101bbb11000011FBBBuuuuuu1QQQQQ. */
+{ "ror", 0x28C30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* ror<.f> b,b,s12 00101bbb10000011FBBBssssssSSSSSS. */
+{ "ror", 0x28830000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* ror<.f> b,limm 00100bbb00101111FBBB111110000011. */
+{ "ror", 0x202F0F83, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* ror<.f> 0,limm 0010011000101111F111111110000011. */
+{ "ror", 0x262F7F83, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* ror<.f> a,limm,c 0010111000000011F111CCCCCCAAAAAA. */
+{ "ror", 0x2E037000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* ror<.f> a,b,limm 00101bbb00000011FBBB111110AAAAAA. */
+{ "ror", 0x28030F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* ror<.f> 0,limm,c 0010111000000011F111CCCCCC111110. */
+{ "ror", 0x2E03703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* ror<.f> 0,b,limm 00101bbb00000011FBBB111110111110. */
+{ "ror", 0x28030FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* ror<.f><.cc> b,b,limm 00101bbb11000011FBBB1111100QQQQQ. */
+{ "ror", 0x28C30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* ror<.f><.cc> 0,limm,c 0010111011000011F111CCCCCC0QQQQQ. */
+{ "ror", 0x2EC37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* ror<.f> a,limm,u6 0010111001000011F111uuuuuuAAAAAA. */
+{ "ror", 0x2E437000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* ror<.f> 0,limm,u6 0010111001000011F111uuuuuu111110. */
+{ "ror", 0x2E43703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* ror<.f><.cc> 0,limm,u6 0010111011000011F111uuuuuu1QQQQQ. */
+{ "ror", 0x2EC37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* ror<.f> 0,limm,s12 0010111010000011F111ssssssSSSSSS. */
+{ "ror", 0x2E837000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* ror<.f> a,limm,limm 0010111000000011F111111110AAAAAA. */
+{ "ror", 0x2E037F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* ror<.f> 0,limm,limm 0010111000000011F111111110111110. */
+{ "ror", 0x2E037FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* ror<.f><.cc> 0,limm,limm 0010111011000011F1111111100QQQQQ. */
+{ "ror", 0x2EC37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* ror8<.f> b,c 00101bbb00101111FBBBCCCCCC010001. */
+{ "ror8", 0x282F0011, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, RC }, { C_F }},
+
+/* ror8<.f> 0,c 0010111000101111F111CCCCCC010001. */
+{ "ror8", 0x2E2F7011, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, RC }, { C_F }},
+
+/* ror8<.f> b,u6 00101bbb01101111FBBBuuuuuu010001. */
+{ "ror8", 0x286F0011, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, UIMM6_20 }, { C_F }},
+
+/* ror8<.f> 0,u6 0010111001101111F111uuuuuu010001. */
+{ "ror8", 0x2E6F7011, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, UIMM6_20 }, { C_F }},
+
+/* ror8<.f> b,limm 00101bbb00101111FBBB111110010001. */
+{ "ror8", 0x282F0F91, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { RB, LIMM }, { C_F }},
+
+/* ror8<.f> 0,limm 0010111000101111F111111110010001. */
+{ "ror8", 0x2E2F7F91, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, SHFT1, { ZA, LIMM }, { C_F }},
+
+/* rrc<.f> b,c 00100bbb00101111FBBBCCCCCC000100. */
+{ "rrc", 0x202F0004, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_F }},
+
+/* rrc<.f> 0,c 0010011000101111F111CCCCCC000100. */
+{ "rrc", 0x262F7004, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RC }, { C_F }},
+
+/* rrc<.f> b,u6 00100bbb01101111FBBBuuuuuu000100. */
+{ "rrc", 0x206F0004, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* rrc<.f> 0,u6 0010011001101111F111uuuuuu000100. */
+{ "rrc", 0x266F7004, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* rrc<.f> b,limm 00100bbb00101111FBBB111110000100. */
+{ "rrc", 0x202F0F84, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_F }},
+
+/* rrc<.f> 0,limm 0010011000101111F111111110000100. */
+{ "rrc", 0x262F7F84, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM }, { C_F }},
+
+/* rsub<.f> a,b,c 00100bbb00001110FBBBCCCCCCAAAAAA. */
+{ "rsub", 0x200E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* rsub<.f> 0,b,c 00100bbb00001110FBBBCCCCCC111110. */
+{ "rsub", 0x200E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* rsub<.f><.cc> b,b,c 00100bbb11001110FBBBCCCCCC0QQQQQ. */
+{ "rsub", 0x20CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* rsub<.f> a,b,u6 00100bbb01001110FBBBuuuuuuAAAAAA. */
+{ "rsub", 0x204E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* rsub<.f> 0,b,u6 00100bbb01001110FBBBuuuuuu111110. */
+{ "rsub", 0x204E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* rsub<.f><.cc> b,b,u6 00100bbb11001110FBBBuuuuuu1QQQQQ. */
+{ "rsub", 0x20CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsub<.f> b,b,s12 00100bbb10001110FBBBssssssSSSSSS. */
+{ "rsub", 0x208E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* rsub<.f> a,limm,c 0010011000001110F111CCCCCCAAAAAA. */
+{ "rsub", 0x260E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* rsub<.f> a,b,limm 00100bbb00001110FBBB111110AAAAAA. */
+{ "rsub", 0x200E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* rsub<.f> 0,limm,c 0010011000001110F111CCCCCC111110. */
+{ "rsub", 0x260E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* rsub<.f> 0,b,limm 00100bbb00001110FBBB111110111110. */
+{ "rsub", 0x200E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* rsub<.f><.cc> b,b,limm 00100bbb11001110FBBB1111100QQQQQ. */
+{ "rsub", 0x20CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* rsub<.f><.cc> 0,limm,c 0010011011001110F111CCCCCC0QQQQQ. */
+{ "rsub", 0x26CE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* rsub<.f> a,limm,u6 0010011001001110F111uuuuuuAAAAAA. */
+{ "rsub", 0x264E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rsub<.f> 0,limm,u6 0010011001001110F111uuuuuu111110. */
+{ "rsub", 0x264E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rsub<.f><.cc> 0,limm,u6 0010011011001110F111uuuuuu1QQQQQ. */
+{ "rsub", 0x26CE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsub<.f> 0,limm,s12 0010011010001110F111ssssssSSSSSS. */
+{ "rsub", 0x268E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* rsub<.f> a,limm,limm 0010011000001110F111111110AAAAAA. */
+{ "rsub", 0x260E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* rsub<.f> 0,limm,limm 0010011000001110F111111110111110. */
+{ "rsub", 0x260E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* rsub<.f><.cc> 0,limm,limm 0010011011001110F1111111100QQQQQ. */
+{ "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,RB,RC 01011bbb00001110FBBBccccccaaaaaa. */
+{ "rsubl", 0x580E0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* rsubl<.f> 0,RB,RC 01011bbb00001110FBBBcccccc111110. */
+{ "rsubl", 0x580E003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* rsubl<.f><.cc> RB,RB,RC 01011bbb11001110FBBBcccccc0QQQQQ. */
+{ "rsubl", 0x58CE0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,RB,u6 01011bbb01001110FBBBuuuuuuaaaaaa. */
+{ "rsubl", 0x584E0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f> 0,RB,u6 01011bbb01001110FBBBuuuuuu111110. */
+{ "rsubl", 0x584E003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f><.cc> RB,RB,u6 01011bbb11001110FBBBuuuuuu1QQQQQ. */
+{ "rsubl", 0x58CE0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsubl<.f> RB,RB,s12 01011bbb10001110FBBBssssssSSSSSS. */
+{ "rsubl", 0x588E0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* rsubl<.f> RA,ximm,RC 0101110000001110F111ccccccaaaaaa. */
+{ "rsubl", 0x5C0E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* rsubl<.f> RA,RB,ximm 01011bbb00001110FBBB111100aaaaaa. */
+{ "rsubl", 0x580E0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* rsubl<.f> 0,ximm,RC 0101110000001110F111cccccc111110. */
+{ "rsubl", 0x5C0E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* rsubl<.f> 0,RB,ximm 01011bbb00001110FBBB111100111110. */
+{ "rsubl", 0x580E0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* rsubl<.f><.cc> 0,ximm,RC 0101110011001110F111cccccc0QQQQQ. */
+{ "rsubl", 0x5CCE7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* rsubl<.f><.cc> RB,RB,ximm 01011bbb11001110FBBB1111000QQQQQ. */
+{ "rsubl", 0x58CE0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,ximm,u6 0101110001001110F111uuuuuuaaaaaa. */
+{ "rsubl", 0x5C4E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f> 0,ximm,u6 0101110001001110F111uuuuuu111110. */
+{ "rsubl", 0x5C4E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f><.cc> 0,ximm,u6 0101110011001110F111uuuuuu1QQQQQ. */
+{ "rsubl", 0x5CCE7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,limm,RC 0101111000001110F111ccccccaaaaaa. */
+{ "rsubl", 0x5E0E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* rsubl<.f> RA,RB,limm 01011bbb00001110FBBB111110aaaaaa. */
+{ "rsubl", 0x580E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* rsubl<.f> 0,limm,RC 0101111000001110F111cccccc111110. */
+{ "rsubl", 0x5E0E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* rsubl<.f> 0,RB,limm 01011bbb00001110FBBB111110111110. */
+{ "rsubl", 0x580E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* rsubl<.f><.cc> 0,limm,RC 0101111011001110F111cccccc0QQQQQ. */
+{ "rsubl", 0x5ECE7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* rsubl<.f><.cc> RB,RB,limm 01011bbb11001110FBBB1111100QQQQQ. */
+{ "rsubl", 0x58CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,limm,u6 0101111001001110F111uuuuuuaaaaaa. */
+{ "rsubl", 0x5E4E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f> 0,limm,u6 0101111001001110F111uuuuuu111110. */
+{ "rsubl", 0x5E4E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* rsubl<.f><.cc> 0,limm,u6 0101111011001110F111uuuuuu1QQQQQ. */
+{ "rsubl", 0x5ECE7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* rsubl<.f> 0,ximm,s12 0101110010001110F111ssssssSSSSSS. */
+{ "rsubl", 0x5C8E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* rsubl<.f> 0,limm,s12 0101111010001110F111ssssssSSSSSS. */
+{ "rsubl", 0x5E8E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* rsubl<.f> RA,ximm,ximm 0101110000001110F111111100aaaaaa. */
+{ "rsubl", 0x5C0E7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* rsubl<.f> 0,ximm,ximm 0101110000001110F111111100111110. */
+{ "rsubl", 0x5C0E7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* rsubl<.f><.cc> 0,ximm,ximm 0101110011001110F1111111000QQQQQ. */
+{ "rsubl", 0x5CCE7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* rsubl<.f> RA,limm,limm 0101111000001110F111111110aaaaaa. */
+{ "rsubl", 0x5E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* rsubl<.f> 0,limm,limm 0101111000001110F111111110111110. */
+{ "rsubl", 0x5E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* rsubl<.f><.cc> 0,limm,limm 0101111011001110F1111111100QQQQQ. */
+{ "rsubl", 0x5ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* rtie 00100100011011110000000000111111. */
+{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* satf<.f> b,c 00101bbb00101111FBBBCCCCCC011010. */
+{ "satf", 0x282F001A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { C_F }},
+
+/* satf<.f> 0,c 0010111000101111F111CCCCCC011010. */
+{ "satf", 0x2E2F701A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* satf<.f> b,u6 00101bbb01101111FBBBuuuuuu011010. */
+{ "satf", 0x286F001A, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { C_F }},
+
+/* satf<.f> 0,u6 0010111001101111F111uuuuuu011010. */
+{ "satf", 0x2E6F701A, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* satf<.f> b,limm 00101bbb00101111FBBB111110011010. */
+{ "satf", 0x282F0F9A, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { C_F }},
+
+/* satf<.f> 0,limm 0010111000101111F111111110011010. */
+{ "satf", 0x2E2F7F9A, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* sath<.f> b,c 00101bbb00101111FBBBCCCCCC000010. */
+{ "sath", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { C_F }},
+
+/* sath<.f> 0,c 0010111000101111F111CCCCCC000010. */
+{ "sath", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* sath<.f> b,u6 00101bbb01101111FBBBuuuuuu000010. */
+{ "sath", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { C_F }},
+
+/* sath<.f> 0,u6 0010111001101111F111uuuuuu000010. */
+{ "sath", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sath<.f> b,limm 00101bbb00101111FBBB111110000010. */
+{ "sath", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { C_F }},
+
+/* sath<.f> 0,limm 0010111000101111F111111110000010. */
+{ "sath", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* sbc<.f> a,b,c 00100bbb00000011FBBBCCCCCCAAAAAA. */
+{ "sbc", 0x20030000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sbc<.f> 0,b,c 00100bbb00000011FBBBCCCCCC111110. */
+{ "sbc", 0x2003003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sbc<.f><.cc> b,b,c 00100bbb11000011FBBBCCCCCC0QQQQQ. */
+{ "sbc", 0x20C30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sbc<.f> a,b,u6 00100bbb01000011FBBBuuuuuuAAAAAA. */
+{ "sbc", 0x20430000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sbc<.f> 0,b,u6 00100bbb01000011FBBBuuuuuu111110. */
+{ "sbc", 0x2043003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sbc<.f><.cc> b,b,u6 00100bbb11000011FBBBuuuuuu1QQQQQ. */
+{ "sbc", 0x20C30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbc<.f> b,b,s12 00100bbb10000011FBBBssssssSSSSSS. */
+{ "sbc", 0x20830000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sbc<.f> a,limm,c 0010011000000011F111CCCCCCAAAAAA. */
+{ "sbc", 0x26037000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sbc<.f> a,b,limm 00100bbb00000011FBBB111110AAAAAA. */
+{ "sbc", 0x20030F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sbc<.f> 0,limm,c 0010011000000011F111CCCCCC111110. */
+{ "sbc", 0x2603703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sbc<.f> 0,b,limm 00100bbb00000011FBBB111110111110. */
+{ "sbc", 0x20030FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sbc<.f><.cc> b,b,limm 00100bbb11000011FBBB1111100QQQQQ. */
+{ "sbc", 0x20C30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sbc<.f><.cc> 0,limm,c 0010011011000011F111CCCCCC0QQQQQ. */
+{ "sbc", 0x26C37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sbc<.f> a,limm,u6 0010011001000011F111uuuuuuAAAAAA. */
+{ "sbc", 0x26437000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbc<.f> 0,limm,u6 0010011001000011F111uuuuuu111110. */
+{ "sbc", 0x2643703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbc<.f><.cc> 0,limm,u6 0010011011000011F111uuuuuu1QQQQQ. */
+{ "sbc", 0x26C37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbc<.f> 0,limm,s12 0010011010000011F111ssssssSSSSSS. */
+{ "sbc", 0x26837000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sbc<.f> a,limm,limm 0010011000000011F111111110AAAAAA. */
+{ "sbc", 0x26037F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sbc<.f> 0,limm,limm 0010011000000011F111111110111110. */
+{ "sbc", 0x26037FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sbc<.f><.cc> 0,limm,limm 0010011011000011F1111111100QQQQQ. */
+{ "sbc", 0x26C37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,RB,RC 01011bbb00000011FBBBccccccaaaaaa. */
+{ "sbcl", 0x58030000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sbcl<.f> 0,RB,RC 01011bbb00000011FBBBcccccc111110. */
+{ "sbcl", 0x5803003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sbcl<.f><.cc> RB,RB,RC 01011bbb11000011FBBBcccccc0QQQQQ. */
+{ "sbcl", 0x58C30000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,RB,u6 01011bbb01000011FBBBuuuuuuaaaaaa. */
+{ "sbcl", 0x58430000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f> 0,RB,u6 01011bbb01000011FBBBuuuuuu111110. */
+{ "sbcl", 0x5843003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f><.cc> RB,RB,u6 01011bbb11000011FBBBuuuuuu1QQQQQ. */
+{ "sbcl", 0x58C30020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbcl<.f> RB,RB,s12 01011bbb10000011FBBBssssssSSSSSS. */
+{ "sbcl", 0x58830000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sbcl<.f> RA,ximm,RC 0101110000000011F111ccccccaaaaaa. */
+{ "sbcl", 0x5C037000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* sbcl<.f> RA,RB,ximm 01011bbb00000011FBBB111100aaaaaa. */
+{ "sbcl", 0x58030F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* sbcl<.f> 0,ximm,RC 0101110000000011F111cccccc111110. */
+{ "sbcl", 0x5C03703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* sbcl<.f> 0,RB,ximm 01011bbb00000011FBBB111100111110. */
+{ "sbcl", 0x58030F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* sbcl<.f><.cc> 0,ximm,RC 0101110011000011F111cccccc0QQQQQ. */
+{ "sbcl", 0x5CC37000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* sbcl<.f><.cc> RB,RB,ximm 01011bbb11000011FBBB1111000QQQQQ. */
+{ "sbcl", 0x58C30F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,ximm,u6 0101110001000011F111uuuuuuaaaaaa. */
+{ "sbcl", 0x5C437000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f> 0,ximm,u6 0101110001000011F111uuuuuu111110. */
+{ "sbcl", 0x5C43703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f><.cc> 0,ximm,u6 0101110011000011F111uuuuuu1QQQQQ. */
+{ "sbcl", 0x5CC37020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,limm,RC 0101111000000011F111ccccccaaaaaa. */
+{ "sbcl", 0x5E037000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sbcl<.f> RA,RB,limm 01011bbb00000011FBBB111110aaaaaa. */
+{ "sbcl", 0x58030F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sbcl<.f> 0,limm,RC 0101111000000011F111cccccc111110. */
+{ "sbcl", 0x5E03703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sbcl<.f> 0,RB,limm 01011bbb00000011FBBB111110111110. */
+{ "sbcl", 0x58030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sbcl<.f><.cc> 0,limm,RC 0101111011000011F111cccccc0QQQQQ. */
+{ "sbcl", 0x5EC37000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sbcl<.f><.cc> RB,RB,limm 01011bbb11000011FBBB1111100QQQQQ. */
+{ "sbcl", 0x58C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,limm,u6 0101111001000011F111uuuuuuaaaaaa. */
+{ "sbcl", 0x5E437000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f> 0,limm,u6 0101111001000011F111uuuuuu111110. */
+{ "sbcl", 0x5E43703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbcl<.f><.cc> 0,limm,u6 0101111011000011F111uuuuuu1QQQQQ. */
+{ "sbcl", 0x5EC37020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbcl<.f> 0,ximm,s12 0101110010000011F111ssssssSSSSSS. */
+{ "sbcl", 0x5C837000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* sbcl<.f> 0,limm,s12 0101111010000011F111ssssssSSSSSS. */
+{ "sbcl", 0x5E837000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sbcl<.f> RA,ximm,ximm 0101110000000011F111111100aaaaaa. */
+{ "sbcl", 0x5C037F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* sbcl<.f> 0,ximm,ximm 0101110000000011F111111100111110. */
+{ "sbcl", 0x5C037F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* sbcl<.f><.cc> 0,ximm,ximm 0101110011000011F1111111000QQQQQ. */
+{ "sbcl", 0x5CC37F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* sbcl<.f> RA,limm,limm 0101111000000011F111111110aaaaaa. */
+{ "sbcl", 0x5E037F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sbcl<.f> 0,limm,limm 0101111000000011F111111110111110. */
+{ "sbcl", 0x5E037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sbcl<.f><.cc> 0,limm,limm 0101111011000011F1111111100QQQQQ. */
+{ "sbcl", 0x5EC37F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sbcs<.f> a,b,c 00101bbb00100111FBBBCCCCCCAAAAAA. */
+{ "sbcs", 0x28270000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sbcs<.f> 0,b,c 00101bbb00100111FBBBCCCCCC111110. */
+{ "sbcs", 0x2827003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sbcs<.f><.cc> b,b,c 00101bbb11100111FBBBCCCCCC0QQQQQ. */
+{ "sbcs", 0x28E70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sbcs<.f> a,b,u6 00101bbb01100111FBBBuuuuuuAAAAAA. */
+{ "sbcs", 0x28670000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sbcs<.f> 0,b,u6 00101bbb01100111FBBBuuuuuu111110. */
+{ "sbcs", 0x2867003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sbcs<.f><.cc> b,b,u6 00101bbb11100111FBBBuuuuuu1QQQQQ. */
+{ "sbcs", 0x28E70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbcs<.f> b,b,s12 00101bbb10100111FBBBssssssSSSSSS. */
+{ "sbcs", 0x28A70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sbcs<.f> a,limm,c 0010111000100111F111CCCCCCAAAAAA. */
+{ "sbcs", 0x2E277000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sbcs<.f> a,b,limm 00101bbb00100111FBBB111110AAAAAA. */
+{ "sbcs", 0x28270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sbcs<.f> 0,limm,c 0010111001100111F111CCCCCC111110. */
+{ "sbcs", 0x2E67703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sbcs<.f> 0,b,limm 00101bbb00100111FBBB111110111110. */
+{ "sbcs", 0x28270FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sbcs<.f><.cc> b,b,limm 00101bbb11100111FBBB1111100QQQQQ. */
+{ "sbcs", 0x28E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sbcs<.f><.cc> 0,limm,c 0010111011100111F111CCCCCC0QQQQQ. */
+{ "sbcs", 0x2EE77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sbcs<.f> a,limm,u6 0010111001100111F111uuuuuuAAAAAA. */
+{ "sbcs", 0x2E677000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbcs<.f> 0,limm,u6 0010111001100111F111uuuuuu111110. */
+{ "sbcs", 0x2E67703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sbcs<.f><.cc> 0,limm,u6 0010111011100111F111uuuuuu1QQQQQ. */
+{ "sbcs", 0x2EE77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sbcs<.f> 0,limm,s12 0010111010100111F111ssssssSSSSSS. */
+{ "sbcs", 0x2EA77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sbcs<.f> a,limm,limm 0010111000100111F111111110AAAAAA. */
+{ "sbcs", 0x2E277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sbcs<.f> 0,limm,limm 0010111000100111F111111110111110. */
+{ "sbcs", 0x2E277FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sbcs<.f><.cc> 0,limm,limm 0010111011100111F1111111100QQQQQ. */
+{ "sbcs", 0x2EE77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* scond<.di> b,c 00100bbb00101111DBBBCCCCCC010001. */
+{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
+
+/* scond<.di> b,u6 00100bbb01101111DBBBuuuuuu010001. */
+{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
+
+/* scond<.di> b,limm 00100bbb00101111DBBB111110010001. */
+{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
+
+/* scondl<.aq> RB,RC 01011bbb00101111FBBBcccccc010001. */
+{ "scondl", 0x582F0011, 0xF8FF003F, ARC_OPCODE_ARC64, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_AQ }},
+
+/* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA. */
+{ "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* setacc 0,b,c 00101bbb000011011BBBCCCCCC111110. */
+{ "setacc", 0x280D803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* setacc<.cc> b,b,c 00101bbb110011011BBBCCCCCC0QQQQQ. */
+{ "setacc", 0x28CD8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* setacc a,b,u6 00101bbb010011011BBBuuuuuuAAAAAA. */
+{ "setacc", 0x284D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* setacc 0,b,u6 00101bbb010011011BBBuuuuuu111110. */
+{ "setacc", 0x284D803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* setacc<.cc> b,b,u6 00101bbb110011011BBBuuuuuu1QQQQQ. */
+{ "setacc", 0x28CD8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* setacc b,b,s12 00101bbb100011011BBBssssssSSSSSS. */
+{ "setacc", 0x288D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* setacc a,limm,c 00101110000011011111CCCCCCAAAAAA. */
+{ "setacc", 0x2E0DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* setacc a,b,limm 00101bbb000011011BBB111110AAAAAA. */
+{ "setacc", 0x280D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* setacc 0,limm,c 00101110000011011111CCCCCC111110. */
+{ "setacc", 0x2E0DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* setacc 0,b,limm 00101bbb000011011BBB111110111110. */
+{ "setacc", 0x280D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* setacc<.cc> b,b,limm 00101bbb110011011BBB1111100QQQQQ. */
+{ "setacc", 0x28CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* setacc<.cc> 0,limm,c 00101110110011011111CCCCCC0QQQQQ. */
+{ "setacc", 0x2ECDF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* setacc a,limm,u6 00101110010011011111uuuuuuAAAAAA. */
+{ "setacc", 0x2E4DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* setacc 0,limm,u6 00101110010011011111uuuuuu111110. */
+{ "setacc", 0x2E4DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* setacc<.cc> 0,limm,u6 00101110110011011111uuuuuu1QQQQQ. */
+{ "setacc", 0x2ECDF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* setacc 0,limm,s12 00101110100011011111ssssssSSSSSS. */
+{ "setacc", 0x2E8DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* setacc a,limm,limm 00101110000011011111111110AAAAAA. */
+{ "setacc", 0x2E0DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* setacc 0,limm,limm 00101110000011011111111110111110. */
+{ "setacc", 0x2E0DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* setacc<.cc> 0,limm,limm 001011101100110111111111100QQQQQ. */
+{ "setacc", 0x2ECDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* seteq<.f> a,b,c 00100bbb00111000FBBBCCCCCCAAAAAA. */
+{ "seteq", 0x20380000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* seteq<.f> 0,b,c 00100bbb00111000FBBBCCCCCC111110. */
+{ "seteq", 0x2038003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* seteq<.f><.cc> b,b,c 00100bbb11111000FBBBCCCCCC0QQQQQ. */
+{ "seteq", 0x20F80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* seteq<.f> a,b,u6 00100bbb01111000FBBBuuuuuuAAAAAA. */
+{ "seteq", 0x20780000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* seteq<.f> 0,b,u6 00100bbb01111000FBBBuuuuuu111110. */
+{ "seteq", 0x2078003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* seteq<.f><.cc> b,b,u6 00100bbb11111000FBBBuuuuuu1QQQQQ. */
+{ "seteq", 0x20F80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteq<.f> b,b,s12 00100bbb10111000FBBBssssssSSSSSS. */
+{ "seteq", 0x20B80000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* seteq<.f> a,limm,c 0010011000111000F111CCCCCCAAAAAA. */
+{ "seteq", 0x26387000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* seteq<.f> a,b,limm 00100bbb00111000FBBB111110AAAAAA. */
+{ "seteq", 0x20380F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* seteq<.f> 0,limm,c 0010011000111000F111CCCCCC111110. */
+{ "seteq", 0x2638703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* seteq<.f> 0,b,limm 00100bbb00111000FBBB111110111110. */
+{ "seteq", 0x20380FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* seteq<.f><.cc> b,b,limm 00100bbb11111000FBBB1111100QQQQQ. */
+{ "seteq", 0x20F80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* seteq<.f><.cc> 0,limm,c 0010011011111000F111CCCCCC0QQQQQ. */
+{ "seteq", 0x26F87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* seteq<.f> a,limm,u6 0010011001111000F111uuuuuuAAAAAA. */
+{ "seteq", 0x26787000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seteq<.f> 0,limm,u6 0010011001111000F111uuuuuu111110. */
+{ "seteq", 0x2678703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seteq<.f><.cc> 0,limm,u6 0010011011111000F111uuuuuu1QQQQQ. */
+{ "seteq", 0x26F87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteq<.f> 0,limm,s12 0010011010111000F111ssssssSSSSSS. */
+{ "seteq", 0x26B87000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* seteq<.f> a,limm,limm 0010011000111000F111111110AAAAAA. */
+{ "seteq", 0x26387F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* seteq<.f> 0,limm,limm 0010011000111000F111111110111110. */
+{ "seteq", 0x26387FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* seteq<.f><.cc> 0,limm,limm 0010011011111000F1111111100QQQQQ. */
+{ "seteq", 0x26F87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* seteql<.f> RA,RB,RC 01011bbb00111000FBBBccccccaaaaaa. */
+{ "seteql", 0x58380000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* seteql<.f> 0,RB,RC 01011bbb00111000FBBBcccccc111110. */
+{ "seteql", 0x5838003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* seteql<.f><.cc> RB,RB,RC 01011bbb11111000FBBBcccccc0QQQQQ. */
+{ "seteql", 0x58F80000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* seteql<.f> RA,RB,u6 01011bbb01111000FBBBuuuuuuaaaaaa. */
+{ "seteql", 0x58780000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* seteql<.f> 0,RB,u6 01011bbb01111000FBBBuuuuuu111110. */
+{ "seteql", 0x5878003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* seteql<.f><.cc> RB,RB,u6 01011bbb11111000FBBBuuuuuu1QQQQQ. */
+{ "seteql", 0x58F80020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteql<.f> RB,RB,s12 01011bbb10111000FBBBssssssSSSSSS. */
+{ "seteql", 0x58B80000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* seteql<.f> RA,ximm,RC 0101110000111000F111ccccccaaaaaa. */
+{ "seteql", 0x5C387000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* seteql<.f> RA,RB,ximm 01011bbb00111000FBBB111100aaaaaa. */
+{ "seteql", 0x58380F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* seteql<.f> 0,ximm,RC 0101110000111000F111cccccc111110. */
+{ "seteql", 0x5C38703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* seteql<.f> 0,RB,ximm 01011bbb00111000FBBB111100111110. */
+{ "seteql", 0x58380F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* seteql<.f><.cc> 0,ximm,RC 0101110011111000F111cccccc0QQQQQ. */
+{ "seteql", 0x5CF87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* seteql<.f><.cc> RB,RB,ximm 01011bbb11111000FBBB1111000QQQQQ. */
+{ "seteql", 0x58F80F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* seteql<.f> RA,ximm,u6 0101110001111000F111uuuuuuaaaaaa. */
+{ "seteql", 0x5C787000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* seteql<.f> 0,ximm,u6 0101110001111000F111uuuuuu111110. */
+{ "seteql", 0x5C78703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* seteql<.f><.cc> 0,ximm,u6 0101110011111000F111uuuuuu1QQQQQ. */
+{ "seteql", 0x5CF87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteql<.f> RA,limm,RC 0101111000111000F111ccccccaaaaaa. */
+{ "seteql", 0x5E387000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* seteql<.f> RA,RB,limm 01011bbb00111000FBBB111110aaaaaa. */
+{ "seteql", 0x58380F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* seteql<.f> 0,limm,RC 0101111000111000F111cccccc111110. */
+{ "seteql", 0x5E38703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* seteql<.f> 0,RB,limm 01011bbb00111000FBBB111110111110. */
+{ "seteql", 0x58380FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* seteql<.f><.cc> 0,limm,RC 0101111011111000F111cccccc0QQQQQ. */
+{ "seteql", 0x5EF87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* seteql<.f><.cc> RB,RB,limm 01011bbb11111000FBBB1111100QQQQQ. */
+{ "seteql", 0x58F80F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* seteql<.f> RA,limm,u6 0101111001111000F111uuuuuuaaaaaa. */
+{ "seteql", 0x5E787000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seteql<.f> 0,limm,u6 0101111001111000F111uuuuuu111110. */
+{ "seteql", 0x5E78703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seteql<.f><.cc> 0,limm,u6 0101111011111000F111uuuuuu1QQQQQ. */
+{ "seteql", 0x5EF87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* seteql<.f> 0,ximm,s12 0101110010111000F111ssssssSSSSSS. */
+{ "seteql", 0x5CB87000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* seteql<.f> 0,limm,s12 0101111010111000F111ssssssSSSSSS. */
+{ "seteql", 0x5EB87000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* seteql<.f> RA,ximm,ximm 0101110000111000F111111100aaaaaa. */
+{ "seteql", 0x5C387F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* seteql<.f> 0,ximm,ximm 0101110000111000F111111100111110. */
+{ "seteql", 0x5C387F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* seteql<.f><.cc> 0,ximm,ximm 0101110011111000F1111111000QQQQQ. */
+{ "seteql", 0x5CF87F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* seteql<.f> RA,limm,limm 0101111000111000F111111110aaaaaa. */
+{ "seteql", 0x5E387F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* seteql<.f> 0,limm,limm 0101111000111000F111111110111110. */
+{ "seteql", 0x5E387FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* seteql<.f><.cc> 0,limm,limm 0101111011111000F1111111100QQQQQ. */
+{ "seteql", 0x5EF87F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setge<.f> a,b,c 00100bbb00111011FBBBCCCCCCAAAAAA. */
+{ "setge", 0x203B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setge<.f> 0,b,c 00100bbb00111011FBBBCCCCCC111110. */
+{ "setge", 0x203B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setge<.f><.cc> b,b,c 00100bbb11111011FBBBCCCCCC0QQQQQ. */
+{ "setge", 0x20FB0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setge<.f> a,b,u6 00100bbb01111011FBBBuuuuuuAAAAAA. */
+{ "setge", 0x207B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setge<.f> 0,b,u6 00100bbb01111011FBBBuuuuuu111110. */
+{ "setge", 0x207B003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setge<.f><.cc> b,b,u6 00100bbb11111011FBBBuuuuuu1QQQQQ. */
+{ "setge", 0x20FB0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setge<.f> b,b,s12 00100bbb10111011FBBBssssssSSSSSS. */
+{ "setge", 0x20BB0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setge<.f> a,limm,c 0010011000111011F111CCCCCCAAAAAA. */
+{ "setge", 0x263B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setge<.f> a,b,limm 00100bbb00111011FBBB111110AAAAAA. */
+{ "setge", 0x203B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setge<.f> 0,limm,c 0010011000111011F111CCCCCC111110. */
+{ "setge", 0x263B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setge<.f> 0,b,limm 00100bbb00111011FBBB111110111110. */
+{ "setge", 0x203B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setge<.f><.cc> b,b,limm 00100bbb11111011FBBB1111100QQQQQ. */
+{ "setge", 0x20FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setge<.f><.cc> 0,limm,c 0010011011111011F111CCCCCC0QQQQQ. */
+{ "setge", 0x26FB7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setge<.f> a,limm,u6 0010011001111011F111uuuuuuAAAAAA. */
+{ "setge", 0x267B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setge<.f> 0,limm,u6 0010011001111011F111uuuuuu111110. */
+{ "setge", 0x267B703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setge<.f><.cc> 0,limm,u6 0010011011111011F111uuuuuu1QQQQQ. */
+{ "setge", 0x26FB7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setge<.f> 0,limm,s12 0010011010111011F111ssssssSSSSSS. */
+{ "setge", 0x26BB7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setge<.f> a,limm,limm 0010011000111011F111111110AAAAAA. */
+{ "setge", 0x263B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setge<.f> 0,limm,limm 0010011000111011F111111110111110. */
+{ "setge", 0x263B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setge<.f><.cc> 0,limm,limm 0010011011111011F1111111100QQQQQ. */
+{ "setge", 0x26FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setgel<.f> RA,RB,RC 01011bbb00111011FBBBccccccaaaaaa. */
+{ "setgel", 0x583B0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setgel<.f> 0,RB,RC 01011bbb00111011FBBBcccccc111110. */
+{ "setgel", 0x583B003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setgel<.f><.cc> RB,RB,RC 01011bbb11111011FBBBcccccc0QQQQQ. */
+{ "setgel", 0x58FB0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setgel<.f> RA,RB,u6 01011bbb01111011FBBBuuuuuuaaaaaa. */
+{ "setgel", 0x587B0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setgel<.f> 0,RB,u6 01011bbb01111011FBBBuuuuuu111110. */
+{ "setgel", 0x587B003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setgel<.f><.cc> RB,RB,u6 01011bbb11111011FBBBuuuuuu1QQQQQ. */
+{ "setgel", 0x58FB0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgel<.f> RB,RB,s12 01011bbb10111011FBBBssssssSSSSSS. */
+{ "setgel", 0x58BB0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setgel<.f> RA,ximm,RC 0101110000111011F111ccccccaaaaaa. */
+{ "setgel", 0x5C3B7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setgel<.f> RA,RB,ximm 01011bbb00111011FBBB111100aaaaaa. */
+{ "setgel", 0x583B0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setgel<.f> 0,ximm,RC 0101110000111011F111cccccc111110. */
+{ "setgel", 0x5C3B703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setgel<.f> 0,RB,ximm 01011bbb00111011FBBB111100111110. */
+{ "setgel", 0x583B0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setgel<.f><.cc> 0,ximm,RC 0101110011111011F111cccccc0QQQQQ. */
+{ "setgel", 0x5CFB7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setgel<.f><.cc> RB,RB,ximm 01011bbb11111011FBBB1111000QQQQQ. */
+{ "setgel", 0x58FB0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setgel<.f> RA,ximm,u6 0101110001111011F111uuuuuuaaaaaa. */
+{ "setgel", 0x5C7B7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setgel<.f> 0,ximm,u6 0101110001111011F111uuuuuu111110. */
+{ "setgel", 0x5C7B703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setgel<.f><.cc> 0,ximm,u6 0101110011111011F111uuuuuu1QQQQQ. */
+{ "setgel", 0x5CFB7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgel<.f> RA,limm,RC 0101111000111011F111ccccccaaaaaa. */
+{ "setgel", 0x5E3B7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setgel<.f> RA,RB,limm 01011bbb00111011FBBB111110aaaaaa. */
+{ "setgel", 0x583B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setgel<.f> 0,limm,RC 0101111000111011F111cccccc111110. */
+{ "setgel", 0x5E3B703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setgel<.f> 0,RB,limm 01011bbb00111011FBBB111110111110. */
+{ "setgel", 0x583B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setgel<.f><.cc> 0,limm,RC 0101111011111011F111cccccc0QQQQQ. */
+{ "setgel", 0x5EFB7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setgel<.f><.cc> RB,RB,limm 01011bbb11111011FBBB1111100QQQQQ. */
+{ "setgel", 0x58FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setgel<.f> RA,limm,u6 0101111001111011F111uuuuuuaaaaaa. */
+{ "setgel", 0x5E7B7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgel<.f> 0,limm,u6 0101111001111011F111uuuuuu111110. */
+{ "setgel", 0x5E7B703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgel<.f><.cc> 0,limm,u6 0101111011111011F111uuuuuu1QQQQQ. */
+{ "setgel", 0x5EFB7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgel<.f> 0,ximm,s12 0101110010111011F111ssssssSSSSSS. */
+{ "setgel", 0x5CBB7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setgel<.f> 0,limm,s12 0101111010111011F111ssssssSSSSSS. */
+{ "setgel", 0x5EBB7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setgel<.f> RA,ximm,ximm 0101110000111011F111111100aaaaaa. */
+{ "setgel", 0x5C3B7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setgel<.f> 0,ximm,ximm 0101110000111011F111111100111110. */
+{ "setgel", 0x5C3B7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setgel<.f><.cc> 0,ximm,ximm 0101110011111011F1111111000QQQQQ. */
+{ "setgel", 0x5CFB7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setgel<.f> RA,limm,limm 0101111000111011F111111110aaaaaa. */
+{ "setgel", 0x5E3B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setgel<.f> 0,limm,limm 0101111000111011F111111110111110. */
+{ "setgel", 0x5E3B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setgel<.f><.cc> 0,limm,limm 0101111011111011F1111111100QQQQQ. */
+{ "setgel", 0x5EFB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setgt<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA. */
+{ "setgt", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setgt<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110. */
+{ "setgt", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setgt<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ. */
+{ "setgt", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setgt<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA. */
+{ "setgt", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setgt<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110. */
+{ "setgt", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setgt<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ. */
+{ "setgt", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgt<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS. */
+{ "setgt", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setgt<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA. */
+{ "setgt", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setgt<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA. */
+{ "setgt", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setgt<.f> 0,limm,c 0010011000111111F111CCCCCC111110. */
+{ "setgt", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setgt<.f> 0,b,limm 00100bbb00111111FBBB111110111110. */
+{ "setgt", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setgt<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ. */
+{ "setgt", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setgt<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ. */
+{ "setgt", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setgt<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA. */
+{ "setgt", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgt<.f> 0,limm,u6 0010011001111111F111uuuuuu111110. */
+{ "setgt", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgt<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ. */
+{ "setgt", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgt<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS. */
+{ "setgt", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setgt<.f> a,limm,limm 0010011000111111F111111110AAAAAA. */
+{ "setgt", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setgt<.f> 0,limm,limm 0010011000111111F111111110111110. */
+{ "setgt", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setgt<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ. */
+{ "setgt", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,RB,RC 01011bbb00111111FBBBccccccaaaaaa. */
+{ "setgtl", 0x583F0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setgtl<.f> 0,RB,RC 01011bbb00111111FBBBcccccc111110. */
+{ "setgtl", 0x583F003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setgtl<.f><.cc> RB,RB,RC 01011bbb11111111FBBBcccccc0QQQQQ. */
+{ "setgtl", 0x58FF0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,RB,u6 01011bbb01111111FBBBuuuuuuaaaaaa. */
+{ "setgtl", 0x587F0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f> 0,RB,u6 01011bbb01111111FBBBuuuuuu111110. */
+{ "setgtl", 0x587F003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f><.cc> RB,RB,u6 01011bbb11111111FBBBuuuuuu1QQQQQ. */
+{ "setgtl", 0x58FF0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgtl<.f> RB,RB,s12 01011bbb10111111FBBBssssssSSSSSS. */
+{ "setgtl", 0x58BF0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setgtl<.f> RA,ximm,RC 0101110000111111F111ccccccaaaaaa. */
+{ "setgtl", 0x5C3F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setgtl<.f> RA,RB,ximm 01011bbb00111111FBBB111100aaaaaa. */
+{ "setgtl", 0x583F0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setgtl<.f> 0,ximm,RC 0101110000111111F111cccccc111110. */
+{ "setgtl", 0x5C3F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setgtl<.f> 0,RB,ximm 01011bbb00111111FBBB111100111110. */
+{ "setgtl", 0x583F0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setgtl<.f><.cc> 0,ximm,RC 0101110011111111F111cccccc0QQQQQ. */
+{ "setgtl", 0x5CFF7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setgtl<.f><.cc> RB,RB,ximm 01011bbb11111111FBBB1111000QQQQQ. */
+{ "setgtl", 0x58FF0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,ximm,u6 0101110001111111F111uuuuuuaaaaaa. */
+{ "setgtl", 0x5C7F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f> 0,ximm,u6 0101110001111111F111uuuuuu111110. */
+{ "setgtl", 0x5C7F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f><.cc> 0,ximm,u6 0101110011111111F111uuuuuu1QQQQQ. */
+{ "setgtl", 0x5CFF7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,limm,RC 0101111000111111F111ccccccaaaaaa. */
+{ "setgtl", 0x5E3F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setgtl<.f> RA,RB,limm 01011bbb00111111FBBB111110aaaaaa. */
+{ "setgtl", 0x583F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setgtl<.f> 0,limm,RC 0101111000111111F111cccccc111110. */
+{ "setgtl", 0x5E3F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setgtl<.f> 0,RB,limm 01011bbb00111111FBBB111110111110. */
+{ "setgtl", 0x583F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setgtl<.f><.cc> 0,limm,RC 0101111011111111F111cccccc0QQQQQ. */
+{ "setgtl", 0x5EFF7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setgtl<.f><.cc> RB,RB,limm 01011bbb11111111FBBB1111100QQQQQ. */
+{ "setgtl", 0x58FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,limm,u6 0101111001111111F111uuuuuuaaaaaa. */
+{ "setgtl", 0x5E7F7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f> 0,limm,u6 0101111001111111F111uuuuuu111110. */
+{ "setgtl", 0x5E7F703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setgtl<.f><.cc> 0,limm,u6 0101111011111111F111uuuuuu1QQQQQ. */
+{ "setgtl", 0x5EFF7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setgtl<.f> 0,ximm,s12 0101110010111111F111ssssssSSSSSS. */
+{ "setgtl", 0x5CBF7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setgtl<.f> 0,limm,s12 0101111010111111F111ssssssSSSSSS. */
+{ "setgtl", 0x5EBF7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setgtl<.f> RA,ximm,ximm 0101110000111111F111111100aaaaaa. */
+{ "setgtl", 0x5C3F7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setgtl<.f> 0,ximm,ximm 0101110000111111F111111100111110. */
+{ "setgtl", 0x5C3F7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setgtl<.f><.cc> 0,ximm,ximm 0101110011111111F1111111000QQQQQ. */
+{ "setgtl", 0x5CFF7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setgtl<.f> RA,limm,limm 0101111000111111F111111110aaaaaa. */
+{ "setgtl", 0x5E3F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setgtl<.f> 0,limm,limm 0101111000111111F111111110111110. */
+{ "setgtl", 0x5E3F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setgtl<.f><.cc> 0,limm,limm 0101111011111111F1111111100QQQQQ. */
+{ "setgtl", 0x5EFF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* seths<.f> a,b,c 00100bbb00111101FBBBCCCCCCAAAAAA. */
+{ "seths", 0x203D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* seths<.f> 0,b,c 00100bbb00111101FBBBCCCCCC111110. */
+{ "seths", 0x203D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* seths<.f><.cc> b,b,c 00100bbb11111101FBBBCCCCCC0QQQQQ. */
+{ "seths", 0x20FD0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* seths<.f> a,b,u6 00100bbb01111101FBBBuuuuuuAAAAAA. */
+{ "seths", 0x207D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* seths<.f> 0,b,u6 00100bbb01111101FBBBuuuuuu111110. */
+{ "seths", 0x207D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* seths<.f><.cc> b,b,u6 00100bbb11111101FBBBuuuuuu1QQQQQ. */
+{ "seths", 0x20FD0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* seths<.f> b,b,s12 00100bbb10111101FBBBssssssSSSSSS. */
+{ "seths", 0x20BD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* seths<.f> a,limm,c 0010011000111101F111CCCCCCAAAAAA. */
+{ "seths", 0x263D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* seths<.f> a,b,limm 00100bbb00111101FBBB111110AAAAAA. */
+{ "seths", 0x203D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* seths<.f> 0,limm,c 0010011000111101F111CCCCCC111110. */
+{ "seths", 0x263D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* seths<.f> 0,b,limm 00100bbb00111101FBBB111110111110. */
+{ "seths", 0x203D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* seths<.f><.cc> b,b,limm 00100bbb11111101FBBB1111100QQQQQ. */
+{ "seths", 0x20FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* seths<.f><.cc> 0,limm,c 0010011011111101F111CCCCCC0QQQQQ. */
+{ "seths", 0x26FD7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* seths<.f> a,limm,u6 0010011001111101F111uuuuuuAAAAAA. */
+{ "seths", 0x267D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seths<.f> 0,limm,u6 0010011001111101F111uuuuuu111110. */
+{ "seths", 0x267D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* seths<.f><.cc> 0,limm,u6 0010011011111101F111uuuuuu1QQQQQ. */
+{ "seths", 0x26FD7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* seths<.f> 0,limm,s12 0010011010111101F111ssssssSSSSSS. */
+{ "seths", 0x26BD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* seths<.f> a,limm,limm 0010011000111101F111111110AAAAAA. */
+{ "seths", 0x263D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* seths<.f> 0,limm,limm 0010011000111101F111111110111110. */
+{ "seths", 0x263D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* seths<.f><.cc> 0,limm,limm 0010011011111101F1111111100QQQQQ. */
+{ "seths", 0x26FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,RB,RC 01011bbb00111101FBBBccccccaaaaaa. */
+{ "sethsl", 0x583D0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sethsl<.f> 0,RB,RC 01011bbb00111101FBBBcccccc111110. */
+{ "sethsl", 0x583D003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sethsl<.f><.cc> RB,RB,RC 01011bbb11111101FBBBcccccc0QQQQQ. */
+{ "sethsl", 0x58FD0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,RB,u6 01011bbb01111101FBBBuuuuuuaaaaaa. */
+{ "sethsl", 0x587D0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f> 0,RB,u6 01011bbb01111101FBBBuuuuuu111110. */
+{ "sethsl", 0x587D003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f><.cc> RB,RB,u6 01011bbb11111101FBBBuuuuuu1QQQQQ. */
+{ "sethsl", 0x58FD0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sethsl<.f> RB,RB,s12 01011bbb10111101FBBBssssssSSSSSS. */
+{ "sethsl", 0x58BD0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sethsl<.f> RA,ximm,RC 0101110000111101F111ccccccaaaaaa. */
+{ "sethsl", 0x5C3D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* sethsl<.f> RA,RB,ximm 01011bbb00111101FBBB111100aaaaaa. */
+{ "sethsl", 0x583D0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* sethsl<.f> 0,ximm,RC 0101110000111101F111cccccc111110. */
+{ "sethsl", 0x5C3D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* sethsl<.f> 0,RB,ximm 01011bbb00111101FBBB111100111110. */
+{ "sethsl", 0x583D0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* sethsl<.f><.cc> 0,ximm,RC 0101110011111101F111cccccc0QQQQQ. */
+{ "sethsl", 0x5CFD7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* sethsl<.f><.cc> RB,RB,ximm 01011bbb11111101FBBB1111000QQQQQ. */
+{ "sethsl", 0x58FD0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,ximm,u6 0101110001111101F111uuuuuuaaaaaa. */
+{ "sethsl", 0x5C7D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f> 0,ximm,u6 0101110001111101F111uuuuuu111110. */
+{ "sethsl", 0x5C7D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f><.cc> 0,ximm,u6 0101110011111101F111uuuuuu1QQQQQ. */
+{ "sethsl", 0x5CFD7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,limm,RC 0101111000111101F111ccccccaaaaaa. */
+{ "sethsl", 0x5E3D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sethsl<.f> RA,RB,limm 01011bbb00111101FBBB111110aaaaaa. */
+{ "sethsl", 0x583D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sethsl<.f> 0,limm,RC 0101111000111101F111cccccc111110. */
+{ "sethsl", 0x5E3D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sethsl<.f> 0,RB,limm 01011bbb00111101FBBB111110111110. */
+{ "sethsl", 0x583D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sethsl<.f><.cc> 0,limm,RC 0101111011111101F111cccccc0QQQQQ. */
+{ "sethsl", 0x5EFD7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sethsl<.f><.cc> RB,RB,limm 01011bbb11111101FBBB1111100QQQQQ. */
+{ "sethsl", 0x58FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,limm,u6 0101111001111101F111uuuuuuaaaaaa. */
+{ "sethsl", 0x5E7D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f> 0,limm,u6 0101111001111101F111uuuuuu111110. */
+{ "sethsl", 0x5E7D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sethsl<.f><.cc> 0,limm,u6 0101111011111101F111uuuuuu1QQQQQ. */
+{ "sethsl", 0x5EFD7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sethsl<.f> 0,ximm,s12 0101110010111101F111ssssssSSSSSS. */
+{ "sethsl", 0x5CBD7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* sethsl<.f> 0,limm,s12 0101111010111101F111ssssssSSSSSS. */
+{ "sethsl", 0x5EBD7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sethsl<.f> RA,ximm,ximm 0101110000111101F111111100aaaaaa. */
+{ "sethsl", 0x5C3D7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* sethsl<.f> 0,ximm,ximm 0101110000111101F111111100111110. */
+{ "sethsl", 0x5C3D7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* sethsl<.f><.cc> 0,ximm,ximm 0101110011111101F1111111000QQQQQ. */
+{ "sethsl", 0x5CFD7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* sethsl<.f> RA,limm,limm 0101111000111101F111111110aaaaaa. */
+{ "sethsl", 0x5E3D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sethsl<.f> 0,limm,limm 0101111000111101F111111110111110. */
+{ "sethsl", 0x5E3D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sethsl<.f><.cc> 0,limm,limm 0101111011111101F1111111100QQQQQ. */
+{ "sethsl", 0x5EFD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* seti c 00100110001011110000CCCCCC111111. */
+{ "seti", 0x262F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { RC }, { 0 }},
+
+/* seti u6 00100110011011110000uuuuuu111111. */
+{ "seti", 0x266F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { UIMM6_20 }, { 0 }},
+
+/* seti limm 00100110001011110000111110111111. */
+{ "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { LIMM }, { 0 }},
+
+/* seti 00100110011011110000000000111111. */
+{ "seti", 0x266F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */
+{ "setle", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setle<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110. */
+{ "setle", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setle<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ. */
+{ "setle", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setle<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA. */
+{ "setle", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setle<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110. */
+{ "setle", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setle<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ. */
+{ "setle", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setle<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS. */
+{ "setle", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setle<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA. */
+{ "setle", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setle<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA. */
+{ "setle", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setle<.f> 0,limm,c 0010011000111110F111CCCCCC111110. */
+{ "setle", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setle<.f> 0,b,limm 00100bbb00111110FBBB111110111110. */
+{ "setle", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setle<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ. */
+{ "setle", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setle<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ. */
+{ "setle", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setle<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA. */
+{ "setle", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setle<.f> 0,limm,u6 0010011001111110F111uuuuuu111110. */
+{ "setle", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setle<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ. */
+{ "setle", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setle<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS. */
+{ "setle", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setle<.f> a,limm,limm 0010011000111110F111111110AAAAAA. */
+{ "setle", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setle<.f> 0,limm,limm 0010011000111110F111111110111110. */
+{ "setle", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setle<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ. */
+{ "setle", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setlel<.f> RA,RB,RC 01011bbb00111110FBBBccccccaaaaaa. */
+{ "setlel", 0x583E0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setlel<.f> 0,RB,RC 01011bbb00111110FBBBcccccc111110. */
+{ "setlel", 0x583E003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setlel<.f><.cc> RB,RB,RC 01011bbb11111110FBBBcccccc0QQQQQ. */
+{ "setlel", 0x58FE0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setlel<.f> RA,RB,u6 01011bbb01111110FBBBuuuuuuaaaaaa. */
+{ "setlel", 0x587E0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setlel<.f> 0,RB,u6 01011bbb01111110FBBBuuuuuu111110. */
+{ "setlel", 0x587E003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setlel<.f><.cc> RB,RB,u6 01011bbb11111110FBBBuuuuuu1QQQQQ. */
+{ "setlel", 0x58FE0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlel<.f> RB,RB,s12 01011bbb10111110FBBBssssssSSSSSS. */
+{ "setlel", 0x58BE0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setlel<.f> RA,ximm,RC 0101110000111110F111ccccccaaaaaa. */
+{ "setlel", 0x5C3E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setlel<.f> RA,RB,ximm 01011bbb00111110FBBB111100aaaaaa. */
+{ "setlel", 0x583E0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setlel<.f> 0,ximm,RC 0101110000111110F111cccccc111110. */
+{ "setlel", 0x5C3E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setlel<.f> 0,RB,ximm 01011bbb00111110FBBB111100111110. */
+{ "setlel", 0x583E0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setlel<.f><.cc> 0,ximm,RC 0101110011111110F111cccccc0QQQQQ. */
+{ "setlel", 0x5CFE7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setlel<.f><.cc> RB,RB,ximm 01011bbb11111110FBBB1111000QQQQQ. */
+{ "setlel", 0x58FE0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setlel<.f> RA,ximm,u6 0101110001111110F111uuuuuuaaaaaa. */
+{ "setlel", 0x5C7E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setlel<.f> 0,ximm,u6 0101110001111110F111uuuuuu111110. */
+{ "setlel", 0x5C7E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setlel<.f><.cc> 0,ximm,u6 0101110011111110F111uuuuuu1QQQQQ. */
+{ "setlel", 0x5CFE7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlel<.f> RA,limm,RC 0101111000111110F111ccccccaaaaaa. */
+{ "setlel", 0x5E3E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setlel<.f> RA,RB,limm 01011bbb00111110FBBB111110aaaaaa. */
+{ "setlel", 0x583E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setlel<.f> 0,limm,RC 0101111000111110F111cccccc111110. */
+{ "setlel", 0x5E3E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setlel<.f> 0,RB,limm 01011bbb00111110FBBB111110111110. */
+{ "setlel", 0x583E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setlel<.f><.cc> 0,limm,RC 0101111011111110F111cccccc0QQQQQ. */
+{ "setlel", 0x5EFE7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setlel<.f><.cc> RB,RB,limm 01011bbb11111110FBBB1111100QQQQQ. */
+{ "setlel", 0x58FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setlel<.f> RA,limm,u6 0101111001111110F111uuuuuuaaaaaa. */
+{ "setlel", 0x5E7E7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlel<.f> 0,limm,u6 0101111001111110F111uuuuuu111110. */
+{ "setlel", 0x5E7E703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlel<.f><.cc> 0,limm,u6 0101111011111110F111uuuuuu1QQQQQ. */
+{ "setlel", 0x5EFE7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlel<.f> 0,ximm,s12 0101110010111110F111ssssssSSSSSS. */
+{ "setlel", 0x5CBE7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setlel<.f> 0,limm,s12 0101111010111110F111ssssssSSSSSS. */
+{ "setlel", 0x5EBE7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setlel<.f> RA,ximm,ximm 0101110000111110F111111100aaaaaa. */
+{ "setlel", 0x5C3E7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setlel<.f> 0,ximm,ximm 0101110000111110F111111100111110. */
+{ "setlel", 0x5C3E7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setlel<.f><.cc> 0,ximm,ximm 0101110011111110F1111111000QQQQQ. */
+{ "setlel", 0x5CFE7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setlel<.f> RA,limm,limm 0101111000111110F111111110aaaaaa. */
+{ "setlel", 0x5E3E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setlel<.f> 0,limm,limm 0101111000111110F111111110111110. */
+{ "setlel", 0x5E3E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setlel<.f><.cc> 0,limm,limm 0101111011111110F1111111100QQQQQ. */
+{ "setlel", 0x5EFE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setlo<.f> a,b,c 00100bbb00111100FBBBCCCCCCAAAAAA. */
+{ "setlo", 0x203C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setlo<.f> 0,b,c 00100bbb00111100FBBBCCCCCC111110. */
+{ "setlo", 0x203C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setlo<.f><.cc> b,b,c 00100bbb11111100FBBBCCCCCC0QQQQQ. */
+{ "setlo", 0x20FC0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setlo<.f> a,b,u6 00100bbb01111100FBBBuuuuuuAAAAAA. */
+{ "setlo", 0x207C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setlo<.f> 0,b,u6 00100bbb01111100FBBBuuuuuu111110. */
+{ "setlo", 0x207C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setlo<.f><.cc> b,b,u6 00100bbb11111100FBBBuuuuuu1QQQQQ. */
+{ "setlo", 0x20FC0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlo<.f> b,b,s12 00100bbb10111100FBBBssssssSSSSSS. */
+{ "setlo", 0x20BC0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setlo<.f> a,limm,c 0010011000111100F111CCCCCCAAAAAA. */
+{ "setlo", 0x263C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setlo<.f> a,b,limm 00100bbb00111100FBBB111110AAAAAA. */
+{ "setlo", 0x203C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setlo<.f> 0,limm,c 0010011000111100F111CCCCCC111110. */
+{ "setlo", 0x263C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setlo<.f> 0,b,limm 00100bbb00111100FBBB111110111110. */
+{ "setlo", 0x203C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setlo<.f><.cc> b,b,limm 00100bbb11111100FBBB1111100QQQQQ. */
+{ "setlo", 0x20FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setlo<.f><.cc> 0,limm,c 0010011011111100F111CCCCCC0QQQQQ. */
+{ "setlo", 0x26FC7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setlo<.f> a,limm,u6 0010011001111100F111uuuuuuAAAAAA. */
+{ "setlo", 0x267C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlo<.f> 0,limm,u6 0010011001111100F111uuuuuu111110. */
+{ "setlo", 0x267C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlo<.f><.cc> 0,limm,u6 0010011011111100F111uuuuuu1QQQQQ. */
+{ "setlo", 0x26FC7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlo<.f> 0,limm,s12 0010011010111100F111ssssssSSSSSS. */
+{ "setlo", 0x26BC7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setlo<.f> a,limm,limm 0010011000111100F111111110AAAAAA. */
+{ "setlo", 0x263C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setlo<.f> 0,limm,limm 0010011000111100F111111110111110. */
+{ "setlo", 0x263C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setlo<.f><.cc> 0,limm,limm 0010011011111100F1111111100QQQQQ. */
+{ "setlo", 0x26FC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setlol<.f> RA,RB,RC 01011bbb00111100FBBBccccccaaaaaa. */
+{ "setlol", 0x583C0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setlol<.f> 0,RB,RC 01011bbb00111100FBBBcccccc111110. */
+{ "setlol", 0x583C003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setlol<.f><.cc> RB,RB,RC 01011bbb11111100FBBBcccccc0QQQQQ. */
+{ "setlol", 0x58FC0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setlol<.f> RA,RB,u6 01011bbb01111100FBBBuuuuuuaaaaaa. */
+{ "setlol", 0x587C0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setlol<.f> 0,RB,u6 01011bbb01111100FBBBuuuuuu111110. */
+{ "setlol", 0x587C003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setlol<.f><.cc> RB,RB,u6 01011bbb11111100FBBBuuuuuu1QQQQQ. */
+{ "setlol", 0x58FC0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlol<.f> RB,RB,s12 01011bbb10111100FBBBssssssSSSSSS. */
+{ "setlol", 0x58BC0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setlol<.f> RA,ximm,RC 0101110000111100F111ccccccaaaaaa. */
+{ "setlol", 0x5C3C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setlol<.f> RA,RB,ximm 01011bbb00111100FBBB111100aaaaaa. */
+{ "setlol", 0x583C0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setlol<.f> 0,ximm,RC 0101110000111100F111cccccc111110. */
+{ "setlol", 0x5C3C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setlol<.f> 0,RB,ximm 01011bbb00111100FBBB111100111110. */
+{ "setlol", 0x583C0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setlol<.f><.cc> 0,ximm,RC 0101110011111100F111cccccc0QQQQQ. */
+{ "setlol", 0x5CFC7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setlol<.f><.cc> RB,RB,ximm 01011bbb11111100FBBB1111000QQQQQ. */
+{ "setlol", 0x58FC0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setlol<.f> RA,ximm,u6 0101110001111100F111uuuuuuaaaaaa. */
+{ "setlol", 0x5C7C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setlol<.f> 0,ximm,u6 0101110001111100F111uuuuuu111110. */
+{ "setlol", 0x5C7C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setlol<.f><.cc> 0,ximm,u6 0101110011111100F111uuuuuu1QQQQQ. */
+{ "setlol", 0x5CFC7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlol<.f> RA,limm,RC 0101111000111100F111ccccccaaaaaa. */
+{ "setlol", 0x5E3C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setlol<.f> RA,RB,limm 01011bbb00111100FBBB111110aaaaaa. */
+{ "setlol", 0x583C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setlol<.f> 0,limm,RC 0101111000111100F111cccccc111110. */
+{ "setlol", 0x5E3C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setlol<.f> 0,RB,limm 01011bbb00111100FBBB111110111110. */
+{ "setlol", 0x583C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setlol<.f><.cc> 0,limm,RC 0101111011111100F111cccccc0QQQQQ. */
+{ "setlol", 0x5EFC7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setlol<.f><.cc> RB,RB,limm 01011bbb11111100FBBB1111100QQQQQ. */
+{ "setlol", 0x58FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setlol<.f> RA,limm,u6 0101111001111100F111uuuuuuaaaaaa. */
+{ "setlol", 0x5E7C7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlol<.f> 0,limm,u6 0101111001111100F111uuuuuu111110. */
+{ "setlol", 0x5E7C703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlol<.f><.cc> 0,limm,u6 0101111011111100F111uuuuuu1QQQQQ. */
+{ "setlol", 0x5EFC7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlol<.f> 0,ximm,s12 0101110010111100F111ssssssSSSSSS. */
+{ "setlol", 0x5CBC7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setlol<.f> 0,limm,s12 0101111010111100F111ssssssSSSSSS. */
+{ "setlol", 0x5EBC7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setlol<.f> RA,ximm,ximm 0101110000111100F111111100aaaaaa. */
+{ "setlol", 0x5C3C7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setlol<.f> 0,ximm,ximm 0101110000111100F111111100111110. */
+{ "setlol", 0x5C3C7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setlol<.f><.cc> 0,ximm,ximm 0101110011111100F1111111000QQQQQ. */
+{ "setlol", 0x5CFC7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setlol<.f> RA,limm,limm 0101111000111100F111111110aaaaaa. */
+{ "setlol", 0x5E3C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setlol<.f> 0,limm,limm 0101111000111100F111111110111110. */
+{ "setlol", 0x5E3C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setlol<.f><.cc> 0,limm,limm 0101111011111100F1111111100QQQQQ. */
+{ "setlol", 0x5EFC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setlt<.f> a,b,c 00100bbb00111010FBBBCCCCCCAAAAAA. */
+{ "setlt", 0x203A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setlt<.f> 0,b,c 00100bbb00111010FBBBCCCCCC111110. */
+{ "setlt", 0x203A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setlt<.f><.cc> b,b,c 00100bbb11111010FBBBCCCCCC0QQQQQ. */
+{ "setlt", 0x20FA0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setlt<.f> a,b,u6 00100bbb01111010FBBBuuuuuuAAAAAA. */
+{ "setlt", 0x207A0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setlt<.f> 0,b,u6 00100bbb01111010FBBBuuuuuu111110. */
+{ "setlt", 0x207A003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setlt<.f><.cc> b,b,u6 00100bbb11111010FBBBuuuuuu1QQQQQ. */
+{ "setlt", 0x20FA0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlt<.f> b,b,s12 00100bbb10111010FBBBssssssSSSSSS. */
+{ "setlt", 0x20BA0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setlt<.f> a,limm,c 0010011000111010F111CCCCCCAAAAAA. */
+{ "setlt", 0x263A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setlt<.f> a,b,limm 00100bbb00111010FBBB111110AAAAAA. */
+{ "setlt", 0x203A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setlt<.f> 0,limm,c 0010011000111010F111CCCCCC111110. */
+{ "setlt", 0x263A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setlt<.f> 0,b,limm 00100bbb00111010FBBB111110111110. */
+{ "setlt", 0x203A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setlt<.f><.cc> b,b,limm 00100bbb11111010FBBB1111100QQQQQ. */
+{ "setlt", 0x20FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setlt<.f><.cc> 0,limm,c 0010011011111010F111CCCCCC0QQQQQ. */
+{ "setlt", 0x26FA7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setlt<.f> a,limm,u6 0010011001111010F111uuuuuuAAAAAA. */
+{ "setlt", 0x267A7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlt<.f> 0,limm,u6 0010011001111010F111uuuuuu111110. */
+{ "setlt", 0x267A703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setlt<.f><.cc> 0,limm,u6 0010011011111010F111uuuuuu1QQQQQ. */
+{ "setlt", 0x26FA7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setlt<.f> 0,limm,s12 0010011010111010F111ssssssSSSSSS. */
+{ "setlt", 0x26BA7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setlt<.f> a,limm,limm 0010011000111010F111111110AAAAAA. */
+{ "setlt", 0x263A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setlt<.f> 0,limm,limm 0010011000111010F111111110111110. */
+{ "setlt", 0x263A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setlt<.f><.cc> 0,limm,limm 0010011011111010F1111111100QQQQQ. */
+{ "setlt", 0x26FA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setltl<.f> RA,RB,RC 01011bbb00111010FBBBccccccaaaaaa. */
+{ "setltl", 0x583A0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setltl<.f> 0,RB,RC 01011bbb00111010FBBBcccccc111110. */
+{ "setltl", 0x583A003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setltl<.f><.cc> RB,RB,RC 01011bbb11111010FBBBcccccc0QQQQQ. */
+{ "setltl", 0x58FA0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setltl<.f> RA,RB,u6 01011bbb01111010FBBBuuuuuuaaaaaa. */
+{ "setltl", 0x587A0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setltl<.f> 0,RB,u6 01011bbb01111010FBBBuuuuuu111110. */
+{ "setltl", 0x587A003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setltl<.f><.cc> RB,RB,u6 01011bbb11111010FBBBuuuuuu1QQQQQ. */
+{ "setltl", 0x58FA0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setltl<.f> RB,RB,s12 01011bbb10111010FBBBssssssSSSSSS. */
+{ "setltl", 0x58BA0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setltl<.f> RA,ximm,RC 0101110000111010F111ccccccaaaaaa. */
+{ "setltl", 0x5C3A7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setltl<.f> RA,RB,ximm 01011bbb00111010FBBB111100aaaaaa. */
+{ "setltl", 0x583A0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setltl<.f> 0,ximm,RC 0101110000111010F111cccccc111110. */
+{ "setltl", 0x5C3A703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setltl<.f> 0,RB,ximm 01011bbb00111010FBBB111100111110. */
+{ "setltl", 0x583A0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setltl<.f><.cc> 0,ximm,RC 0101110011111010F111cccccc0QQQQQ. */
+{ "setltl", 0x5CFA7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setltl<.f><.cc> RB,RB,ximm 01011bbb11111010FBBB1111000QQQQQ. */
+{ "setltl", 0x58FA0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setltl<.f> RA,ximm,u6 0101110001111010F111uuuuuuaaaaaa. */
+{ "setltl", 0x5C7A7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setltl<.f> 0,ximm,u6 0101110001111010F111uuuuuu111110. */
+{ "setltl", 0x5C7A703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setltl<.f><.cc> 0,ximm,u6 0101110011111010F111uuuuuu1QQQQQ. */
+{ "setltl", 0x5CFA7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setltl<.f> RA,limm,RC 0101111000111010F111ccccccaaaaaa. */
+{ "setltl", 0x5E3A7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setltl<.f> RA,RB,limm 01011bbb00111010FBBB111110aaaaaa. */
+{ "setltl", 0x583A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setltl<.f> 0,limm,RC 0101111000111010F111cccccc111110. */
+{ "setltl", 0x5E3A703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setltl<.f> 0,RB,limm 01011bbb00111010FBBB111110111110. */
+{ "setltl", 0x583A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setltl<.f><.cc> 0,limm,RC 0101111011111010F111cccccc0QQQQQ. */
+{ "setltl", 0x5EFA7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setltl<.f><.cc> RB,RB,limm 01011bbb11111010FBBB1111100QQQQQ. */
+{ "setltl", 0x58FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setltl<.f> RA,limm,u6 0101111001111010F111uuuuuuaaaaaa. */
+{ "setltl", 0x5E7A7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setltl<.f> 0,limm,u6 0101111001111010F111uuuuuu111110. */
+{ "setltl", 0x5E7A703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setltl<.f><.cc> 0,limm,u6 0101111011111010F111uuuuuu1QQQQQ. */
+{ "setltl", 0x5EFA7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setltl<.f> 0,ximm,s12 0101110010111010F111ssssssSSSSSS. */
+{ "setltl", 0x5CBA7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setltl<.f> 0,limm,s12 0101111010111010F111ssssssSSSSSS. */
+{ "setltl", 0x5EBA7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setltl<.f> RA,ximm,ximm 0101110000111010F111111100aaaaaa. */
+{ "setltl", 0x5C3A7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setltl<.f> 0,ximm,ximm 0101110000111010F111111100111110. */
+{ "setltl", 0x5C3A7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setltl<.f><.cc> 0,ximm,ximm 0101110011111010F1111111000QQQQQ. */
+{ "setltl", 0x5CFA7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setltl<.f> RA,limm,limm 0101111000111010F111111110aaaaaa. */
+{ "setltl", 0x5E3A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setltl<.f> 0,limm,limm 0101111000111010F111111110111110. */
+{ "setltl", 0x5E3A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setltl<.f><.cc> 0,limm,limm 0101111011111010F1111111100QQQQQ. */
+{ "setltl", 0x5EFA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setne<.f> a,b,c 00100bbb00111001FBBBCCCCCCAAAAAA. */
+{ "setne", 0x20390000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
+
+/* setne<.f> 0,b,c 00100bbb00111001FBBBCCCCCC111110. */
+{ "setne", 0x2039003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, RC }, { C_F }},
+
+/* setne<.f><.cc> b,b,c 00100bbb11111001FBBBCCCCCC0QQQQQ. */
+{ "setne", 0x20F90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setne<.f> a,b,u6 00100bbb01111001FBBBuuuuuuAAAAAA. */
+{ "setne", 0x20790000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setne<.f> 0,b,u6 00100bbb01111001FBBBuuuuuu111110. */
+{ "setne", 0x2079003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setne<.f><.cc> b,b,u6 00100bbb11111001FBBBuuuuuu1QQQQQ. */
+{ "setne", 0x20F90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setne<.f> b,b,s12 00100bbb10111001FBBBssssssSSSSSS. */
+{ "setne", 0x20B90000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setne<.f> a,limm,c 0010011000111001F111CCCCCCAAAAAA. */
+{ "setne", 0x26397000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }},
+
+/* setne<.f> a,b,limm 00100bbb00111001FBBB111110AAAAAA. */
+{ "setne", 0x20390F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }},
+
+/* setne<.f> 0,limm,c 0010011000111001F111CCCCCC111110. */
+{ "setne", 0x2639703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }},
+
+/* setne<.f> 0,b,limm 00100bbb00111001FBBB111110111110. */
+{ "setne", 0x20390FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }},
+
+/* setne<.f><.cc> b,b,limm 00100bbb11111001FBBB1111100QQQQQ. */
+{ "setne", 0x20F90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setne<.f><.cc> 0,limm,c 0010011011111001F111CCCCCC0QQQQQ. */
+{ "setne", 0x26F97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setne<.f> a,limm,u6 0010011001111001F111uuuuuuAAAAAA. */
+{ "setne", 0x26797000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setne<.f> 0,limm,u6 0010011001111001F111uuuuuu111110. */
+{ "setne", 0x2679703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setne<.f><.cc> 0,limm,u6 0010011011111001F111uuuuuu1QQQQQ. */
+{ "setne", 0x26F97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setne<.f> 0,limm,s12 0010011010111001F111ssssssSSSSSS. */
+{ "setne", 0x26B97000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setne<.f> a,limm,limm 0010011000111001F111111110AAAAAA. */
+{ "setne", 0x26397F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setne<.f> 0,limm,limm 0010011000111001F111111110111110. */
+{ "setne", 0x26397FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setne<.f><.cc> 0,limm,limm 0010011011111001F1111111100QQQQQ. */
+{ "setne", 0x26F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* setnel<.f> RA,RB,RC 01011bbb00111001FBBBccccccaaaaaa. */
+{ "setnel", 0x58390000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* setnel<.f> 0,RB,RC 01011bbb00111001FBBBcccccc111110. */
+{ "setnel", 0x5839003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* setnel<.f><.cc> RB,RB,RC 01011bbb11111001FBBBcccccc0QQQQQ. */
+{ "setnel", 0x58F90000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* setnel<.f> RA,RB,u6 01011bbb01111001FBBBuuuuuuaaaaaa. */
+{ "setnel", 0x58790000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* setnel<.f> 0,RB,u6 01011bbb01111001FBBBuuuuuu111110. */
+{ "setnel", 0x5879003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* setnel<.f><.cc> RB,RB,u6 01011bbb11111001FBBBuuuuuu1QQQQQ. */
+{ "setnel", 0x58F90020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* setnel<.f> RB,RB,s12 01011bbb10111001FBBBssssssSSSSSS. */
+{ "setnel", 0x58B90000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* setnel<.f> RA,ximm,RC 0101110000111001F111ccccccaaaaaa. */
+{ "setnel", 0x5C397000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* setnel<.f> RA,RB,ximm 01011bbb00111001FBBB111100aaaaaa. */
+{ "setnel", 0x58390F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* setnel<.f> 0,ximm,RC 0101110000111001F111cccccc111110. */
+{ "setnel", 0x5C39703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* setnel<.f> 0,RB,ximm 01011bbb00111001FBBB111100111110. */
+{ "setnel", 0x58390F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* setnel<.f><.cc> 0,ximm,RC 0101110011111001F111cccccc0QQQQQ. */
+{ "setnel", 0x5CF97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* setnel<.f><.cc> RB,RB,ximm 01011bbb11111001FBBB1111000QQQQQ. */
+{ "setnel", 0x58F90F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* setnel<.f> RA,ximm,u6 0101110001111001F111uuuuuuaaaaaa. */
+{ "setnel", 0x5C797000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setnel<.f> 0,ximm,u6 0101110001111001F111uuuuuu111110. */
+{ "setnel", 0x5C79703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* setnel<.f><.cc> 0,ximm,u6 0101110011111001F111uuuuuu1QQQQQ. */
+{ "setnel", 0x5CF97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setnel<.f> RA,limm,RC 0101111000111001F111ccccccaaaaaa. */
+{ "setnel", 0x5E397000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* setnel<.f> RA,RB,limm 01011bbb00111001FBBB111110aaaaaa. */
+{ "setnel", 0x58390F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* setnel<.f> 0,limm,RC 0101111000111001F111cccccc111110. */
+{ "setnel", 0x5E39703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* setnel<.f> 0,RB,limm 01011bbb00111001FBBB111110111110. */
+{ "setnel", 0x58390FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* setnel<.f><.cc> 0,limm,RC 0101111011111001F111cccccc0QQQQQ. */
+{ "setnel", 0x5EF97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* setnel<.f><.cc> RB,RB,limm 01011bbb11111001FBBB1111100QQQQQ. */
+{ "setnel", 0x58F90F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* setnel<.f> RA,limm,u6 0101111001111001F111uuuuuuaaaaaa. */
+{ "setnel", 0x5E797000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setnel<.f> 0,limm,u6 0101111001111001F111uuuuuu111110. */
+{ "setnel", 0x5E79703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* setnel<.f><.cc> 0,limm,u6 0101111011111001F111uuuuuu1QQQQQ. */
+{ "setnel", 0x5EF97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* setnel<.f> 0,ximm,s12 0101110010111001F111ssssssSSSSSS. */
+{ "setnel", 0x5CB97000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* setnel<.f> 0,limm,s12 0101111010111001F111ssssssSSSSSS. */
+{ "setnel", 0x5EB97000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* setnel<.f> RA,ximm,ximm 0101110000111001F111111100aaaaaa. */
+{ "setnel", 0x5C397F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* setnel<.f> 0,ximm,ximm 0101110000111001F111111100111110. */
+{ "setnel", 0x5C397F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* setnel<.f><.cc> 0,ximm,ximm 0101110011111001F1111111000QQQQQ. */
+{ "setnel", 0x5CF97F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* setnel<.f> RA,limm,limm 0101111000111001F111111110aaaaaa. */
+{ "setnel", 0x5E397F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* setnel<.f> 0,limm,limm 0101111000111001F111111110111110. */
+{ "setnel", 0x5E397FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* setnel<.f><.cc> 0,limm,limm 0101111011111001F1111111100QQQQQ. */
+{ "setnel", 0x5EF97F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sexb<.f> b,c 00100bbb00101111FBBBCCCCCC000101. */
+{ "sexb", 0x202F0005, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexb<.f> 0,c 0010011000101111F111CCCCCC000101. */
+{ "sexb", 0x262F7005, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexb<.f> b,u6 00100bbb01101111FBBBuuuuuu000101. */
+{ "sexb", 0x206F0005, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexb<.f> 0,u6 0010011001101111F111uuuuuu000101. */
+{ "sexb", 0x266F7005, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexb<.f> b,limm 00100bbb00101111FBBB111110000101. */
+{ "sexb", 0x202F0F85, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexb<.f> 0,limm 0010011000101111F111111110000101. */
+{ "sexb", 0x262F7F85, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexbl<.f> RB,RC 01011bbb00101111FBBBcccccc000101. */
+{ "sexbl", 0x582F0005, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexbl<.f> 0,RC 0101111000101111F111cccccc000101. */
+{ "sexbl", 0x5E2F7005, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexbl<.f> RB,u6 01011bbb01101111FBBBuuuuuu000101. */
+{ "sexbl", 0x586F0005, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexbl<.f> 0,u6 0101111001101111F111uuuuuu000101. */
+{ "sexbl", 0x5E6F7005, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexbl<.f> RB,ximm 01011bbb00101111FBBB111100000101. */
+{ "sexbl", 0x582F0F05, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* sexbl<.f> 0,ximm 0101111000101111F111111100000101. */
+{ "sexbl", 0x5E2F7F05, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* sexbl<.f> RB,limm 01011bbb00101111FBBB111110000101. */
+{ "sexbl", 0x582F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexbl<.f> 0,limm 0101111000101111F111111110000101. */
+{ "sexbl", 0x5E2F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexb_s b,c 01111bbbccc01101. */
+{ "sexb_s", 0x0000780D, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* sexh<.f> b,c 00100bbb00101111FBBBCCCCCC000110. */
+{ "sexh", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexh<.f> 0,c 0010011000101111F111CCCCCC000110. */
+{ "sexh", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexh<.f> b,u6 00100bbb01101111FBBBuuuuuu000110. */
+{ "sexh", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexh<.f> 0,u6 0010011001101111F111uuuuuu000110. */
+{ "sexh", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexh<.f> b,limm 00100bbb00101111FBBB111110000110. */
+{ "sexh", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexh<.f> 0,limm 0010011000101111F111111110000110. */
+{ "sexh", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexhl<.f> RB,RC 01011bbb00101111FBBBcccccc000110. */
+{ "sexhl", 0x582F0006, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexhl<.f> 0,RC 0101111000101111F111cccccc000110. */
+{ "sexhl", 0x5E2F7006, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexhl<.f> RB,u6 01011bbb01101111FBBBuuuuuu000110. */
+{ "sexhl", 0x586F0006, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexhl<.f> 0,u6 0101111001101111F111uuuuuu000110. */
+{ "sexhl", 0x5E6F7006, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexhl<.f> RB,ximm 01011bbb00101111FBBB111100000110. */
+{ "sexhl", 0x582F0F06, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* sexhl<.f> 0,ximm 0101111000101111F111111100000110. */
+{ "sexhl", 0x5E2F7F06, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* sexhl<.f> RB,limm 01011bbb00101111FBBB111110000110. */
+{ "sexhl", 0x582F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexhl<.f> 0,limm 0101111000101111F111111110000110. */
+{ "sexhl", 0x5E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sexh_s b,c 01111bbbccc01110. */
+{ "sexh_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RC_S }, { 0 }},
+
+/* sexwl<.f> RB,RC 01011bbb00101111FBBBcccccc000111. */
+{ "sexwl", 0x582F0007, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* sexwl<.f> 0,RC 0101111000101111F111cccccc000111. */
+{ "sexwl", 0x5E2F7007, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* sexwl<.f> RB,u6 01011bbb01101111FBBBuuuuuu000111. */
+{ "sexwl", 0x586F0007, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* sexwl<.f> 0,u6 0101111001101111F111uuuuuu000111. */
+{ "sexwl", 0x5E6F7007, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sexwl<.f> RB,ximm 01011bbb00101111FBBB111100000111. */
+{ "sexwl", 0x582F0F07, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* sexwl<.f> 0,ximm 0101111000101111F111111100000111. */
+{ "sexwl", 0x5E2F7F07, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* sexwl<.f> RB,limm 01011bbb00101111FBBB111110000111. */
+{ "sexwl", 0x582F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* sexwl<.f> 0,limm 0101111000101111F111111110000111. */
+{ "sexwl", 0x5E2F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* sleep c 00100001001011110000CCCCCC111111. */
+{ "sleep", 0x212F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { RC }, { 0 }},
+
+/* sleep u6 00100001011011110000uuuuuu111111. */
+{ "sleep", 0x216F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { UIMM6_20 }, { 0 }},
+
+/* sleep limm 00100001001011110000111110111111. */
+{ "sleep", 0x212F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { LIMM }, { 0 }},
+
+/* sleep 00100001011011110000000000111111. */
+{ "sleep", 0x216F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* sqrt<.f> b,c 00101bbb00101111FBBBCCCCCC110000. */
+{ "sqrt", 0x282F0030, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { C_F }},
+
+/* sqrt<.f> 0,c 0010111000101111F111CCCCCC110000. */
+{ "sqrt", 0x2E2F7030, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* sqrt<.f> b,u6 00101bbb01101111FBBBuuuuuu110000. */
+{ "sqrt", 0x286F0030, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { C_F }},
+
+/* sqrt<.f> 0,u6 0010111001101111F111uuuuuu110000. */
+{ "sqrt", 0x2E6F7030, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sqrt<.f> b,limm 00101bbb00101111FBBB111110110000. */
+{ "sqrt", 0x282F0FB0, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { C_F }},
+
+/* sqrt<.f> 0,limm 0010111000101111F111111110110000. */
+{ "sqrt", 0x2E2F7FB0, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* sqrtf<.f> b,c 00101bbb00101111FBBBCCCCCC110001. */
+{ "sqrtf", 0x282F0031, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { C_F }},
+
+/* sqrtf<.f> 0,c 0010111000101111F111CCCCCC110001. */
+{ "sqrtf", 0x2E2F7031, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { C_F }},
+
+/* sqrtf<.f> b,u6 00101bbb01101111FBBBuuuuuu110001. */
+{ "sqrtf", 0x286F0031, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { C_F }},
+
+/* sqrtf<.f> 0,u6 0010111001101111F111uuuuuu110001. */
+{ "sqrtf", 0x2E6F7031, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* sqrtf<.f> b,limm 00101bbb00101111FBBB111110110001. */
+{ "sqrtf", 0x282F0FB1, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { C_F }},
+
+/* sqrtf<.f> 0,limm 0010111000101111F111111110110001. */
+{ "sqrtf", 0x2E2F7FB1, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { C_F }},
+
+/* sr b,c 00100bbb00101011RBBBCCCCCCRRRRRR. */
+{ "sr", 0x202B0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* sr b,u6 00100bbb01101011RBBBuuuuuu000000. */
+{ "sr", 0x206B0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* sr b,s12 00100bbb10101011RBBBssssssSSSSSS. */
+{ "sr", 0x20AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* sr limm,c 0010011000101011R111CCCCCCRRRRRR. */
+{ "sr", 0x262B7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* sr b,limm 00100bbb00101011RBBB111110RRRRRR. */
+{ "sr", 0x202B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* sr limm,u6 0010011001101011R111uuuuuu000000. */
+{ "sr", 0x266B7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* sr limm,s12 0010011010101011R111ssssssSSSSSS. */
+{ "sr", 0x26AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* sr limm,limm 0010011000101011R111111110RRRRRR. */
+{ "sr", 0x262B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 }},
+
+/* srl RB,RC 01011bbb001010110BBBccccccRRRRRR. */
+{ "srl", 0x582B0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, RC, BRAKETdup }, { 0 }},
+
+/* srl RB,u6 01011bbb011010110BBBuuuuuuRRRRRR. */
+{ "srl", 0x586B0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, UIMM6_20, BRAKETdup }, { 0 }},
+
+/* srl RB,s12 01011bbb101010110BBBssssssSSSSSS. */
+{ "srl", 0x58AB0000, 0xF8FF8000, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, SIMM12_20, BRAKETdup }, { 0 }},
+
+/* srl RB,ximm 01011bbb001010110BBB111100RRRRRR. */
+{ "srl", 0x582B0F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, XIMM, BRAKETdup }, { 0 }},
+
+/* srl RB,limm 01011bbb001010110BBB111110RRRRRR. */
+{ "srl", 0x582B0F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, AUXREG, NONE, { RB_CHK, BRAKET, LIMM, BRAKETdup }, { 0 }},
+
+/* st<zz><.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaaZZ0. */
+{ "st", 0x18000000, 0xF8FF8001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, RB, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<zz><.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaaZZ1. */
+{ "st", 0x18000001, 0xF8FF8001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<zz><.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZ0. */
+{ "st", 0x18000000, 0xF8000001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<zz><.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaaZZ1. */
+{ "st", 0x18000001, 0xF8000001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<zz><.di> c,limm 00011110000000000111CCCCCCDRRZZ0. */
+{ "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_ZZ29, C_DI26 }},
+
+/* st<zz><.di> w6,limm 00011110000000000111wwwwwwDRRZZ1. */
+{ "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_ZZ29, C_DI26 }},
+
+/* st<zz><.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110DaaZZ0. */
+{ "st", 0x18000F80, 0xF8000FC1, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<zz><.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaaZZ1. */
+{ "st", 0x1E007001, 0xFF007001, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* st<zz><.di><.aa> limm,limm,s9 00011110ssssssssS111111110DaaZZ0. */
+{ "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }},
+
+/* stb_sZZ_B c,b,u5 10101bbbcccuuuuu. */
+{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { C_ZZ_B }},
+
+/* stb_sZZ_B b,SP,u7 11000bbb011uuuuu. */
+{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { C_ZZ_B }},
+
+/* stdl<.aa> c,b 00011bbb000000000BBBCCCCCC1aa111 -> stdl c,[b,s9=0] */
+/* stdl<.aa> c,b,s9 00011bbbssssssssSBBBCCCCCC1aa111 -> stdl c,[b,s9] */
+/* stdl<.as> c,ximm 00011100000000000111CCCCCC1aa111 -> stdl c,[b=60,s9=0] */
+/* stdl<.as> c,limm 00011110000000000111CCCCCC1aa111 -> stdl c,[b=62,s9=0] */
+/* stdl<.aa> ximm,b,s9 00011bbbssssssssSBBB1111001aa111 -> stdl c=60,[b,s9] */
+/* stdl<.aa> limm,b,s9 00011bbbssssssssSBBB1111101aa111 -> stdl c=62,[b,s9] */
+{ "stdl", 0x18000027, 0xF8FF8027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_AA27 }},
+{ "stdl", 0x18000027, 0xF8000027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }},
+
+{ "stdl", 0x1C007027, 0xFFFFF027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, XIMM, BRAKETdup }, { C_AS27 }},
+{ "stdl", 0x1E007027, 0xFFFFF027, ARC_OPCODE_ARC64, STORE, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_AS27 }},
+
+{ "stdl", 0x18000F27, 0xF8000FE7, ARC_OPCODE_ARC64, STORE, NONE, { XIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }},
+{ "stdl", 0x18000FA7, 0xF8000FE7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA27 }},
+
+/* sth_sZZ_H c,b,u6 10110bbbcccuuuuu. */
+{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_ZZ_H }},
+
+/* stlZZ_L<.aa> c,b 00011bbb000000000BBBCCCCCC0aa111. */
+{ "stl", 0x18000007, 0xF8FF8027, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, RB, BRAKETdup }, { C_ZZ_L, C_AA27 }},
+
+/* stlZZ_L<.aa> c,b,s9 00011bbbssssssssSBBBCCCCCC0aa111. */
+{ "stl", 0x18000007, 0xF8000027, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
+
+/* stlZZ_L c,ximm 00011100000000000111CCCCCC000111. */
+{ "stl", 0x1C007007, 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, XIMM, BRAKETdup }, { C_ZZ_L }},
+
+/* stlZZ_L c,limm 00011110000000000111CCCCCC000111. */
+{ "stl", 0x1E007007, 0xFFFFF03F, ARC_OPCODE_ARC64, STORE, NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_ZZ_L }},
+
+/* stlZZ_L<.aa> limm,b,s9 00011bbbssssssssSBBB1111100aa111. */
+{ "stl", 0x18000F87, 0xF8000FE7, ARC_OPCODE_ARC64, STORE, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ_L, C_AA27 }},
+
+/* st_s b,SP,u7 11000bbb010uuuuu. */
+{ "st_s", 0x0000C040, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* st_s c,b,u7 10100bbbcccuuuuu. */
+{ "st_s", 0x0000A000, 0x0000F800, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+/* st_s R0,GP,s11 01010SSSSSS10sss. */
+{ "st_s", 0x00005010, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, STORE, CD2, { R0_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }},
+
+/* sub<.f> a,b,c 00100bbb00000010FBBBCCCCCCAAAAAA. */
+{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub<.f> 0,b,c 00100bbb00000010FBBBCCCCCC111110. */
+{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub<.f><.cc> b,b,c 00100bbb11000010FBBBCCCCCC0QQQQQ. */
+{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
+{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub<.f> 0,b,u6 00100bbb01000010FBBBuuuuuu111110. */
+{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub<.f><.cc> b,b,u6 00100bbb11000010FBBBuuuuuu1QQQQQ. */
+{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub<.f> b,b,s12 00100bbb10000010FBBBssssssSSSSSS. */
+{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub<.f> a,limm,c 0010011000000010F111CCCCCCAAAAAA. */
+{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
+{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub<.f> 0,limm,c 0010011000000010F111CCCCCC111110. */
+{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub<.f> 0,b,limm 00100bbb00000010FBBB111110111110. */
+{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub<.f><.cc> b,b,limm 00100bbb11000010FBBB1111100QQQQQ. */
+{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub<.f><.cc> 0,limm,c 0010011011000010F111CCCCCC0QQQQQ. */
+{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub<.f> a,limm,u6 0010011001000010F111uuuuuuAAAAAA. */
+{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub<.f> 0,limm,u6 0010011001000010F111uuuuuu111110. */
+{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub<.f><.cc> 0,limm,u6 0010011011000010F111uuuuuu1QQQQQ. */
+{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub<.f> 0,limm,s12 0010011010000010F111ssssssSSSSSS. */
+{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub<.f> a,limm,limm 0010011000000010F111111110AAAAAA. */
+{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub<.f> 0,limm,limm 0010011000000010F111111110111110. */
+{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub<.f><.cc> 0,limm,limm 0010011011000010F1111111100QQQQQ. */
+{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub1<.f> a,b,c 00100bbb00010111FBBBCCCCCCAAAAAA. */
+{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub1<.f> 0,b,c 00100bbb00010111FBBBCCCCCC111110. */
+{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub1<.f><.cc> b,b,c 00100bbb11010111FBBBCCCCCC0QQQQQ. */
+{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub1<.f> a,b,u6 00100bbb01010111FBBBuuuuuuAAAAAA. */
+{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub1<.f> 0,b,u6 00100bbb01010111FBBBuuuuuu111110. */
+{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub1<.f><.cc> b,b,u6 00100bbb11010111FBBBuuuuuu1QQQQQ. */
+{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1<.f> b,b,s12 00100bbb10010111FBBBssssssSSSSSS. */
+{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub1<.f> a,limm,c 0010011000010111F111CCCCCCAAAAAA. */
+{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub1<.f> a,b,limm 00100bbb00010111FBBB111110AAAAAA. */
+{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub1<.f> 0,limm,c 0010011000010111F111CCCCCC111110. */
+{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub1<.f> 0,b,limm 00100bbb00010111FBBB111110111110. */
+{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub1<.f><.cc> b,b,limm 00100bbb11010111FBBB1111100QQQQQ. */
+{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub1<.f><.cc> 0,limm,c 0010011011010111F111CCCCCC0QQQQQ. */
+{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub1<.f> a,limm,u6 0010011001010111F111uuuuuuAAAAAA. */
+{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub1<.f> 0,limm,u6 0010011001010111F111uuuuuu111110. */
+{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub1<.f><.cc> 0,limm,u6 0010011011010111F111uuuuuu1QQQQQ. */
+{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1<.f> 0,limm,s12 0010011010010111F111ssssssSSSSSS. */
+{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub1<.f> a,limm,limm 0010011000010111F111111110AAAAAA. */
+{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub1<.f> 0,limm,limm 0010011000010111F111111110111110. */
+{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub1<.f><.cc> 0,limm,limm 0010011011010111F1111111100QQQQQ. */
+{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,RB,RC 01011bbb00010111FBBBccccccaaaaaa. */
+{ "sub1l", 0x58170000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub1l<.f> 0,RB,RC 01011bbb00010111FBBBcccccc111110. */
+{ "sub1l", 0x5817003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub1l<.f><.cc> RB,RB,RC 01011bbb11010111FBBBcccccc0QQQQQ. */
+{ "sub1l", 0x58D70000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,RB,u6 01011bbb01010111FBBBuuuuuuaaaaaa. */
+{ "sub1l", 0x58570000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f> 0,RB,u6 01011bbb01010111FBBBuuuuuu111110. */
+{ "sub1l", 0x5857003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f><.cc> RB,RB,u6 01011bbb11010111FBBBuuuuuu1QQQQQ. */
+{ "sub1l", 0x58D70020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1l<.f> RB,RB,s12 01011bbb10010111FBBBssssssSSSSSS. */
+{ "sub1l", 0x58970000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub1l<.f> RA,ximm,RC 0101110000010111F111ccccccaaaaaa. */
+{ "sub1l", 0x5C177000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* sub1l<.f> RA,RB,ximm 01011bbb00010111FBBB111100aaaaaa. */
+{ "sub1l", 0x58170F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* sub1l<.f> 0,ximm,RC 0101110000010111F111cccccc111110. */
+{ "sub1l", 0x5C17703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* sub1l<.f> 0,RB,ximm 01011bbb00010111FBBB111100111110. */
+{ "sub1l", 0x58170F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* sub1l<.f><.cc> 0,ximm,RC 0101110011010111F111cccccc0QQQQQ. */
+{ "sub1l", 0x5CD77000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* sub1l<.f><.cc> RB,RB,ximm 01011bbb11010111FBBB1111000QQQQQ. */
+{ "sub1l", 0x58D70F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,ximm,u6 0101110001010111F111uuuuuuaaaaaa. */
+{ "sub1l", 0x5C577000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f> 0,ximm,u6 0101110001010111F111uuuuuu111110. */
+{ "sub1l", 0x5C57703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f><.cc> 0,ximm,u6 0101110011010111F111uuuuuu1QQQQQ. */
+{ "sub1l", 0x5CD77020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,limm,RC 0101111000010111F111ccccccaaaaaa. */
+{ "sub1l", 0x5E177000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub1l<.f> RA,RB,limm 01011bbb00010111FBBB111110aaaaaa. */
+{ "sub1l", 0x58170F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub1l<.f> 0,limm,RC 0101111000010111F111cccccc111110. */
+{ "sub1l", 0x5E17703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub1l<.f> 0,RB,limm 01011bbb00010111FBBB111110111110. */
+{ "sub1l", 0x58170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub1l<.f><.cc> 0,limm,RC 0101111011010111F111cccccc0QQQQQ. */
+{ "sub1l", 0x5ED77000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub1l<.f><.cc> RB,RB,limm 01011bbb11010111FBBB1111100QQQQQ. */
+{ "sub1l", 0x58D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,limm,u6 0101111001010111F111uuuuuuaaaaaa. */
+{ "sub1l", 0x5E577000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f> 0,limm,u6 0101111001010111F111uuuuuu111110. */
+{ "sub1l", 0x5E57703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub1l<.f><.cc> 0,limm,u6 0101111011010111F111uuuuuu1QQQQQ. */
+{ "sub1l", 0x5ED77020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub1l<.f> 0,ximm,s12 0101110010010111F111ssssssSSSSSS. */
+{ "sub1l", 0x5C977000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* sub1l<.f> 0,limm,s12 0101111010010111F111ssssssSSSSSS. */
+{ "sub1l", 0x5E977000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub1l<.f> RA,ximm,ximm 0101110000010111F111111100aaaaaa. */
+{ "sub1l", 0x5C177F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* sub1l<.f> 0,ximm,ximm 0101110000010111F111111100111110. */
+{ "sub1l", 0x5C177F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* sub1l<.f><.cc> 0,ximm,ximm 0101110011010111F1111111000QQQQQ. */
+{ "sub1l", 0x5CD77F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* sub1l<.f> RA,limm,limm 0101111000010111F111111110aaaaaa. */
+{ "sub1l", 0x5E177F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub1l<.f> 0,limm,limm 0101111000010111F111111110111110. */
+{ "sub1l", 0x5E177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub1l<.f><.cc> 0,limm,limm 0101111011010111F1111111100QQQQQ. */
+{ "sub1l", 0x5ED77F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub2<.f> a,b,c 00100bbb00011000FBBBCCCCCCAAAAAA. */
+{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub2<.f> 0,b,c 00100bbb00011000FBBBCCCCCC111110. */
+{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub2<.f><.cc> b,b,c 00100bbb11011000FBBBCCCCCC0QQQQQ. */
+{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub2<.f> a,b,u6 00100bbb01011000FBBBuuuuuuAAAAAA. */
+{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub2<.f> 0,b,u6 00100bbb01011000FBBBuuuuuu111110. */
+{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub2<.f><.cc> b,b,u6 00100bbb11011000FBBBuuuuuu1QQQQQ. */
+{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2<.f> b,b,s12 00100bbb10011000FBBBssssssSSSSSS. */
+{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub2<.f> a,limm,c 0010011000011000F111CCCCCCAAAAAA. */
+{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub2<.f> a,b,limm 00100bbb00011000FBBB111110AAAAAA. */
+{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub2<.f> 0,limm,c 0010011000011000F111CCCCCC111110. */
+{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub2<.f> 0,b,limm 00100bbb00011000FBBB111110111110. */
+{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub2<.f><.cc> b,b,limm 00100bbb11011000FBBB1111100QQQQQ. */
+{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub2<.f><.cc> 0,limm,c 0010011011011000F111CCCCCC0QQQQQ. */
+{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub2<.f> a,limm,u6 0010011001011000F111uuuuuuAAAAAA. */
+{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub2<.f> 0,limm,u6 0010011001011000F111uuuuuu111110. */
+{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub2<.f><.cc> 0,limm,u6 0010011011011000F111uuuuuu1QQQQQ. */
+{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2<.f> 0,limm,s12 0010011010011000F111ssssssSSSSSS. */
+{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub2<.f> a,limm,limm 0010011000011000F111111110AAAAAA. */
+{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub2<.f> 0,limm,limm 0010011000011000F111111110111110. */
+{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub2<.f><.cc> 0,limm,limm 0010011011011000F1111111100QQQQQ. */
+{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,RB,RC 01011bbb00011000FBBBccccccaaaaaa. */
+{ "sub2l", 0x58180000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub2l<.f> 0,RB,RC 01011bbb00011000FBBBcccccc111110. */
+{ "sub2l", 0x5818003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub2l<.f><.cc> RB,RB,RC 01011bbb11011000FBBBcccccc0QQQQQ. */
+{ "sub2l", 0x58D80000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,RB,u6 01011bbb01011000FBBBuuuuuuaaaaaa. */
+{ "sub2l", 0x58580000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f> 0,RB,u6 01011bbb01011000FBBBuuuuuu111110. */
+{ "sub2l", 0x5858003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f><.cc> RB,RB,u6 01011bbb11011000FBBBuuuuuu1QQQQQ. */
+{ "sub2l", 0x58D80020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2l<.f> RB,RB,s12 01011bbb10011000FBBBssssssSSSSSS. */
+{ "sub2l", 0x58980000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub2l<.f> RA,ximm,RC 0101110000011000F111ccccccaaaaaa. */
+{ "sub2l", 0x5C187000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* sub2l<.f> RA,RB,ximm 01011bbb00011000FBBB111100aaaaaa. */
+{ "sub2l", 0x58180F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* sub2l<.f> 0,ximm,RC 0101110000011000F111cccccc111110. */
+{ "sub2l", 0x5C18703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* sub2l<.f> 0,RB,ximm 01011bbb00011000FBBB111100111110. */
+{ "sub2l", 0x58180F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* sub2l<.f><.cc> 0,ximm,RC 0101110011011000F111cccccc0QQQQQ. */
+{ "sub2l", 0x5CD87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* sub2l<.f><.cc> RB,RB,ximm 01011bbb11011000FBBB1111000QQQQQ. */
+{ "sub2l", 0x58D80F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,ximm,u6 0101110001011000F111uuuuuuaaaaaa. */
+{ "sub2l", 0x5C587000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f> 0,ximm,u6 0101110001011000F111uuuuuu111110. */
+{ "sub2l", 0x5C58703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f><.cc> 0,ximm,u6 0101110011011000F111uuuuuu1QQQQQ. */
+{ "sub2l", 0x5CD87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,limm,RC 0101111000011000F111ccccccaaaaaa. */
+{ "sub2l", 0x5E187000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub2l<.f> RA,RB,limm 01011bbb00011000FBBB111110aaaaaa. */
+{ "sub2l", 0x58180F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub2l<.f> 0,limm,RC 0101111000011000F111cccccc111110. */
+{ "sub2l", 0x5E18703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub2l<.f> 0,RB,limm 01011bbb00011000FBBB111110111110. */
+{ "sub2l", 0x58180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub2l<.f><.cc> 0,limm,RC 0101111011011000F111cccccc0QQQQQ. */
+{ "sub2l", 0x5ED87000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub2l<.f><.cc> RB,RB,limm 01011bbb11011000FBBB1111100QQQQQ. */
+{ "sub2l", 0x58D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,limm,u6 0101111001011000F111uuuuuuaaaaaa. */
+{ "sub2l", 0x5E587000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f> 0,limm,u6 0101111001011000F111uuuuuu111110. */
+{ "sub2l", 0x5E58703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub2l<.f><.cc> 0,limm,u6 0101111011011000F111uuuuuu1QQQQQ. */
+{ "sub2l", 0x5ED87020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub2l<.f> 0,ximm,s12 0101110010011000F111ssssssSSSSSS. */
+{ "sub2l", 0x5C987000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* sub2l<.f> 0,limm,s12 0101111010011000F111ssssssSSSSSS. */
+{ "sub2l", 0x5E987000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub2l<.f> RA,ximm,ximm 0101110000011000F111111100aaaaaa. */
+{ "sub2l", 0x5C187F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* sub2l<.f> 0,ximm,ximm 0101110000011000F111111100111110. */
+{ "sub2l", 0x5C187F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* sub2l<.f><.cc> 0,ximm,ximm 0101110011011000F1111111000QQQQQ. */
+{ "sub2l", 0x5CD87F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* sub2l<.f> RA,limm,limm 0101111000011000F111111110aaaaaa. */
+{ "sub2l", 0x5E187F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub2l<.f> 0,limm,limm 0101111000011000F111111110111110. */
+{ "sub2l", 0x5E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub2l<.f><.cc> 0,limm,limm 0101111011011000F1111111100QQQQQ. */
+{ "sub2l", 0x5ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub3<.f> a,b,c 00100bbb00011001FBBBCCCCCCAAAAAA. */
+{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub3<.f> 0,b,c 00100bbb00011001FBBBCCCCCC111110. */
+{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub3<.f><.cc> b,b,c 00100bbb11011001FBBBCCCCCC0QQQQQ. */
+{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub3<.f> a,b,u6 00100bbb01011001FBBBuuuuuuAAAAAA. */
+{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub3<.f> 0,b,u6 00100bbb01011001FBBBuuuuuu111110. */
+{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub3<.f><.cc> b,b,u6 00100bbb11011001FBBBuuuuuu1QQQQQ. */
+{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3<.f> b,b,s12 00100bbb10011001FBBBssssssSSSSSS. */
+{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub3<.f> a,limm,c 0010011000011001F111CCCCCCAAAAAA. */
+{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub3<.f> a,b,limm 00100bbb00011001FBBB111110AAAAAA. */
+{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub3<.f> 0,limm,c 0010011000011001F111CCCCCC111110. */
+{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub3<.f> 0,b,limm 00100bbb00011001FBBB111110111110. */
+{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub3<.f><.cc> b,b,limm 00100bbb11011001FBBB1111100QQQQQ. */
+{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub3<.f><.cc> 0,limm,c 0010011011011001F111CCCCCC0QQQQQ. */
+{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub3<.f> a,limm,u6 0010011001011001F111uuuuuuAAAAAA. */
+{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub3<.f> 0,limm,u6 0010011001011001F111uuuuuu111110. */
+{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub3<.f><.cc> 0,limm,u6 0010011011011001F111uuuuuu1QQQQQ. */
+{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3<.f> 0,limm,s12 0010011010011001F111ssssssSSSSSS. */
+{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub3<.f> a,limm,limm 0010011000011001F111111110AAAAAA. */
+{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub3<.f> 0,limm,limm 0010011000011001F111111110111110. */
+{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub3<.f><.cc> 0,limm,limm 0010011011011001F1111111100QQQQQ. */
+{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,RB,RC 01011bbb00011001FBBBccccccaaaaaa. */
+{ "sub3l", 0x58190000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* sub3l<.f> 0,RB,RC 01011bbb00011001FBBBcccccc111110. */
+{ "sub3l", 0x5819003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* sub3l<.f><.cc> RB,RB,RC 01011bbb11011001FBBBcccccc0QQQQQ. */
+{ "sub3l", 0x58D90000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,RB,u6 01011bbb01011001FBBBuuuuuuaaaaaa. */
+{ "sub3l", 0x58590000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f> 0,RB,u6 01011bbb01011001FBBBuuuuuu111110. */
+{ "sub3l", 0x5859003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f><.cc> RB,RB,u6 01011bbb11011001FBBBuuuuuu1QQQQQ. */
+{ "sub3l", 0x58D90020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3l<.f> RB,RB,s12 01011bbb10011001FBBBssssssSSSSSS. */
+{ "sub3l", 0x58990000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* sub3l<.f> RA,ximm,RC 0101110000011001F111ccccccaaaaaa. */
+{ "sub3l", 0x5C197000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* sub3l<.f> RA,RB,ximm 01011bbb00011001FBBB111100aaaaaa. */
+{ "sub3l", 0x58190F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* sub3l<.f> 0,ximm,RC 0101110000011001F111cccccc111110. */
+{ "sub3l", 0x5C19703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* sub3l<.f> 0,RB,ximm 01011bbb00011001FBBB111100111110. */
+{ "sub3l", 0x58190F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* sub3l<.f><.cc> 0,ximm,RC 0101110011011001F111cccccc0QQQQQ. */
+{ "sub3l", 0x5CD97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* sub3l<.f><.cc> RB,RB,ximm 01011bbb11011001FBBB1111000QQQQQ. */
+{ "sub3l", 0x58D90F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,ximm,u6 0101110001011001F111uuuuuuaaaaaa. */
+{ "sub3l", 0x5C597000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f> 0,ximm,u6 0101110001011001F111uuuuuu111110. */
+{ "sub3l", 0x5C59703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f><.cc> 0,ximm,u6 0101110011011001F111uuuuuu1QQQQQ. */
+{ "sub3l", 0x5CD97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,limm,RC 0101111000011001F111ccccccaaaaaa. */
+{ "sub3l", 0x5E197000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* sub3l<.f> RA,RB,limm 01011bbb00011001FBBB111110aaaaaa. */
+{ "sub3l", 0x58190F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* sub3l<.f> 0,limm,RC 0101111000011001F111cccccc111110. */
+{ "sub3l", 0x5E19703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* sub3l<.f> 0,RB,limm 01011bbb00011001FBBB111110111110. */
+{ "sub3l", 0x58190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* sub3l<.f><.cc> 0,limm,RC 0101111011011001F111cccccc0QQQQQ. */
+{ "sub3l", 0x5ED97000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* sub3l<.f><.cc> RB,RB,limm 01011bbb11011001FBBB1111100QQQQQ. */
+{ "sub3l", 0x58D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,limm,u6 0101111001011001F111uuuuuuaaaaaa. */
+{ "sub3l", 0x5E597000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f> 0,limm,u6 0101111001011001F111uuuuuu111110. */
+{ "sub3l", 0x5E59703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* sub3l<.f><.cc> 0,limm,u6 0101111011011001F111uuuuuu1QQQQQ. */
+{ "sub3l", 0x5ED97020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* sub3l<.f> 0,ximm,s12 0101110010011001F111ssssssSSSSSS. */
+{ "sub3l", 0x5C997000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* sub3l<.f> 0,limm,s12 0101111010011001F111ssssssSSSSSS. */
+{ "sub3l", 0x5E997000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* sub3l<.f> RA,ximm,ximm 0101110000011001F111111100aaaaaa. */
+{ "sub3l", 0x5C197F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* sub3l<.f> 0,ximm,ximm 0101110000011001F111111100111110. */
+{ "sub3l", 0x5C197F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* sub3l<.f><.cc> 0,ximm,ximm 0101110011011001F1111111000QQQQQ. */
+{ "sub3l", 0x5CD97F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* sub3l<.f> RA,limm,limm 0101111000011001F111111110aaaaaa. */
+{ "sub3l", 0x5E197F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* sub3l<.f> 0,limm,limm 0101111000011001F111111110111110. */
+{ "sub3l", 0x5E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* sub3l<.f><.cc> 0,limm,limm 0101111011011001F1111111100QQQQQ. */
+{ "sub3l", 0x5ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* subl<.f> RA,RB,RC 01011bbb00000010FBBBccccccaaaaaa. */
+{ "subl", 0x58020000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* subl<.f> 0,RB,RC 01011bbb00000010FBBBcccccc111110. */
+{ "subl", 0x5802003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* subl<.f><.cc> RB,RB,RC 01011bbb11000010FBBBcccccc0QQQQQ. */
+{ "subl", 0x58C20000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* subl<.f> RA,RB,u6 01011bbb01000010FBBBuuuuuuaaaaaa. */
+{ "subl", 0x58420000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* subl<.f> 0,RB,u6 01011bbb01000010FBBBuuuuuu111110. */
+{ "subl", 0x5842003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* subl<.f><.cc> RB,RB,u6 01011bbb11000010FBBBuuuuuu1QQQQQ. */
+{ "subl", 0x58C20020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* subl<.f> RB,RB,s12 01011bbb10000010FBBBssssssSSSSSS. */
+{ "subl", 0x58820000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* subl<.f> RA,ximm,RC 0101110000000010F111ccccccaaaaaa. */
+{ "subl", 0x5C027000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* subl<.f> RA,RB,ximm 01011bbb00000010FBBB111100aaaaaa. */
+{ "subl", 0x58020F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* subl<.f> 0,ximm,RC 0101110000000010F111cccccc111110. */
+{ "subl", 0x5C02703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* subl<.f> 0,RB,ximm 01011bbb00000010FBBB111100111110. */
+{ "subl", 0x58020F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* subl<.f><.cc> 0,ximm,RC 0101110011000010F111cccccc0QQQQQ. */
+{ "subl", 0x5CC27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* subl<.f><.cc> RB,RB,ximm 01011bbb11000010FBBB1111000QQQQQ. */
+{ "subl", 0x58C20F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* subl<.f> RA,ximm,u6 0101110001000010F111uuuuuuaaaaaa. */
+{ "subl", 0x5C427000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* subl<.f> 0,ximm,u6 0101110001000010F111uuuuuu111110. */
+{ "subl", 0x5C42703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* subl<.f><.cc> 0,ximm,u6 0101110011000010F111uuuuuu1QQQQQ. */
+{ "subl", 0x5CC27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* subl<.f> RA,limm,RC 0101111000000010F111ccccccaaaaaa. */
+{ "subl", 0x5E027000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* subl<.f> RA,RB,limm 01011bbb00000010FBBB111110aaaaaa. */
+{ "subl", 0x58020F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* subl<.f> 0,limm,RC 0101111000000010F111cccccc111110. */
+{ "subl", 0x5E02703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* subl<.f> 0,RB,limm 01011bbb00000010FBBB111110111110. */
+{ "subl", 0x58020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* subl<.f><.cc> 0,limm,RC 0101111011000010F111cccccc0QQQQQ. */
+{ "subl", 0x5EC27000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* subl<.f><.cc> RB,RB,limm 01011bbb11000010FBBB1111100QQQQQ. */
+{ "subl", 0x58C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* subl<.f> RA,limm,u6 0101111001000010F111uuuuuuaaaaaa. */
+{ "subl", 0x5E427000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* subl<.f> 0,limm,u6 0101111001000010F111uuuuuu111110. */
+{ "subl", 0x5E42703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* subl<.f><.cc> 0,limm,u6 0101111011000010F111uuuuuu1QQQQQ. */
+{ "subl", 0x5EC27020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* subl<.f> 0,ximm,s12 0101110010000010F111ssssssSSSSSS. */
+{ "subl", 0x5C827000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* subl<.f> 0,limm,s12 0101111010000010F111ssssssSSSSSS. */
+{ "subl", 0x5E827000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* subl<.f> RA,ximm,ximm 0101110000000010F111111100aaaaaa. */
+{ "subl", 0x5C027F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* subl<.f> 0,ximm,ximm 0101110000000010F111111100111110. */
+{ "subl", 0x5C027F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* subl<.f><.cc> 0,ximm,ximm 0101110011000010F1111111000QQQQQ. */
+{ "subl", 0x5CC27F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* subl<.f> RA,limm,limm 0101111000000010F111111110aaaaaa. */
+{ "subl", 0x5E027F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* subl<.f> 0,limm,limm 0101111000000010F111111110111110. */
+{ "subl", 0x5E027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* subl<.f><.cc> 0,limm,limm 0101111011000010F1111111100QQQQQ. */
+{ "subl", 0x5EC27F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* subl_s SP,SP,u9 11000UU1101uuuuu. */
+{ "subl_s", 0x0000C1A0, 0x0000F9E0, ARC_OPCODE_ARC64, ARITH, NONE, { SP_S, SP_Sdup, UIMM9_A32_11_S }, { 0 }},
+
+/* subl_s b,b,c 01111bbbccc00011. */
+{ "subl_s", 0x00007803, 0x0000F81F, ARC_OPCODE_ARC64, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* subs<.f> a,b,c 00101bbb00000111FBBBCCCCCCAAAAAA. */
+{ "subs", 0x28070000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* subs<.f> 0,b,c 00101bbb00000111FBBBCCCCCC111110. */
+{ "subs", 0x2807003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* subs<.f><.cc> b,b,c 00101bbb11000111FBBBCCCCCC0QQQQQ. */
+{ "subs", 0x28C70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* subs<.f> a,b,u6 00101bbb01000111FBBBuuuuuuAAAAAA. */
+{ "subs", 0x28470000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* subs<.f> 0,b,u6 00101bbb01000111FBBBuuuuuu111110. */
+{ "subs", 0x2847003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* subs<.f><.cc> b,b,u6 00101bbb11000111FBBBuuuuuu1QQQQQ. */
+{ "subs", 0x28C70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* subs<.f> b,b,s12 00101bbb10000111FBBBssssssSSSSSS. */
+{ "subs", 0x28870000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA. */
+{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* subs<.f> a,b,limm 00101bbb00000111FBBB111110AAAAAA. */
+{ "subs", 0x28070F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* subs<.f> 0,limm,c 0010111000000111F111CCCCCC111110. */
+{ "subs", 0x2E07703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* subs<.f> 0,b,limm 00101bbb00000111FBBB111110111110. */
+{ "subs", 0x28070FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA. */
+{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* subs<.f><.cc> b,b,limm 00101bbb11000111FBBB1111100QQQQQ. */
+{ "subs", 0x28C70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* subs<.f><.cc> 0,limm,c 0010111011000111F111CCCCCC0QQQQQ. */
+{ "subs", 0x2EC77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* subs<.f> a,limm,u6 0010111001000111F111uuuuuuAAAAAA. */
+{ "subs", 0x2E477000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* subs<.f> 0,limm,u6 0010111001000111F111uuuuuu111110. */
+{ "subs", 0x2E47703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* subs<.f><.cc> 0,limm,u6 0010111011000111F111uuuuuu1QQQQQ. */
+{ "subs", 0x2EC77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* subs<.f> 0,limm,s12 0010111010000111F111ssssssSSSSSS. */
+{ "subs", 0x2E877000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* subs<.f> a,limm,limm 0010111000000111F111111110AAAAAA. */
+{ "subs", 0x2E077F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* subs<.f> 0,limm,limm 0010111000000111F111111110111110. */
+{ "subs", 0x2E077FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* subs<.f><.cc> 0,limm,limm 0010111011000111F1111111100QQQQQ. */
+{ "subs", 0x2EC77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* sub_s.NE b,b,b 01111bbb11000000. */
+{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB_S, RB_Sdup, RB_Sdup }, { C_NE }},
+
+/* sub_s b,b,c 01111bbbccc00010. */
+{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
+/* sub_s a,b,c 01001bbbccc10aaa. */
+{ "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, CD2, { RA_S, RB_S, RC_S }, { 0 }},
+
+/* sub_s c,b,u3 01101bbbccc01uuu. */
+{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+
+/* sub_s b,b,u5 10111bbb011uuuuu. */
+{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, SUB, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
+
+/* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000. */
+{ "swap", 0x282F0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* swap<.f> 0,c 0010111000101111F111CCCCCC000000. */
+{ "swap", 0x2E2F7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* swap<.f> b,u6 00101bbb01101111FBBBuuuuuu000000. */
+{ "swap", 0x286F0000, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* swap<.f> 0,u6 0010111001101111F111uuuuuu000000. */
+{ "swap", 0x2E6F7000, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* swap<.f> b,limm 00101bbb00101111FBBB111110000000. */
+{ "swap", 0x282F0F80, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* swap<.f> 0,limm 0010111000101111F111111110000000. */
+{ "swap", 0x2E2F7F80, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* swape<.f> b,c 00101bbb00101111FBBBCCCCCC001001. */
+{ "swape", 0x282F0009, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, RC }, { C_F }},
+
+/* swape<.f> 0,c 0010111000101111F111CCCCCC001001. */
+{ "swape", 0x2E2F7009, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, RC }, { C_F }},
+
+/* swape<.f> b,u6 00101bbb01101111FBBBuuuuuu001001. */
+{ "swape", 0x286F0009, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }},
+
+/* swape<.f> 0,u6 0010111001101111F111uuuuuu001001. */
+{ "swape", 0x2E6F7009, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }},
+
+/* swape<.f> b,limm 00101bbb00101111FBBB111110001001. */
+{ "swape", 0x282F0F89, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { RB, LIMM }, { C_F }},
+
+/* swape<.f> 0,limm 0010111000101111F111111110001001. */
+{ "swape", 0x2E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SWAP, { ZA, LIMM }, { C_F }},
+
+/* swapel<.f> RB,RC 01011bbb00101111FBBBcccccc101001. */
+{ "swapel", 0x582F0029, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* swapel<.f> 0,RC 0101111000101111F111cccccc101001. */
+{ "swapel", 0x5E2F7029, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* swapel<.f> RB,u6 01011bbb01101111FBBBuuuuuu101001. */
+{ "swapel", 0x586F0029, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* swapel<.f> 0,u6 0101111001101111F111uuuuuu101001. */
+{ "swapel", 0x5E6F7029, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* swapel<.f> RB,ximm 01011bbb00101111FBBB111100101001. */
+{ "swapel", 0x582F0F29, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* swapel<.f> 0,ximm 0101111000101111F111111100101001. */
+{ "swapel", 0x5E2F7F29, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* swapel<.f> RB,limm 01011bbb00101111FBBB111110101001. */
+{ "swapel", 0x582F0FA9, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* swapel<.f> 0,limm 0101111000101111F111111110101001. */
+{ "swapel", 0x5E2F7FA9, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* swapl<.f> RB,RC 01011bbb00101111FBBBcccccc100000. */
+{ "swapl", 0x582F0020, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_F }},
+
+/* swapl<.f> 0,RC 0101111000101111F111cccccc100000. */
+{ "swapl", 0x5E2F7020, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RC }, { C_F }},
+
+/* swapl<.f> RB,u6 01011bbb01101111FBBBuuuuuu100000. */
+{ "swapl", 0x586F0020, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_F }},
+
+/* swapl<.f> 0,u6 0101111001101111F111uuuuuu100000. */
+{ "swapl", 0x5E6F7020, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }},
+
+/* swapl<.f> RB,ximm 01011bbb00101111FBBB111100100000. */
+{ "swapl", 0x582F0F20, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_F }},
+
+/* swapl<.f> 0,ximm 0101111000101111F111111100100000. */
+{ "swapl", 0x5E2F7F20, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM }, { C_F }},
+
+/* swapl<.f> RB,limm 01011bbb00101111FBBB111110100000. */
+{ "swapl", 0x582F0FA0, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_F }},
+
+/* swapl<.f> 0,limm 0101111000101111F111111110100000. */
+{ "swapl", 0x5E2F7FA0, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM }, { C_F }},
+
+/* swi 00100010011011110000000000111111. */
+{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* swi_s 0111101011100000. */
+{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* swi_s u6 01111uuuuuu11111. */
+{ "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
+
+/* sync 00100011011011110000000000111111. */
+{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, CONTROL, NONE, { 0 }, { 0 }},
+
+/* trap_s u6 01111uuuuuu11110. */
+{ "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
+
+/* tst b,c 00100bbb000010111BBBCCCCCCRRRRRR. */
+{ "tst", 0x200B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { 0 }},
+
+/* tst<.cc> b,c 00100bbb110010111BBBCCCCCC0QQQQQ. */
+{ "tst", 0x20CB8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RC }, { C_CC }},
+
+/* tst b,u6 00100bbb010010111BBBuuuuuuRRRRRR. */
+{ "tst", 0x204B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* tst<.cc> b,u6 00100bbb110010111BBBuuuuuu1QQQQQ. */
+{ "tst", 0x20CB8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* tst b,s12 00100bbb100010111BBBssssssSSSSSS. */
+{ "tst", 0x208B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* tst limm,c 00100110000010111111CCCCCCRRRRRR. */
+{ "tst", 0x260BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, RC }, { 0 }},
+
+/* tst b,limm 00100bbb000010111BBB111110RRRRRR. */
+{ "tst", 0x200B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { 0 }},
+
+/* tst<.cc> b,limm 00100bbb110010111BBB1111100QQQQQ. */
+{ "tst", 0x20CB8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, LIMM }, { C_CC }},
+
+/* tst<.cc> limm,c 00100110110010111111CCCCCC0QQQQQ. */
+{ "tst", 0x26CBF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, RC }, { C_CC }},
+
+/* tst limm,u6 00100110010010111111uuuuuuRRRRRR. */
+{ "tst", 0x264BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }},
+
+/* tst<.cc> limm,u6 00100110110010111111uuuuuu1QQQQQ. */
+{ "tst", 0x26CBF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, UIMM6_20 }, { C_CC }},
+
+/* tst limm,s12 00100110100010111111ssssssSSSSSS. */
+{ "tst", 0x268BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, SIMM12_20 }, { 0 }},
+
+/* tst limm,limm 00100110000010111111111110RRRRRR. */
+{ "tst", 0x260BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }},
+
+/* tst<.cc> limm,limm 001001101100101111111111100QQQQQ. */
+{ "tst", 0x26CBFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { LIMM, LIMMdup }, { C_CC }},
+
+/* tstl RB,RC 01011bbb000010111BBBccccccRRRRRR. */
+{ "tstl", 0x580B8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { 0 }},
+
+/* tstl<.cc> RB,RC 01011bbb110010111BBBcccccc0QQQQQ. */
+{ "tstl", 0x58CB8000, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RC }, { C_CC }},
+
+/* tstl RB,u6 01011bbb010010111BBBuuuuuuRRRRRR. */
+{ "tstl", 0x584B8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { 0 }},
+
+/* tstl<.cc> RB,u6 01011bbb110010111BBBuuuuuu1QQQQQ. */
+{ "tstl", 0x58CB8020, 0xF8FF8020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }},
+
+/* tstl RB,s12 01011bbb100010111BBBssssssSSSSSS. */
+{ "tstl", 0x588B8000, 0xF8FF8000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, SIMM12_20 }, { 0 }},
+
+/* tstl RB,ximm 01011bbb000010111BBB111100RRRRRR. */
+{ "tstl", 0x580B8F00, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { 0 }},
+
+/* tstl<.cc> RB,ximm 01011bbb110010111BBB1111000QQQQQ. */
+{ "tstl", 0x58CB8F00, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, XIMM }, { C_CC }},
+
+/* tstl RB,limm 01011bbb000010111BBB111110RRRRRR. */
+{ "tstl", 0x580B8F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { 0 }},
+
+/* tstl<.cc> RB,limm 01011bbb110010111BBB1111100QQQQQ. */
+{ "tstl", 0x58CB8F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, LIMM }, { C_CC }},
+
+/* tst_s b,c 01111bbbccc01011. */
+{ "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
+
+/* unimp_s 0111100111100000. */
+{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* vabs2h b,c 00101bbb001011110BBBCCCCCC101000. */
+{ "vabs2h", 0x282F0028, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vabs2h 0,c 00101110001011110111CCCCCC101000. */
+{ "vabs2h", 0x2E2F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vabs2h b,u6 00101bbb011011110BBBuuuuuu101000. */
+{ "vabs2h", 0x286F0028, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vabs2h 0,u6 00101110011011110111uuuuuu101000. */
+{ "vabs2h", 0x2E6F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vabs2h b,limm 00101bbb001011110BBB111110101000. */
+{ "vabs2h", 0x282F0FA8, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vabs2h 0,limm 00101110001011110111111110101000. */
+{ "vabs2h", 0x2E2F7FA8, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vabss2h b,c 00101bbb001011110BBBCCCCCC101001. */
+{ "vabss2h", 0x282F0029, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vabss2h 0,c 00101110001011110111CCCCCC101001. */
+{ "vabss2h", 0x2E2F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vabss2h b,u6 00101bbb011011110BBBuuuuuu101001. */
+{ "vabss2h", 0x286F0029, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vabss2h 0,u6 00101110011011110111uuuuuu101001. */
+{ "vabss2h", 0x2E6F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vabss2h b,limm 00101bbb001011110BBB111110101001. */
+{ "vabss2h", 0x282F0FA9, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vabss2h 0,limm 00101110001011110111111110101001. */
+{ "vabss2h", 0x2E2F7FA9, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vadd2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA. */
+{ "vadd2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vadd2 0,b,c 00101bbb001111000BBBCCCCCC111110. */
+{ "vadd2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vadd2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ. */
+{ "vadd2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vadd2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA. */
+{ "vadd2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2 0,b,u6 00101bbb011111000BBBuuuuuu111110. */
+{ "vadd2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ. */
+{ "vadd2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd2 b,b,s12 00101bbb101111000BBBssssssSSSSSS. */
+{ "vadd2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd2 a,limm,c 00101110001111000111CCCCCCAAAAAA. */
+{ "vadd2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vadd2 a,b,limm 00101bbb001111000BBB111110AAAAAA. */
+{ "vadd2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vadd2 0,limm,c 00101110001111000111CCCCCC111110. */
+{ "vadd2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd2 0,b,limm 00101bbb001111000BBB111110111110. */
+{ "vadd2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ. */
+{ "vadd2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vadd2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ. */
+{ "vadd2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd2 a,limm,u6 00101110011111000111uuuuuuAAAAAA. */
+{ "vadd2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2 0,limm,u6 00101110011111000111uuuuuu111110. */
+{ "vadd2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ. */
+{ "vadd2", 0x2EFC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd2 0,limm,s12 00101110101111000111ssssssSSSSSS. */
+{ "vadd2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd2 a,limm,limm 00101110001111000111111110AAAAAA. */
+{ "vadd2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2 0,limm,limm 00101110001111000111111110111110. */
+{ "vadd2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ. */
+{ "vadd2", 0x2EFC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadd2h a,b,c 00101bbb000101000BBBCCCCCCAAAAAA. */
+{ "vadd2h", 0x28140000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vadd2h 0,b,c 00101bbb000101000BBBCCCCCC111110. */
+{ "vadd2h", 0x2814003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vadd2h<.cc> b,b,c 00101bbb110101000BBBCCCCCC0QQQQQ. */
+{ "vadd2h", 0x28D40000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vadd2h a,b,u6 00101bbb010101000BBBuuuuuuAAAAAA. */
+{ "vadd2h", 0x28540000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2h 0,b,u6 00101bbb010101000BBBuuuuuu111110. */
+{ "vadd2h", 0x2854003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd2h<.cc> b,b,u6 00101bbb110101000BBBuuuuuu1QQQQQ. */
+{ "vadd2h", 0x28D40020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd2h b,b,s12 00101bbb100101000BBBssssssSSSSSS. */
+{ "vadd2h", 0x28940000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd2h a,limm,c 00101110000101000111CCCCCCAAAAAA. */
+{ "vadd2h", 0x2E147000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vadd2h a,b,limm 00101bbb000101000BBB111110AAAAAA. */
+{ "vadd2h", 0x28140F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vadd2h 0,limm,c 00101110000101000111CCCCCC111110. */
+{ "vadd2h", 0x2E14703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd2h 0,b,limm 00101bbb000101000BBB111110111110. */
+{ "vadd2h", 0x28140FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd2h<.cc> b,b,limm 00101bbb110101000BBB1111100QQQQQ. */
+{ "vadd2h", 0x28D40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vadd2h<.cc> 0,limm,c 00101110110101000111CCCCCC0QQQQQ. */
+{ "vadd2h", 0x2ED47000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd2h a,limm,u6 00101110010101000111uuuuuuAAAAAA. */
+{ "vadd2h", 0x2E547000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2h 0,limm,u6 00101110010101000111uuuuuu111110. */
+{ "vadd2h", 0x2E54703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd2h<.cc> 0,limm,u6 00101110110101000111uuuuuu1QQQQQ. */
+{ "vadd2h", 0x2ED47020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd2h 0,limm,s12 00101110100101000111ssssssSSSSSS. */
+{ "vadd2h", 0x2E947000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd2h a,limm,limm 00101110000101000111111110AAAAAA. */
+{ "vadd2h", 0x2E147F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2h 0,limm,limm 00101110000101000111111110111110. */
+{ "vadd2h", 0x2E147FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd2h<.cc> 0,limm,limm 001011101101010001111111100QQQQQ. */
+{ "vadd2h", 0x2ED47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadd4b a,b,c 00101bbb001001000BBBCCCCCCAAAAAA. */
+{ "vadd4b", 0x28240000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vadd4b 0,b,c 00101bbb001001000BBBCCCCCC111110. */
+{ "vadd4b", 0x2824003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vadd4b<.cc> b,b,c 00101bbb111001000BBBCCCCCC0QQQQQ. */
+{ "vadd4b", 0x28E40000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vadd4b a,b,u6 00101bbb011001000BBBuuuuuuAAAAAA. */
+{ "vadd4b", 0x28640000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vadd4b 0,b,u6 00101bbb011001000BBBuuuuuu111110. */
+{ "vadd4b", 0x2864003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd4b<.cc> b,b,u6 00101bbb111001000BBBuuuuuu1QQQQQ. */
+{ "vadd4b", 0x28E40020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd4b b,b,s12 00101bbb101001000BBBssssssSSSSSS. */
+{ "vadd4b", 0x28A40000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd4b a,limm,c 00101110001001000111CCCCCCAAAAAA. */
+{ "vadd4b", 0x2E247000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vadd4b a,b,limm 00101bbb001001000BBB111110AAAAAA. */
+{ "vadd4b", 0x28240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vadd4b 0,limm,c 00101110011001000111CCCCCC111110. */
+{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd4b 0,b,limm 00101bbb001001000BBB111110111110. */
+{ "vadd4b", 0x28240FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd4b<.cc> b,b,limm 00101bbb111001000BBB1111100QQQQQ. */
+{ "vadd4b", 0x28E40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vadd4b<.cc> 0,limm,c 00101110111001000111CCCCCC0QQQQQ. */
+{ "vadd4b", 0x2EE47000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd4b a,limm,u6 00101110011001000111uuuuuuAAAAAA. */
+{ "vadd4b", 0x2E647000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd4b 0,limm,u6 00101110011001000111uuuuuu111110. */
+{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd4b<.cc> 0,limm,u6 00101110111001000111uuuuuu1QQQQQ. */
+{ "vadd4b", 0x2EE47020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd4b 0,limm,s12 00101110101001000111ssssssSSSSSS. */
+{ "vadd4b", 0x2EA47000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd4b a,limm,limm 00101110001001000111111110AAAAAA. */
+{ "vadd4b", 0x2E247F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vadd4b 0,limm,limm 00101110001001000111111110111110. */
+{ "vadd4b", 0x2E247FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd4b<.cc> 0,limm,limm 001011101110010001111111100QQQQQ. */
+{ "vadd4b", 0x2EE47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadd4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA. */
+{ "vadd4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vadd4h 0,b,c 00101bbb001110000BBBCCCCCC111110. */
+{ "vadd4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vadd4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ. */
+{ "vadd4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vadd4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA. */
+{ "vadd4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vadd4h 0,b,u6 00101bbb011110000BBBuuuuuu111110. */
+{ "vadd4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadd4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ. */
+{ "vadd4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadd4h b,b,s12 00101bbb101110000BBBssssssSSSSSS. */
+{ "vadd4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadd4h a,limm,c 00101110001110000111CCCCCCAAAAAA. */
+{ "vadd4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vadd4h a,b,limm 00101bbb001110000BBB111110AAAAAA. */
+{ "vadd4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vadd4h 0,limm,c 00101110001110000111CCCCCC111110. */
+{ "vadd4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadd4h 0,b,limm 00101bbb001110000BBB111110111110. */
+{ "vadd4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadd4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ. */
+{ "vadd4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vadd4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ. */
+{ "vadd4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadd4h a,limm,u6 00101110011110000111uuuuuuAAAAAA. */
+{ "vadd4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd4h 0,limm,u6 00101110011110000111uuuuuu111110. */
+{ "vadd4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadd4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ. */
+{ "vadd4h", 0x2EF87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadd4h 0,limm,s12 00101110101110000111ssssssSSSSSS. */
+{ "vadd4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadd4h a,limm,limm 00101110001110000111111110AAAAAA. */
+{ "vadd4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vadd4h 0,limm,limm 00101110001110000111111110111110. */
+{ "vadd4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadd4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ. */
+{ "vadd4h", 0x2EF87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadds2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA. */
+{ "vadds2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vadds2 0,b,c 00101bbb001111000BBBCCCCCC111110. */
+{ "vadds2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vadds2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ. */
+{ "vadds2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vadds2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA. */
+{ "vadds2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vadds2 0,b,u6 00101bbb011111000BBBuuuuuu111110. */
+{ "vadds2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadds2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ. */
+{ "vadds2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadds2 b,b,s12 00101bbb101111000BBBssssssSSSSSS. */
+{ "vadds2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadds2 a,limm,c 00101110001111000111CCCCCCAAAAAA. */
+{ "vadds2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vadds2 a,b,limm 00101bbb001111000BBB111110AAAAAA. */
+{ "vadds2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vadds2 0,limm,c 00101110001111000111CCCCCC111110. */
+{ "vadds2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadds2 0,b,limm 00101bbb001111000BBB111110111110. */
+{ "vadds2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadds2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ. */
+{ "vadds2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vadds2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ. */
+{ "vadds2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadds2 a,limm,u6 00101110011111000111uuuuuuAAAAAA. */
+{ "vadds2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadds2 0,limm,u6 00101110011111000111uuuuuu111110. */
+{ "vadds2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadds2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ. */
+{ "vadds2", 0x2EFC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadds2 0,limm,s12 00101110101111000111ssssssSSSSSS. */
+{ "vadds2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadds2 a,limm,limm 00101110001111000111111110AAAAAA. */
+{ "vadds2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vadds2 0,limm,limm 00101110001111000111111110111110. */
+{ "vadds2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadds2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ. */
+{ "vadds2", 0x2EFC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadds2h a,b,c 00101bbb000101001BBBCCCCCCAAAAAA. */
+{ "vadds2h", 0x28148000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vadds2h 0,b,c 00101bbb000101001BBBCCCCCC111110. */
+{ "vadds2h", 0x2814803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vadds2h<.cc> b,b,c 00101bbb110101001BBBCCCCCC0QQQQQ. */
+{ "vadds2h", 0x28D48000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vadds2h a,b,u6 00101bbb010101001BBBuuuuuuAAAAAA. */
+{ "vadds2h", 0x28548000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vadds2h 0,b,u6 00101bbb010101001BBBuuuuuu111110. */
+{ "vadds2h", 0x2854803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadds2h<.cc> b,b,u6 00101bbb110101001BBBuuuuuu1QQQQQ. */
+{ "vadds2h", 0x28D48020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadds2h b,b,s12 00101bbb100101001BBBssssssSSSSSS. */
+{ "vadds2h", 0x28948000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadds2h a,limm,c 00101110000101001111CCCCCCAAAAAA. */
+{ "vadds2h", 0x2E14F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vadds2h a,b,limm 00101bbb000101001BBB111110AAAAAA. */
+{ "vadds2h", 0x28148F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vadds2h 0,limm,c 00101110000101001111CCCCCC111110. */
+{ "vadds2h", 0x2E14F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vadds2h 0,b,limm 00101bbb000101001BBB111110111110. */
+{ "vadds2h", 0x28148FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vadds2h<.cc> b,b,limm 00101bbb110101001BBB1111100QQQQQ. */
+{ "vadds2h", 0x28D48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vadds2h<.cc> 0,limm,c 00101110110101001111CCCCCC0QQQQQ. */
+{ "vadds2h", 0x2ED4F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadds2h a,limm,u6 00101110010101001111uuuuuuAAAAAA. */
+{ "vadds2h", 0x2E54F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadds2h 0,limm,u6 00101110010101001111uuuuuu111110. */
+{ "vadds2h", 0x2E54F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadds2h<.cc> 0,limm,u6 00101110110101001111uuuuuu1QQQQQ. */
+{ "vadds2h", 0x2ED4F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadds2h 0,limm,s12 00101110100101001111ssssssSSSSSS. */
+{ "vadds2h", 0x2E94F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadds2h a,limm,limm 00101110000101001111111110AAAAAA. */
+{ "vadds2h", 0x2E14FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vadds2h 0,limm,limm 00101110000101001111111110111110. */
+{ "vadds2h", 0x2E14FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadds2h<.cc> 0,limm,limm 001011101101010011111111100QQQQQ. */
+{ "vadds2h", 0x2ED4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vadds4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA. */
+{ "vadds4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vadds4h 0,b,c 00101bbb001110000BBBCCCCCC111110. */
+{ "vadds4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vadds4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ. */
+{ "vadds4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vadds4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA. */
+{ "vadds4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vadds4h 0,b,u6 00101bbb011110000BBBuuuuuu111110. */
+{ "vadds4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vadds4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ. */
+{ "vadds4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vadds4h b,b,s12 00101bbb101110000BBBssssssSSSSSS. */
+{ "vadds4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vadds4h a,limm,c 00101110001110000111CCCCCCAAAAAA. */
+{ "vadds4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vadds4h a,b,limm 00101bbb001110000BBB111110AAAAAA. */
+{ "vadds4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vadds4h 0,limm,c 00101110001110000111CCCCCC111110. */
+{ "vadds4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vadds4h 0,b,limm 00101bbb001110000BBB111110111110. */
+{ "vadds4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vadds4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ. */
+{ "vadds4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vadds4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ. */
+{ "vadds4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vadds4h a,limm,u6 00101110011110000111uuuuuuAAAAAA. */
+{ "vadds4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadds4h 0,limm,u6 00101110011110000111uuuuuu111110. */
+{ "vadds4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vadds4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ. */
+{ "vadds4h", 0x2EF87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vadds4h 0,limm,s12 00101110101110000111ssssssSSSSSS. */
+{ "vadds4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vadds4h a,limm,limm 00101110001110000111111110AAAAAA. */
+{ "vadds4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vadds4h 0,limm,limm 00101110001110000111111110111110. */
+{ "vadds4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vadds4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ. */
+{ "vadds4h", 0x2EF87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsub a,b,c 00101bbb001111100BBBCCCCCCAAAAAA. */
+{ "vaddsub", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vaddsub 0,b,c 00101bbb001111100BBBCCCCCC111110. */
+{ "vaddsub", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsub<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ. */
+{ "vaddsub", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vaddsub a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA. */
+{ "vaddsub", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub 0,b,u6 00101bbb011111100BBBuuuuuu111110. */
+{ "vaddsub", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ. */
+{ "vaddsub", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsub b,b,s12 00101bbb101111100BBBssssssSSSSSS. */
+{ "vaddsub", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsub a,limm,c 00101110001111100111CCCCCCAAAAAA. */
+{ "vaddsub", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vaddsub a,b,limm 00101bbb001111100BBB111110AAAAAA. */
+{ "vaddsub", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vaddsub 0,limm,c 00101110001111100111CCCCCC111110. */
+{ "vaddsub", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsub 0,b,limm 00101bbb001111100BBB111110111110. */
+{ "vaddsub", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsub<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ. */
+{ "vaddsub", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vaddsub<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ. */
+{ "vaddsub", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsub a,limm,u6 00101110011111100111uuuuuuAAAAAA. */
+{ "vaddsub", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub 0,limm,u6 00101110011111100111uuuuuu111110. */
+{ "vaddsub", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ. */
+{ "vaddsub", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsub 0,limm,s12 00101110101111100111ssssssSSSSSS. */
+{ "vaddsub", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsub a,limm,limm 00101110001111100111111110AAAAAA. */
+{ "vaddsub", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub 0,limm,limm 00101110001111100111111110111110. */
+{ "vaddsub", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub<.cc> 0,limm,limm 001011101111111001111111100QQQQQ. */
+{ "vaddsub", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsub2h a,b,c 00101bbb000101100BBBCCCCCCAAAAAA. */
+{ "vaddsub2h", 0x28160000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vaddsub2h 0,b,c 00101bbb000101100BBBCCCCCC111110. */
+{ "vaddsub2h", 0x2816003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsub2h<.cc> b,b,c 00101bbb110101100BBBCCCCCC0QQQQQ. */
+{ "vaddsub2h", 0x28D60000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vaddsub2h a,b,u6 00101bbb010101100BBBuuuuuuAAAAAA. */
+{ "vaddsub2h", 0x28560000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h 0,b,u6 00101bbb010101100BBBuuuuuu111110. */
+{ "vaddsub2h", 0x2856003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h<.cc> b,b,u6 00101bbb110101100BBBuuuuuu1QQQQQ. */
+{ "vaddsub2h", 0x28D60020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsub2h b,b,s12 00101bbb100101100BBBssssssSSSSSS. */
+{ "vaddsub2h", 0x28960000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsub2h a,limm,c 00101110000101100111CCCCCCAAAAAA. */
+{ "vaddsub2h", 0x2E167000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vaddsub2h a,b,limm 00101bbb000101100BBB111110AAAAAA. */
+{ "vaddsub2h", 0x28160F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vaddsub2h 0,limm,c 00101110000101100111CCCCCC111110. */
+{ "vaddsub2h", 0x2E16703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsub2h 0,b,limm 00101bbb000101100BBB111110111110. */
+{ "vaddsub2h", 0x28160FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsub2h<.cc> b,b,limm 00101bbb110101100BBB1111100QQQQQ. */
+{ "vaddsub2h", 0x28D60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vaddsub2h<.cc> 0,limm,c 00101110110101100111CCCCCC0QQQQQ. */
+{ "vaddsub2h", 0x2ED67000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsub2h a,limm,u6 00101110010101100111uuuuuuAAAAAA. */
+{ "vaddsub2h", 0x2E567000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h 0,limm,u6 00101110010101100111uuuuuu111110. */
+{ "vaddsub2h", 0x2E56703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub2h<.cc> 0,limm,u6 00101110110101100111uuuuuu1QQQQQ. */
+{ "vaddsub2h", 0x2ED67020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsub2h 0,limm,s12 00101110100101100111ssssssSSSSSS. */
+{ "vaddsub2h", 0x2E967000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsub2h a,limm,limm 00101110000101100111111110AAAAAA. */
+{ "vaddsub2h", 0x2E167F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub2h 0,limm,limm 00101110000101100111111110111110. */
+{ "vaddsub2h", 0x2E167FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub2h<.cc> 0,limm,limm 001011101101011001111111100QQQQQ. */
+{ "vaddsub2h", 0x2ED67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsub4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA. */
+{ "vaddsub4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vaddsub4h 0,b,c 00101bbb001110100BBBCCCCCC111110. */
+{ "vaddsub4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsub4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ. */
+{ "vaddsub4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vaddsub4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA. */
+{ "vaddsub4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h 0,b,u6 00101bbb011110100BBBuuuuuu111110. */
+{ "vaddsub4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ. */
+{ "vaddsub4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsub4h b,b,s12 00101bbb101110100BBBssssssSSSSSS. */
+{ "vaddsub4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsub4h a,limm,c 00101110001110100111CCCCCCAAAAAA. */
+{ "vaddsub4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vaddsub4h a,b,limm 00101bbb001110100BBB111110AAAAAA. */
+{ "vaddsub4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vaddsub4h 0,limm,c 00101110001110100111CCCCCC111110. */
+{ "vaddsub4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsub4h 0,b,limm 00101bbb001110100BBB111110111110. */
+{ "vaddsub4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsub4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ. */
+{ "vaddsub4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vaddsub4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ. */
+{ "vaddsub4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsub4h a,limm,u6 00101110011110100111uuuuuuAAAAAA. */
+{ "vaddsub4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h 0,limm,u6 00101110011110100111uuuuuu111110. */
+{ "vaddsub4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsub4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ. */
+{ "vaddsub4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsub4h 0,limm,s12 00101110101110100111ssssssSSSSSS. */
+{ "vaddsub4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsub4h a,limm,limm 00101110001110100111111110AAAAAA. */
+{ "vaddsub4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub4h 0,limm,limm 00101110001110100111111110111110. */
+{ "vaddsub4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsub4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ. */
+{ "vaddsub4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsubs a,b,c 00101bbb001111100BBBCCCCCCAAAAAA. */
+{ "vaddsubs", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vaddsubs 0,b,c 00101bbb001111100BBBCCCCCC111110. */
+{ "vaddsubs", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsubs<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ. */
+{ "vaddsubs", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vaddsubs a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA. */
+{ "vaddsubs", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsubs 0,b,u6 00101bbb011111100BBBuuuuuu111110. */
+{ "vaddsubs", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsubs<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ. */
+{ "vaddsubs", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsubs b,b,s12 00101bbb101111100BBBssssssSSSSSS. */
+{ "vaddsubs", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsubs a,limm,c 00101110001111100111CCCCCCAAAAAA. */
+{ "vaddsubs", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vaddsubs a,b,limm 00101bbb001111100BBB111110AAAAAA. */
+{ "vaddsubs", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vaddsubs 0,limm,c 00101110001111100111CCCCCC111110. */
+{ "vaddsubs", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsubs 0,b,limm 00101bbb001111100BBB111110111110. */
+{ "vaddsubs", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsubs<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ. */
+{ "vaddsubs", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vaddsubs<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ. */
+{ "vaddsubs", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsubs a,limm,u6 00101110011111100111uuuuuuAAAAAA. */
+{ "vaddsubs", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsubs 0,limm,u6 00101110011111100111uuuuuu111110. */
+{ "vaddsubs", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsubs<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ. */
+{ "vaddsubs", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsubs 0,limm,s12 00101110101111100111ssssssSSSSSS. */
+{ "vaddsubs", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsubs a,limm,limm 00101110001111100111111110AAAAAA. */
+{ "vaddsubs", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsubs 0,limm,limm 00101110001111100111111110111110. */
+{ "vaddsubs", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsubs<.cc> 0,limm,limm 001011101111111001111111100QQQQQ. */
+{ "vaddsubs", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsubs2h a,b,c 00101bbb000101101BBBCCCCCCAAAAAA. */
+{ "vaddsubs2h", 0x28168000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vaddsubs2h 0,b,c 00101bbb000101101BBBCCCCCC111110. */
+{ "vaddsubs2h", 0x2816803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vaddsubs2h<.cc> b,b,c 00101bbb110101101BBBCCCCCC0QQQQQ. */
+{ "vaddsubs2h", 0x28D68000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vaddsubs2h a,b,u6 00101bbb010101101BBBuuuuuuAAAAAA. */
+{ "vaddsubs2h", 0x28568000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsubs2h 0,b,u6 00101bbb010101101BBBuuuuuu111110. */
+{ "vaddsubs2h", 0x2856803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsubs2h<.cc> b,b,u6 00101bbb110101101BBBuuuuuu1QQQQQ. */
+{ "vaddsubs2h", 0x28D68020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsubs2h b,b,s12 00101bbb100101101BBBssssssSSSSSS. */
+{ "vaddsubs2h", 0x28968000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsubs2h a,limm,c 00101110000101101111CCCCCCAAAAAA. */
+{ "vaddsubs2h", 0x2E16F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vaddsubs2h a,b,limm 00101bbb000101101BBB111110AAAAAA. */
+{ "vaddsubs2h", 0x28168F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vaddsubs2h 0,limm,c 00101110000101101111CCCCCC111110. */
+{ "vaddsubs2h", 0x2E16F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsubs2h 0,b,limm 00101bbb000101101BBB111110111110. */
+{ "vaddsubs2h", 0x28168FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsubs2h<.cc> b,b,limm 00101bbb110101101BBB1111100QQQQQ. */
+{ "vaddsubs2h", 0x28D68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vaddsubs2h<.cc> 0,limm,c 00101110110101101111CCCCCC0QQQQQ. */
+{ "vaddsubs2h", 0x2ED6F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsubs2h a,limm,u6 00101110010101101111uuuuuuAAAAAA. */
+{ "vaddsubs2h", 0x2E56F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsubs2h 0,limm,u6 00101110010101101111uuuuuu111110. */
+{ "vaddsubs2h", 0x2E56F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsubs2h<.cc> 0,limm,u6 00101110110101101111uuuuuu1QQQQQ. */
+{ "vaddsubs2h", 0x2ED6F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsubs2h 0,limm,s12 00101110100101101111ssssssSSSSSS. */
+{ "vaddsubs2h", 0x2E96F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsubs2h a,limm,limm 00101110000101101111111110AAAAAA. */
+{ "vaddsubs2h", 0x2E16FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsubs2h 0,limm,limm 00101110000101101111111110111110. */
+{ "vaddsubs2h", 0x2E16FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsubs2h<.cc> 0,limm,limm 001011101101011011111111100QQQQQ. */
+{ "vaddsubs2h", 0x2ED6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vaddsubs4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA. */
+{ "vaddsubs4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vaddsubs4h 0,b,c 00101bbb001110100BBBCCCCCC111110. */
+{ "vaddsubs4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vaddsubs4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ. */
+{ "vaddsubs4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vaddsubs4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA. */
+{ "vaddsubs4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsubs4h 0,b,u6 00101bbb011110100BBBuuuuuu111110. */
+{ "vaddsubs4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vaddsubs4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ. */
+{ "vaddsubs4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vaddsubs4h b,b,s12 00101bbb101110100BBBssssssSSSSSS. */
+{ "vaddsubs4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vaddsubs4h a,limm,c 00101110001110100111CCCCCCAAAAAA. */
+{ "vaddsubs4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vaddsubs4h a,b,limm 00101bbb001110100BBB111110AAAAAA. */
+{ "vaddsubs4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vaddsubs4h 0,limm,c 00101110001110100111CCCCCC111110. */
+{ "vaddsubs4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vaddsubs4h 0,b,limm 00101bbb001110100BBB111110111110. */
+{ "vaddsubs4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vaddsubs4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ. */
+{ "vaddsubs4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vaddsubs4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ. */
+{ "vaddsubs4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vaddsubs4h a,limm,u6 00101110011110100111uuuuuuAAAAAA. */
+{ "vaddsubs4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsubs4h 0,limm,u6 00101110011110100111uuuuuu111110. */
+{ "vaddsubs4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vaddsubs4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ. */
+{ "vaddsubs4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vaddsubs4h 0,limm,s12 00101110101110100111ssssssSSSSSS. */
+{ "vaddsubs4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vaddsubs4h a,limm,limm 00101110001110100111111110AAAAAA. */
+{ "vaddsubs4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsubs4h 0,limm,limm 00101110001110100111111110111110. */
+{ "vaddsubs4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vaddsubs4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ. */
+{ "vaddsubs4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* valgn2h a,b,c 00101bbb000011010BBBCCCCCCAAAAAA. */
+{ "valgn2h", 0x280D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* valgn2h 0,b,c 00101bbb000011010BBBCCCCCC111110. */
+{ "valgn2h", 0x280D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* valgn2h<.cc> b,b,c 00101bbb110011010BBBCCCCCC0QQQQQ. */
+{ "valgn2h", 0x28CD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* valgn2h a,b,u6 00101bbb010011010BBBuuuuuuAAAAAA. */
+{ "valgn2h", 0x284D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* valgn2h 0,b,u6 00101bbb010011010BBBuuuuuu111110. */
+{ "valgn2h", 0x284D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* valgn2h<.cc> b,b,u6 00101bbb110011010BBBuuuuuu1QQQQQ. */
+{ "valgn2h", 0x28CD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* valgn2h b,b,s12 00101bbb100011010BBBssssssSSSSSS. */
+{ "valgn2h", 0x288D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* valgn2h a,limm,c 00101110000011010111CCCCCCAAAAAA. */
+{ "valgn2h", 0x2E0D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* valgn2h a,b,limm 00101bbb000011010BBB111110AAAAAA. */
+{ "valgn2h", 0x280D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* valgn2h 0,limm,c 00101110000011010111CCCCCC111110. */
+{ "valgn2h", 0x2E0D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* valgn2h 0,b,limm 00101bbb000011010BBB111110111110. */
+{ "valgn2h", 0x280D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* valgn2h<.cc> b,b,limm 00101bbb110011010BBB1111100QQQQQ. */
+{ "valgn2h", 0x28CD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* valgn2h<.cc> 0,limm,c 00101110110011010111CCCCCC0QQQQQ. */
+{ "valgn2h", 0x2ECD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* valgn2h a,limm,u6 00101110010011010111uuuuuuAAAAAA. */
+{ "valgn2h", 0x2E4D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* valgn2h 0,limm,u6 00101110010011010111uuuuuu111110. */
+{ "valgn2h", 0x2E4D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* valgn2h<.cc> 0,limm,u6 00101110110011010111uuuuuu1QQQQQ. */
+{ "valgn2h", 0x2ECD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* valgn2h 0,limm,s12 00101110100011010111ssssssSSSSSS. */
+{ "valgn2h", 0x2E8D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* valgn2h a,limm,limm 00101110000011010111111110AAAAAA. */
+{ "valgn2h", 0x2E0D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* valgn2h 0,limm,limm 00101110000011010111111110111110. */
+{ "valgn2h", 0x2E0D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* valgn2h<.cc> 0,limm,limm 001011101100110101111111100QQQQQ. */
+{ "valgn2h", 0x2ECD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vasl2h a,b,c 00101bbb001000010BBBCCCCCCAAAAAA. */
+{ "vasl2h", 0x28210000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vasl2h 0,b,c 00101bbb001000010BBBCCCCCC111110. */
+{ "vasl2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vasl2h<.cc> b,b,c 00101bbb111000010BBBCCCCCC0QQQQQ. */
+{ "vasl2h", 0x28E10000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vasl2h a,b,u6 00101bbb011000010BBBuuuuuuAAAAAA. */
+{ "vasl2h", 0x28610000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vasl2h 0,b,u6 00101bbb011000010BBBuuuuuu111110. */
+{ "vasl2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vasl2h<.cc> b,b,u6 00101bbb111000010BBBuuuuuu1QQQQQ. */
+{ "vasl2h", 0x28E10020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vasl2h b,b,s12 00101bbb101000010BBBssssssSSSSSS. */
+{ "vasl2h", 0x28A10000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vasl2h a,limm,c 00101110001000010111CCCCCCAAAAAA. */
+{ "vasl2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vasl2h a,b,limm 00101bbb001000010BBB111110AAAAAA. */
+{ "vasl2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vasl2h 0,limm,c 00101110011000010111CCCCCC111110. */
+{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vasl2h 0,b,limm 00101bbb001000010BBB111110111110. */
+{ "vasl2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vasl2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ. */
+{ "vasl2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vasl2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ. */
+{ "vasl2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vasl2h a,limm,u6 00101110011000010111uuuuuuAAAAAA. */
+{ "vasl2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasl2h 0,limm,u6 00101110011000010111uuuuuu111110. */
+{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasl2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ. */
+{ "vasl2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vasl2h 0,limm,s12 00101110101000010111ssssssSSSSSS. */
+{ "vasl2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vasl2h a,limm,limm 00101110001000010111111110AAAAAA. */
+{ "vasl2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vasl2h 0,limm,limm 00101110001000010111111110111110. */
+{ "vasl2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vasl2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ. */
+{ "vasl2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vasls2h a,b,c 00101bbb001000011BBBCCCCCCAAAAAA. */
+{ "vasls2h", 0x28218000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vasls2h 0,b,c 00101bbb001000010BBBCCCCCC111110. */
+{ "vasls2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vasls2h<.cc> b,b,c 00101bbb111000011BBBCCCCCC0QQQQQ. */
+{ "vasls2h", 0x28E18000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vasls2h a,b,u6 00101bbb011000011BBBuuuuuuAAAAAA. */
+{ "vasls2h", 0x28618000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vasls2h 0,b,u6 00101bbb011000010BBBuuuuuu111110. */
+{ "vasls2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vasls2h<.cc> b,b,u6 00101bbb111000011BBBuuuuuu1QQQQQ. */
+{ "vasls2h", 0x28E18020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vasls2h b,b,s12 00101bbb101000011BBBssssssSSSSSS. */
+{ "vasls2h", 0x28A18000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vasls2h a,limm,c 00101110001000010111CCCCCCAAAAAA. */
+{ "vasls2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vasls2h a,b,limm 00101bbb001000010BBB111110AAAAAA. */
+{ "vasls2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vasls2h 0,limm,c 00101110011000010111CCCCCC111110. */
+{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vasls2h 0,b,limm 00101bbb001000010BBB111110111110. */
+{ "vasls2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vasls2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ. */
+{ "vasls2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vasls2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ. */
+{ "vasls2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vasls2h a,limm,u6 00101110011000010111uuuuuuAAAAAA. */
+{ "vasls2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasls2h 0,limm,u6 00101110011000010111uuuuuu111110. */
+{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasls2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ. */
+{ "vasls2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vasls2h 0,limm,s12 00101110101000010111ssssssSSSSSS. */
+{ "vasls2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vasls2h a,limm,limm 00101110001000010111111110AAAAAA. */
+{ "vasls2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vasls2h 0,limm,limm 00101110001000010111111110111110. */
+{ "vasls2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vasls2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ. */
+{ "vasls2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vasr2h a,b,c 00101bbb001000100BBBCCCCCCAAAAAA. */
+{ "vasr2h", 0x28220000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vasr2h 0,b,c 00101bbb001000100BBBCCCCCC111110. */
+{ "vasr2h", 0x2822003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vasr2h<.cc> b,b,c 00101bbb111000100BBBCCCCCC0QQQQQ. */
+{ "vasr2h", 0x28E20000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vasr2h a,b,u6 00101bbb011000100BBBuuuuuuAAAAAA. */
+{ "vasr2h", 0x28620000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vasr2h 0,b,u6 00101bbb011000100BBBuuuuuu111110. */
+{ "vasr2h", 0x2862003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vasr2h<.cc> b,b,u6 00101bbb111000100BBBuuuuuu1QQQQQ. */
+{ "vasr2h", 0x28E20020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vasr2h b,b,s12 00101bbb101000100BBBssssssSSSSSS. */
+{ "vasr2h", 0x28A20000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vasr2h a,limm,c 00101110001000100111CCCCCCAAAAAA. */
+{ "vasr2h", 0x2E227000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vasr2h a,b,limm 00101bbb001000100BBB111110AAAAAA. */
+{ "vasr2h", 0x28220F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vasr2h 0,limm,c 00101110011000100111CCCCCC111110. */
+{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vasr2h 0,b,limm 00101bbb001000100BBB111110111110. */
+{ "vasr2h", 0x28220FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vasr2h<.cc> b,b,limm 00101bbb111000100BBB1111100QQQQQ. */
+{ "vasr2h", 0x28E20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vasr2h<.cc> 0,limm,c 00101110111000100111CCCCCC0QQQQQ. */
+{ "vasr2h", 0x2EE27000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vasr2h a,limm,u6 00101110011000100111uuuuuuAAAAAA. */
+{ "vasr2h", 0x2E627000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasr2h 0,limm,u6 00101110011000100111uuuuuu111110. */
+{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasr2h<.cc> 0,limm,u6 00101110111000100111uuuuuu1QQQQQ. */
+{ "vasr2h", 0x2EE27020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vasr2h 0,limm,s12 00101110101000100111ssssssSSSSSS. */
+{ "vasr2h", 0x2EA27000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vasr2h a,limm,limm 00101110001000100111111110AAAAAA. */
+{ "vasr2h", 0x2E227F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vasr2h 0,limm,limm 00101110001000100111111110111110. */
+{ "vasr2h", 0x2E227FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vasr2h<.cc> 0,limm,limm 001011101110001001111111100QQQQQ. */
+{ "vasr2h", 0x2EE27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vasrs2h a,b,c 00101bbb001000101BBBCCCCCCAAAAAA. */
+{ "vasrs2h", 0x28228000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vasrs2h 0,b,c 00101bbb001000101BBBCCCCCC111110. */
+{ "vasrs2h", 0x2822803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vasrs2h<.cc> b,b,c 00101bbb111000101BBBCCCCCC0QQQQQ. */
+{ "vasrs2h", 0x28E28000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vasrs2h a,b,u6 00101bbb011000101BBBuuuuuuAAAAAA. */
+{ "vasrs2h", 0x28628000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vasrs2h 0,b,u6 00101bbb011000101BBBuuuuuu111110. */
+{ "vasrs2h", 0x2862803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vasrs2h<.cc> b,b,u6 00101bbb111000101BBBuuuuuu1QQQQQ. */
+{ "vasrs2h", 0x28E28020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vasrs2h b,b,s12 00101bbb101000101BBBssssssSSSSSS. */
+{ "vasrs2h", 0x28A28000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vasrs2h a,limm,c 00101110001000101111CCCCCCAAAAAA. */
+{ "vasrs2h", 0x2E22F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vasrs2h a,b,limm 00101bbb001000101BBB111110AAAAAA. */
+{ "vasrs2h", 0x28228F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vasrs2h 0,limm,c 00101110011000101111CCCCCC111110. */
+{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vasrs2h 0,b,limm 00101bbb001000101BBB111110111110. */
+{ "vasrs2h", 0x28228FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vasrs2h<.cc> b,b,limm 00101bbb111000101BBB1111100QQQQQ. */
+{ "vasrs2h", 0x28E28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vasrs2h<.cc> 0,limm,c 00101110111000101111CCCCCC0QQQQQ. */
+{ "vasrs2h", 0x2EE2F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vasrs2h a,limm,u6 00101110011000101111uuuuuuAAAAAA. */
+{ "vasrs2h", 0x2E62F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasrs2h 0,limm,u6 00101110011000101111uuuuuu111110. */
+{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasrs2h<.cc> 0,limm,u6 00101110111000101111uuuuuu1QQQQQ. */
+{ "vasrs2h", 0x2EE2F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vasrs2h 0,limm,s12 00101110101000101111ssssssSSSSSS. */
+{ "vasrs2h", 0x2EA2F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vasrs2h a,limm,limm 00101110001000101111111110AAAAAA. */
+{ "vasrs2h", 0x2E22FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vasrs2h 0,limm,limm 00101110001000101111111110111110. */
+{ "vasrs2h", 0x2E22FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vasrs2h<.cc> 0,limm,limm 001011101110001011111111100QQQQQ. */
+{ "vasrs2h", 0x2EE2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vasrsr2h a,b,c 00101bbb001000111BBBCCCCCCAAAAAA. */
+{ "vasrsr2h", 0x28238000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vasrsr2h 0,b,c 00101bbb001000111BBBCCCCCC111110. */
+{ "vasrsr2h", 0x2823803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vasrsr2h<.cc> b,b,c 00101bbb111000111BBBCCCCCC0QQQQQ. */
+{ "vasrsr2h", 0x28E38000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vasrsr2h a,b,u6 00101bbb011000111BBBuuuuuuAAAAAA. */
+{ "vasrsr2h", 0x28638000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vasrsr2h 0,b,u6 00101bbb011000111BBBuuuuuu111110. */
+{ "vasrsr2h", 0x2863803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vasrsr2h<.cc> b,b,u6 00101bbb111000111BBBuuuuuu1QQQQQ. */
+{ "vasrsr2h", 0x28E38020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vasrsr2h b,b,s12 00101bbb101000111BBBssssssSSSSSS. */
+{ "vasrsr2h", 0x28A38000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vasrsr2h a,limm,c 00101110001000111111CCCCCCAAAAAA. */
+{ "vasrsr2h", 0x2E23F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vasrsr2h a,b,limm 00101bbb001000111BBB111110AAAAAA. */
+{ "vasrsr2h", 0x28238F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vasrsr2h 0,limm,c 00101110011000111111CCCCCC111110. */
+{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vasrsr2h 0,b,limm 00101bbb001000111BBB111110111110. */
+{ "vasrsr2h", 0x28238FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vasrsr2h<.cc> b,b,limm 00101bbb111000111BBB1111100QQQQQ. */
+{ "vasrsr2h", 0x28E38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vasrsr2h<.cc> 0,limm,c 00101110111000111111CCCCCC0QQQQQ. */
+{ "vasrsr2h", 0x2EE3F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vasrsr2h a,limm,u6 00101110011000111111uuuuuuAAAAAA. */
+{ "vasrsr2h", 0x2E63F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasrsr2h 0,limm,u6 00101110011000111111uuuuuu111110. */
+{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vasrsr2h<.cc> 0,limm,u6 00101110111000111111uuuuuu1QQQQQ. */
+{ "vasrsr2h", 0x2EE3F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vasrsr2h 0,limm,s12 00101110101000111111ssssssSSSSSS. */
+{ "vasrsr2h", 0x2EA3F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vasrsr2h a,limm,limm 00101110001000111111111110AAAAAA. */
+{ "vasrsr2h", 0x2E23FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vasrsr2h 0,limm,limm 00101110001000111111111110111110. */
+{ "vasrsr2h", 0x2E23FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vasrsr2h<.cc> 0,limm,limm 001011101110001111111111100QQQQQ. */
+{ "vasrsr2h", 0x2EE3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vext2bhl b,c 00101bbb001011110BBBCCCCCC100100. */
+{ "vext2bhl", 0x282F0024, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vext2bhl 0,c 00101110001011110111CCCCCC100100. */
+{ "vext2bhl", 0x2E2F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vext2bhl b,u6 00101bbb011011110BBBuuuuuu100100. */
+{ "vext2bhl", 0x286F0024, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vext2bhl 0,u6 00101110011011110111uuuuuu100100. */
+{ "vext2bhl", 0x2E6F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vext2bhl b,limm 00101bbb001011110BBB111110100100. */
+{ "vext2bhl", 0x282F0FA4, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vext2bhl 0,limm 00101110001011110111111110100100. */
+{ "vext2bhl", 0x2E2F7FA4, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vext2bhlf b,c 00101bbb001011110BBBCCCCCC100000. */
+{ "vext2bhlf", 0x282F0020, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vext2bhlf 0,c 00101110001011110111CCCCCC100000. */
+{ "vext2bhlf", 0x2E2F7020, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vext2bhlf b,u6 00101bbb011011110BBBuuuuuu100000. */
+{ "vext2bhlf", 0x286F0020, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vext2bhlf 0,u6 00101110011011110111uuuuuu100000. */
+{ "vext2bhlf", 0x2E6F7020, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vext2bhlf b,limm 00101bbb001011110BBB111110100000. */
+{ "vext2bhlf", 0x282F0FA0, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vext2bhlf 0,limm 00101110001011110111111110100000. */
+{ "vext2bhlf", 0x2E2F7FA0, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vext2bhm b,c 00101bbb001011110BBBCCCCCC100101. */
+{ "vext2bhm", 0x282F0025, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vext2bhm 0,c 00101110001011110111CCCCCC100101. */
+{ "vext2bhm", 0x2E2F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vext2bhm b,u6 00101bbb011011110BBBuuuuuu100101. */
+{ "vext2bhm", 0x286F0025, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vext2bhm 0,u6 00101110011011110111uuuuuu100101. */
+{ "vext2bhm", 0x2E6F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vext2bhm b,limm 00101bbb001011110BBB111110100101. */
+{ "vext2bhm", 0x282F0FA5, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vext2bhm 0,limm 00101110001011110111111110100101. */
+{ "vext2bhm", 0x2E2F7FA5, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vext2bhmf b,c 00101bbb001011110BBBCCCCCC100001. */
+{ "vext2bhmf", 0x282F0021, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vext2bhmf 0,c 00101110001011110111CCCCCC100001. */
+{ "vext2bhmf", 0x2E2F7021, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vext2bhmf b,u6 00101bbb011011110BBBuuuuuu100001. */
+{ "vext2bhmf", 0x286F0021, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vext2bhmf 0,u6 00101110011011110111uuuuuu100001. */
+{ "vext2bhmf", 0x2E6F7021, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vext2bhmf b,limm 00101bbb001011110BBB111110100001. */
+{ "vext2bhmf", 0x282F0FA1, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vext2bhmf 0,limm 00101110001011110111111110100001. */
+{ "vext2bhmf", 0x2E2F7FA1, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vlsr2h a,b,c 00101bbb001000110BBBCCCCCCAAAAAA. */
+{ "vlsr2h", 0x28230000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vlsr2h 0,b,c 00101bbb001000110BBBCCCCCC111110. */
+{ "vlsr2h", 0x2823003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vlsr2h<.cc> b,b,c 00101bbb111000110BBBCCCCCC0QQQQQ. */
+{ "vlsr2h", 0x28E30000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vlsr2h a,b,u6 00101bbb011000110BBBuuuuuuAAAAAA. */
+{ "vlsr2h", 0x28630000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vlsr2h 0,b,u6 00101bbb011000110BBBuuuuuu111110. */
+{ "vlsr2h", 0x2863003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vlsr2h<.cc> b,b,u6 00101bbb111000110BBBuuuuuu1QQQQQ. */
+{ "vlsr2h", 0x28E30020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vlsr2h b,b,s12 00101bbb101000110BBBssssssSSSSSS. */
+{ "vlsr2h", 0x28A30000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vlsr2h a,limm,c 00101110001000110111CCCCCCAAAAAA. */
+{ "vlsr2h", 0x2E237000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vlsr2h a,b,limm 00101bbb001000110BBB111110AAAAAA. */
+{ "vlsr2h", 0x28230F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vlsr2h 0,limm,c 00101110011000110111CCCCCC111110. */
+{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vlsr2h 0,b,limm 00101bbb001000110BBB111110111110. */
+{ "vlsr2h", 0x28230FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vlsr2h<.cc> b,b,limm 00101bbb111000110BBB1111100QQQQQ. */
+{ "vlsr2h", 0x28E30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vlsr2h<.cc> 0,limm,c 00101110111000110111CCCCCC0QQQQQ. */
+{ "vlsr2h", 0x2EE37000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vlsr2h a,limm,u6 00101110011000110111uuuuuuAAAAAA. */
+{ "vlsr2h", 0x2E637000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vlsr2h 0,limm,u6 00101110011000110111uuuuuu111110. */
+{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vlsr2h<.cc> 0,limm,u6 00101110111000110111uuuuuu1QQQQQ. */
+{ "vlsr2h", 0x2EE37020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vlsr2h 0,limm,s12 00101110101000110111ssssssSSSSSS. */
+{ "vlsr2h", 0x2EA37000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vlsr2h a,limm,limm 00101110001000110111111110AAAAAA. */
+{ "vlsr2h", 0x2E237F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vlsr2h 0,limm,limm 00101110001000110111111110111110. */
+{ "vlsr2h", 0x2E237FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vlsr2h<.cc> 0,limm,limm 001011101110001101111111100QQQQQ. */
+{ "vlsr2h", 0x2EE37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2h a,b,c 00101bbb000111100BBBCCCCCCAAAAAA. */
+{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmac2h 0,b,c 00101bbb000111100BBBCCCCCC111110. */
+{ "vmac2h", 0x281E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2h<.cc> b,b,c 00101bbb110111100BBBCCCCCC0QQQQQ. */
+{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmac2h a,b,u6 00101bbb010111100BBBuuuuuuAAAAAA. */
+{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2h 0,b,u6 00101bbb010111100BBBuuuuuu111110. */
+{ "vmac2h", 0x285E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2h<.cc> b,b,u6 00101bbb110111100BBBuuuuuu1QQQQQ. */
+{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2h b,b,s12 00101bbb100111100BBBssssssSSSSSS. */
+{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2h a,limm,c 00101110000111100111CCCCCCAAAAAA. */
+{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmac2h a,b,limm 00101bbb000111100BBB111110AAAAAA. */
+{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmac2h 0,limm,c 00101110000111100111CCCCCC111110. */
+{ "vmac2h", 0x2E1E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2h 0,b,limm 00101bbb000111100BBB111110111110. */
+{ "vmac2h", 0x281E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2h<.cc> b,b,limm 00101bbb110111100BBB1111100QQQQQ. */
+{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmac2h<.cc> 0,limm,c 00101110110111100111CCCCCC0QQQQQ. */
+{ "vmac2h", 0x2EDE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2h a,limm,u6 00101110010111100111uuuuuuAAAAAA. */
+{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2h 0,limm,u6 00101110010111100111uuuuuu111110. */
+{ "vmac2h", 0x2E5E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2h<.cc> 0,limm,u6 00101110110111100111uuuuuu1QQQQQ. */
+{ "vmac2h", 0x2EDE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2h 0,limm,s12 00101110100111100111ssssssSSSSSS. */
+{ "vmac2h", 0x2E9E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2h a,limm,limm 00101110000111100111111110AAAAAA. */
+{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2h 0,limm,limm 00101110000111100111111110111110. */
+{ "vmac2h", 0x2E1E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2h<.cc> 0,limm,limm 001011101101111001111111100QQQQQ. */
+{ "vmac2h", 0x2EDE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2hf a,b,c 00101bbb000111101BBBCCCCCCAAAAAA. */
+{ "vmac2hf", 0x281E8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmac2hf 0,b,c 00101bbb000111101BBBCCCCCC111110. */
+{ "vmac2hf", 0x281E803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2hf<.cc> b,b,c 00101bbb110111101BBBCCCCCC0QQQQQ. */
+{ "vmac2hf", 0x28DE8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmac2hf a,b,u6 00101bbb010111101BBBuuuuuuAAAAAA. */
+{ "vmac2hf", 0x285E8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hf 0,b,u6 00101bbb010111101BBBuuuuuu111110. */
+{ "vmac2hf", 0x285E803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hf<.cc> b,b,u6 00101bbb110111101BBBuuuuuu1QQQQQ. */
+{ "vmac2hf", 0x28DE8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2hf b,b,s12 00101bbb100111101BBBssssssSSSSSS. */
+{ "vmac2hf", 0x289E8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2hf a,limm,c 00101110000111101111CCCCCCAAAAAA. */
+{ "vmac2hf", 0x2E1EF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmac2hf a,b,limm 00101bbb000111101BBB111110AAAAAA. */
+{ "vmac2hf", 0x281E8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmac2hf 0,limm,c 00101110000111101111CCCCCC111110. */
+{ "vmac2hf", 0x2E1EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2hf 0,b,limm 00101bbb000111101BBB111110111110. */
+{ "vmac2hf", 0x281E8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2hf<.cc> b,b,limm 00101bbb110111101BBB1111100QQQQQ. */
+{ "vmac2hf", 0x28DE8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmac2hf<.cc> 0,limm,c 00101110110111101111CCCCCC0QQQQQ. */
+{ "vmac2hf", 0x2EDEF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2hf a,limm,u6 00101110010111101111uuuuuuAAAAAA. */
+{ "vmac2hf", 0x2E5EF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hf 0,limm,u6 00101110010111101111uuuuuu111110. */
+{ "vmac2hf", 0x2E5EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hf<.cc> 0,limm,u6 00101110110111101111uuuuuu1QQQQQ. */
+{ "vmac2hf", 0x2EDEF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2hf 0,limm,s12 00101110100111101111ssssssSSSSSS. */
+{ "vmac2hf", 0x2E9EF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2hf a,limm,limm 00101110000111101111111110AAAAAA. */
+{ "vmac2hf", 0x2E1EFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hf 0,limm,limm 00101110000111101111111110111110. */
+{ "vmac2hf", 0x2E1EFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hf<.cc> 0,limm,limm 001011101101111011111111100QQQQQ. */
+{ "vmac2hf", 0x2EDEFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2hfr a,b,c 00101bbb000111111BBBCCCCCCAAAAAA. */
+{ "vmac2hfr", 0x281F8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmac2hfr 0,b,c 00101bbb000111111BBBCCCCCC111110. */
+{ "vmac2hfr", 0x281F803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2hfr<.cc> b,b,c 00101bbb110111111BBBCCCCCC0QQQQQ. */
+{ "vmac2hfr", 0x28DF8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmac2hfr a,b,u6 00101bbb010111111BBBuuuuuuAAAAAA. */
+{ "vmac2hfr", 0x285F8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hfr 0,b,u6 00101bbb010111111BBBuuuuuu111110. */
+{ "vmac2hfr", 0x285F803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hfr<.cc> b,b,u6 00101bbb110111111BBBuuuuuu1QQQQQ. */
+{ "vmac2hfr", 0x28DF8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2hfr b,b,s12 00101bbb100111111BBBssssssSSSSSS. */
+{ "vmac2hfr", 0x289F8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2hfr a,limm,c 00101110000111111111CCCCCCAAAAAA. */
+{ "vmac2hfr", 0x2E1FF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmac2hfr a,b,limm 00101bbb000111111BBB111110AAAAAA. */
+{ "vmac2hfr", 0x281F8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmac2hfr 0,limm,c 00101110000111111111CCCCCC111110. */
+{ "vmac2hfr", 0x2E1FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2hfr 0,b,limm 00101bbb000111111BBB111110111110. */
+{ "vmac2hfr", 0x281F8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2hfr<.cc> b,b,limm 00101bbb110111111BBB1111100QQQQQ. */
+{ "vmac2hfr", 0x28DF8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmac2hfr<.cc> 0,limm,c 00101110110111111111CCCCCC0QQQQQ. */
+{ "vmac2hfr", 0x2EDFF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2hfr a,limm,u6 00101110010111111111uuuuuuAAAAAA. */
+{ "vmac2hfr", 0x2E5FF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hfr 0,limm,u6 00101110010111111111uuuuuu111110. */
+{ "vmac2hfr", 0x2E5FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hfr<.cc> 0,limm,u6 00101110110111111111uuuuuu1QQQQQ. */
+{ "vmac2hfr", 0x2EDFF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2hfr 0,limm,s12 00101110100111111111ssssssSSSSSS. */
+{ "vmac2hfr", 0x2E9FF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2hfr a,limm,limm 00101110000111111111111110AAAAAA. */
+{ "vmac2hfr", 0x2E1FFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hfr 0,limm,limm 00101110000111111111111110111110. */
+{ "vmac2hfr", 0x2E1FFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hfr<.cc> 0,limm,limm 001011101101111111111111100QQQQQ. */
+{ "vmac2hfr", 0x2EDFFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2hnfr a,b,c 00110bbb000100010BBBCCCCCCAAAAAA. */
+{ "vmac2hnfr", 0x30110000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmac2hnfr 0,b,c 00110bbb000100010BBBCCCCCC111110. */
+{ "vmac2hnfr", 0x3011003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2hnfr<.cc> b,b,c 00110bbb110100010BBBCCCCCC0QQQQQ. */
+{ "vmac2hnfr", 0x30D10000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmac2hnfr a,b,u6 00110bbb010100010BBBuuuuuuAAAAAA. */
+{ "vmac2hnfr", 0x30510000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hnfr 0,b,u6 00110bbb010100010BBBuuuuuu111110. */
+{ "vmac2hnfr", 0x3051003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hnfr<.cc> b,b,u6 00110bbb110100010BBBuuuuuu1QQQQQ. */
+{ "vmac2hnfr", 0x30D10020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2hnfr b,b,s12 00110bbb100100010BBBssssssSSSSSS. */
+{ "vmac2hnfr", 0x30910000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2hnfr a,limm,c 00110110000100010111CCCCCCAAAAAA. */
+{ "vmac2hnfr", 0x36117000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmac2hnfr a,b,limm 00110bbb000100010BBB111110AAAAAA. */
+{ "vmac2hnfr", 0x30110F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmac2hnfr 0,limm,c 00110110000100010111CCCCCC111110. */
+{ "vmac2hnfr", 0x3611703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2hnfr 0,b,limm 00110bbb000100010BBB111110111110. */
+{ "vmac2hnfr", 0x30110FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2hnfr<.cc> b,b,limm 00110bbb110100010BBB1111100QQQQQ. */
+{ "vmac2hnfr", 0x30D10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmac2hnfr<.cc> 0,limm,c 00110110110100010111CCCCCC0QQQQQ. */
+{ "vmac2hnfr", 0x36D17000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2hnfr a,limm,u6 00110110010100010111uuuuuuAAAAAA. */
+{ "vmac2hnfr", 0x36517000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hnfr 0,limm,u6 00110110010100010111uuuuuu111110. */
+{ "vmac2hnfr", 0x3651703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hnfr<.cc> 0,limm,u6 00110110110100010111uuuuuu1QQQQQ. */
+{ "vmac2hnfr", 0x36D17020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2hnfr 0,limm,s12 00110110100100010111ssssssSSSSSS. */
+{ "vmac2hnfr", 0x36917000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2hnfr a,limm,limm 00110110000100010111111110AAAAAA. */
+{ "vmac2hnfr", 0x36117F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hnfr 0,limm,limm 00110110000100010111111110111110. */
+{ "vmac2hnfr", 0x36117FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hnfr<.cc> 0,limm,limm 001101101101000101111111100QQQQQ. */
+{ "vmac2hnfr", 0x36D17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmac2hu a,b,c 00101bbb000111110BBBCCCCCCAAAAAA. */
+{ "vmac2hu", 0x281F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmac2hu 0,b,c 00101bbb000111110BBBCCCCCC111110. */
+{ "vmac2hu", 0x281F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmac2hu<.cc> b,b,c 00101bbb110111110BBBCCCCCC0QQQQQ. */
+{ "vmac2hu", 0x28DF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmac2hu a,b,u6 00101bbb010111110BBBuuuuuuAAAAAA. */
+{ "vmac2hu", 0x285F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hu 0,b,u6 00101bbb010111110BBBuuuuuu111110. */
+{ "vmac2hu", 0x285F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmac2hu<.cc> b,b,u6 00101bbb110111110BBBuuuuuu1QQQQQ. */
+{ "vmac2hu", 0x28DF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmac2hu b,b,s12 00101bbb100111110BBBssssssSSSSSS. */
+{ "vmac2hu", 0x289F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmac2hu a,limm,c 00101110000111110111CCCCCCAAAAAA. */
+{ "vmac2hu", 0x2E1F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmac2hu a,b,limm 00101bbb000111110BBB111110AAAAAA. */
+{ "vmac2hu", 0x281F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmac2hu 0,limm,c 00101110000111110111CCCCCC111110. */
+{ "vmac2hu", 0x2E1F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmac2hu 0,b,limm 00101bbb000111110BBB111110111110. */
+{ "vmac2hu", 0x281F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmac2hu<.cc> b,b,limm 00101bbb110111110BBB1111100QQQQQ. */
+{ "vmac2hu", 0x28DF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmac2hu<.cc> 0,limm,c 00101110110111110111CCCCCC0QQQQQ. */
+{ "vmac2hu", 0x2EDF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmac2hu a,limm,u6 00101110010111110111uuuuuuAAAAAA. */
+{ "vmac2hu", 0x2E5F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hu 0,limm,u6 00101110010111110111uuuuuu111110. */
+{ "vmac2hu", 0x2E5F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmac2hu<.cc> 0,limm,u6 00101110110111110111uuuuuu1QQQQQ. */
+{ "vmac2hu", 0x2EDF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmac2hu 0,limm,s12 00101110100111110111ssssssSSSSSS. */
+{ "vmac2hu", 0x2E9F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmac2hu a,limm,limm 00101110000111110111111110AAAAAA. */
+{ "vmac2hu", 0x2E1F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hu 0,limm,limm 00101110000111110111111110111110. */
+{ "vmac2hu", 0x2E1F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmac2hu<.cc> 0,limm,limm 001011101101111101111111100QQQQQ. */
+{ "vmac2hu", 0x2EDF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmax2h a,b,c 00101bbb001001001BBBCCCCCCAAAAAA. */
+{ "vmax2h", 0x28248000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmax2h 0,b,c 00101bbb001001001BBBCCCCCC111110. */
+{ "vmax2h", 0x2824803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmax2h<.cc> b,b,c 00101bbb111001001BBBCCCCCC0QQQQQ. */
+{ "vmax2h", 0x28E48000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmax2h a,b,u6 00101bbb011001001BBBuuuuuuAAAAAA. */
+{ "vmax2h", 0x28648000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmax2h 0,b,u6 00101bbb011001001BBBuuuuuu111110. */
+{ "vmax2h", 0x2864803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmax2h<.cc> b,b,u6 00101bbb111001001BBBuuuuuu1QQQQQ. */
+{ "vmax2h", 0x28E48020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmax2h b,b,s12 00101bbb101001001BBBssssssSSSSSS. */
+{ "vmax2h", 0x28A48000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmax2h a,limm,c 00101110001001001111CCCCCCAAAAAA. */
+{ "vmax2h", 0x2E24F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmax2h a,b,limm 00101bbb001001001BBB111110AAAAAA. */
+{ "vmax2h", 0x28248F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmax2h 0,limm,c 00101110011001001111CCCCCC111110. */
+{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmax2h 0,b,limm 00101bbb001001001BBB111110111110. */
+{ "vmax2h", 0x28248FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmax2h<.cc> b,b,limm 00101bbb111001001BBB1111100QQQQQ. */
+{ "vmax2h", 0x28E48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmax2h<.cc> 0,limm,c 00101110111001001111CCCCCC0QQQQQ. */
+{ "vmax2h", 0x2EE4F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmax2h a,limm,u6 00101110011001001111uuuuuuAAAAAA. */
+{ "vmax2h", 0x2E64F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmax2h 0,limm,u6 00101110011001001111uuuuuu111110. */
+{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmax2h<.cc> 0,limm,u6 00101110111001001111uuuuuu1QQQQQ. */
+{ "vmax2h", 0x2EE4F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmax2h 0,limm,s12 00101110101001001111ssssssSSSSSS. */
+{ "vmax2h", 0x2EA4F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmax2h a,limm,limm 00101110001001001111111110AAAAAA. */
+{ "vmax2h", 0x2E24FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmax2h 0,limm,limm 00101110001001001111111110111110. */
+{ "vmax2h", 0x2E24FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmax2h<.cc> 0,limm,limm 001011101110010011111111100QQQQQ. */
+{ "vmax2h", 0x2EE4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmin2h a,b,c 00101bbb001001011BBBCCCCCCAAAAAA. */
+{ "vmin2h", 0x28258000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmin2h 0,b,c 00101bbb001001011BBBCCCCCC111110. */
+{ "vmin2h", 0x2825803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmin2h<.cc> b,b,c 00101bbb111001011BBBCCCCCC0QQQQQ. */
+{ "vmin2h", 0x28E58000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmin2h a,b,u6 00101bbb011001011BBBuuuuuuAAAAAA. */
+{ "vmin2h", 0x28658000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmin2h 0,b,u6 00101bbb011001011BBBuuuuuu111110. */
+{ "vmin2h", 0x2865803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmin2h<.cc> b,b,u6 00101bbb111001011BBBuuuuuu1QQQQQ. */
+{ "vmin2h", 0x28E58020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmin2h b,b,s12 00101bbb101001011BBBssssssSSSSSS. */
+{ "vmin2h", 0x28A58000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmin2h a,limm,c 00101110001001011111CCCCCCAAAAAA. */
+{ "vmin2h", 0x2E25F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmin2h a,b,limm 00101bbb001001011BBB111110AAAAAA. */
+{ "vmin2h", 0x28258F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmin2h 0,limm,c 00101110011001011111CCCCCC111110. */
+{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmin2h 0,b,limm 00101bbb001001011BBB111110111110. */
+{ "vmin2h", 0x28258FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmin2h<.cc> b,b,limm 00101bbb111001011BBB1111100QQQQQ. */
+{ "vmin2h", 0x28E58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmin2h<.cc> 0,limm,c 00101110111001011111CCCCCC0QQQQQ. */
+{ "vmin2h", 0x2EE5F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmin2h a,limm,u6 00101110011001011111uuuuuuAAAAAA. */
+{ "vmin2h", 0x2E65F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmin2h 0,limm,u6 00101110011001011111uuuuuu111110. */
+{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmin2h<.cc> 0,limm,u6 00101110111001011111uuuuuu1QQQQQ. */
+{ "vmin2h", 0x2EE5F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmin2h 0,limm,s12 00101110101001011111ssssssSSSSSS. */
+{ "vmin2h", 0x2EA5F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmin2h a,limm,limm 00101110001001011111111110AAAAAA. */
+{ "vmin2h", 0x2E25FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmin2h 0,limm,limm 00101110001001011111111110111110. */
+{ "vmin2h", 0x2E25FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmin2h<.cc> 0,limm,limm 001011101110010111111111100QQQQQ. */
+{ "vmin2h", 0x2EE5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */
+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */
+{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */
+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */
+{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */
+{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */
+{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */
+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */
+{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */
+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */
+{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */
+{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */
+{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */
+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */
+{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */
+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */
+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */
+{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */
+{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */
+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */
+{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */
+{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */
+{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */
+{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */
+{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */
+{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */
+{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */
+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */
+{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */
+{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */
+{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */
+{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */
+{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */
+{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */
+{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */
+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */
+{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */
+{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */
+{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */
+{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */
+{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hf a,b,c 00101bbb000111001BBBCCCCCCAAAAAA. */
+{ "vmpy2hf", 0x281C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmpy2hf 0,b,c 00101bbb000111001BBBCCCCCC111110. */
+{ "vmpy2hf", 0x281C803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hf<.cc> b,b,c 00101bbb110111001BBBCCCCCC0QQQQQ. */
+{ "vmpy2hf", 0x28DC8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmpy2hf a,b,u6 00101bbb010111001BBBuuuuuuAAAAAA. */
+{ "vmpy2hf", 0x285C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hf 0,b,u6 00101bbb010111001BBBuuuuuu111110. */
+{ "vmpy2hf", 0x285C803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hf<.cc> b,b,u6 00101bbb110111001BBBuuuuuu1QQQQQ. */
+{ "vmpy2hf", 0x28DC8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hf b,b,s12 00101bbb100111001BBBssssssSSSSSS. */
+{ "vmpy2hf", 0x289C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hf a,limm,c 00101110000111001111CCCCCCAAAAAA. */
+{ "vmpy2hf", 0x2E1CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmpy2hf a,b,limm 00101bbb000111001BBB111110AAAAAA. */
+{ "vmpy2hf", 0x281C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmpy2hf 0,limm,c 00101110000111001111CCCCCC111110. */
+{ "vmpy2hf", 0x2E1CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hf 0,b,limm 00101bbb000111001BBB111110111110. */
+{ "vmpy2hf", 0x281C8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hf<.cc> b,b,limm 00101bbb110111001BBB1111100QQQQQ. */
+{ "vmpy2hf", 0x28DC8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hf<.cc> 0,limm,c 00101110110111001111CCCCCC0QQQQQ. */
+{ "vmpy2hf", 0x2EDCF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hf a,limm,u6 00101110010111001111uuuuuuAAAAAA. */
+{ "vmpy2hf", 0x2E5CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hf 0,limm,u6 00101110010111001111uuuuuu111110. */
+{ "vmpy2hf", 0x2E5CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hf<.cc> 0,limm,u6 00101110110111001111uuuuuu1QQQQQ. */
+{ "vmpy2hf", 0x2EDCF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hf 0,limm,s12 00101110100111001111ssssssSSSSSS. */
+{ "vmpy2hf", 0x2E9CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hf a,limm,limm 00101110000111001111111110AAAAAA. */
+{ "vmpy2hf", 0x2E1CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hf 0,limm,limm 00101110000111001111111110111110. */
+{ "vmpy2hf", 0x2E1CFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hf<.cc> 0,limm,limm 001011101101110011111111100QQQQQ. */
+{ "vmpy2hf", 0x2EDCFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hfr a,b,c 00101bbb000111011BBBCCCCCCAAAAAA. */
+{ "vmpy2hfr", 0x281D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmpy2hfr 0,b,c 00101bbb000111011BBBCCCCCC111110. */
+{ "vmpy2hfr", 0x281D803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hfr<.cc> b,b,c 00101bbb110111011BBBCCCCCC0QQQQQ. */
+{ "vmpy2hfr", 0x28DD8000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmpy2hfr a,b,u6 00101bbb010111011BBBuuuuuuAAAAAA. */
+{ "vmpy2hfr", 0x285D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hfr 0,b,u6 00101bbb010111011BBBuuuuuu111110. */
+{ "vmpy2hfr", 0x285D803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hfr<.cc> b,b,u6 00101bbb110111011BBBuuuuuu1QQQQQ. */
+{ "vmpy2hfr", 0x28DD8020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hfr b,b,s12 00101bbb100111011BBBssssssSSSSSS. */
+{ "vmpy2hfr", 0x289D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hfr a,limm,c 00101110000111011111CCCCCCAAAAAA. */
+{ "vmpy2hfr", 0x2E1DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmpy2hfr a,b,limm 00101bbb000111011BBB111110AAAAAA. */
+{ "vmpy2hfr", 0x281D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmpy2hfr 0,limm,c 00101110000111011111CCCCCC111110. */
+{ "vmpy2hfr", 0x2E1DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hfr 0,b,limm 00101bbb000111011BBB111110111110. */
+{ "vmpy2hfr", 0x281D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hfr<.cc> b,b,limm 00101bbb110111011BBB1111100QQQQQ. */
+{ "vmpy2hfr", 0x28DD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hfr<.cc> 0,limm,c 00101110110111011111CCCCCC0QQQQQ. */
+{ "vmpy2hfr", 0x2EDDF000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hfr a,limm,u6 00101110010111011111uuuuuuAAAAAA. */
+{ "vmpy2hfr", 0x2E5DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hfr 0,limm,u6 00101110010111011111uuuuuu111110. */
+{ "vmpy2hfr", 0x2E5DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hfr<.cc> 0,limm,u6 00101110110111011111uuuuuu1QQQQQ. */
+{ "vmpy2hfr", 0x2EDDF020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hfr 0,limm,s12 00101110100111011111ssssssSSSSSS. */
+{ "vmpy2hfr", 0x2E9DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hfr a,limm,limm 00101110000111011111111110AAAAAA. */
+{ "vmpy2hfr", 0x2E1DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hfr 0,limm,limm 00101110000111011111111110111110. */
+{ "vmpy2hfr", 0x2E1DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hfr<.cc> 0,limm,limm 001011101101110111111111100QQQQQ. */
+{ "vmpy2hfr", 0x2EDDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */
+{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */
+{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */
+{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */
+{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */
+{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */
+{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */
+{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */
+{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */
+{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */
+{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */
+{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */
+{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */
+{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */
+{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */
+{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */
+{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */
+{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */
+{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */
+{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */
+{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */
+{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */
+{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */
+{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */
+{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */
+{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */
+{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */
+{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */
+{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */
+{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */
+{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */
+{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */
+{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */
+{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */
+{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */
+{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */
+{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */
+{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */
+{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */
+{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */
+{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY8E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmpy2hwf a,b,c 00101bbb001000000BBBCCCCCCAAAAAA. */
+{ "vmpy2hwf", 0x28200000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmpy2hwf 0,b,c 00101bbb001000000BBBCCCCCC111110. */
+{ "vmpy2hwf", 0x2820003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmpy2hwf<.cc> b,b,c 00101bbb111000000BBBCCCCCC0QQQQQ. */
+{ "vmpy2hwf", 0x28E00000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmpy2hwf a,b,u6 00101bbb011000000BBBuuuuuuAAAAAA. */
+{ "vmpy2hwf", 0x28600000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hwf 0,b,u6 00101bbb011000000BBBuuuuuu111110. */
+{ "vmpy2hwf", 0x2860003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmpy2hwf<.cc> b,b,u6 00101bbb111000000BBBuuuuuu1QQQQQ. */
+{ "vmpy2hwf", 0x28E00020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hwf b,b,s12 00101bbb101000000BBBssssssSSSSSS. */
+{ "vmpy2hwf", 0x28A00000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmpy2hwf a,limm,c 00101110001000000111CCCCCCAAAAAA. */
+{ "vmpy2hwf", 0x2E207000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmpy2hwf a,b,limm 00101bbb001000000BBB111110AAAAAA. */
+{ "vmpy2hwf", 0x28200F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmpy2hwf 0,limm,c 00101110011000000111CCCCCC111110. */
+{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmpy2hwf 0,b,limm 00101bbb001000000BBB111110111110. */
+{ "vmpy2hwf", 0x28200FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmpy2hwf<.cc> b,b,limm 00101bbb111000000BBB1111100QQQQQ. */
+{ "vmpy2hwf", 0x28E00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmpy2hwf<.cc> 0,limm,c 00101110111000000111CCCCCC0QQQQQ. */
+{ "vmpy2hwf", 0x2EE07000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmpy2hwf a,limm,u6 00101110011000000111uuuuuuAAAAAA. */
+{ "vmpy2hwf", 0x2E607000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hwf 0,limm,u6 00101110011000000111uuuuuu111110. */
+{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmpy2hwf<.cc> 0,limm,u6 00101110111000000111uuuuuu1QQQQQ. */
+{ "vmpy2hwf", 0x2EE07020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmpy2hwf 0,limm,s12 00101110101000000111ssssssSSSSSS. */
+{ "vmpy2hwf", 0x2EA07000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmpy2hwf a,limm,limm 00101110001000000111111110AAAAAA. */
+{ "vmpy2hwf", 0x2E207F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hwf 0,limm,limm 00101110001000000111111110111110. */
+{ "vmpy2hwf", 0x2E207FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmpy2hwf<.cc> 0,limm,limm 001011101110000001111111100QQQQQ. */
+{ "vmpy2hwf", 0x2EE07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmsub2hf a,b,c 00110bbb000001000BBBCCCCCCAAAAAA. */
+{ "vmsub2hf", 0x30040000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmsub2hf 0,b,c 00110bbb000001000BBBCCCCCC111110. */
+{ "vmsub2hf", 0x3004003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmsub2hf<.cc> b,b,c 00110bbb110001000BBBCCCCCC0QQQQQ. */
+{ "vmsub2hf", 0x30C40000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmsub2hf a,b,u6 00110bbb010001000BBBuuuuuuAAAAAA. */
+{ "vmsub2hf", 0x30440000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hf 0,b,u6 00110bbb010001000BBBuuuuuu111110. */
+{ "vmsub2hf", 0x3044003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hf<.cc> b,b,u6 00110bbb110001000BBBuuuuuu1QQQQQ. */
+{ "vmsub2hf", 0x30C40020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hf b,b,s12 00110bbb100001000BBBssssssSSSSSS. */
+{ "vmsub2hf", 0x30840000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmsub2hf a,limm,c 00110110000001000111CCCCCCAAAAAA. */
+{ "vmsub2hf", 0x36047000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmsub2hf a,b,limm 00110bbb000001000BBB111110AAAAAA. */
+{ "vmsub2hf", 0x30040F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmsub2hf 0,limm,c 00110110000001000111CCCCCC111110. */
+{ "vmsub2hf", 0x3604703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmsub2hf 0,b,limm 00110bbb000001000BBB111110111110. */
+{ "vmsub2hf", 0x30040FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmsub2hf<.cc> b,b,limm 00110bbb110001000BBB1111100QQQQQ. */
+{ "vmsub2hf", 0x30C40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmsub2hf<.cc> 0,limm,c 00110110110001000111CCCCCC0QQQQQ. */
+{ "vmsub2hf", 0x36C47000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmsub2hf a,limm,u6 00110110010001000111uuuuuuAAAAAA. */
+{ "vmsub2hf", 0x36447000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hf 0,limm,u6 00110110010001000111uuuuuu111110. */
+{ "vmsub2hf", 0x3644703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hf<.cc> 0,limm,u6 00110110110001000111uuuuuu1QQQQQ. */
+{ "vmsub2hf", 0x36C47020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hf 0,limm,s12 00110110100001000111ssssssSSSSSS. */
+{ "vmsub2hf", 0x36847000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmsub2hf a,limm,limm 00110110000001000111111110AAAAAA. */
+{ "vmsub2hf", 0x36047F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hf 0,limm,limm 00110110000001000111111110111110. */
+{ "vmsub2hf", 0x36047FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hf<.cc> 0,limm,limm 001101101100010001111111100QQQQQ. */
+{ "vmsub2hf", 0x36C47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmsub2hfr a,b,c 00110bbb000000110BBBCCCCCCAAAAAA. */
+{ "vmsub2hfr", 0x30030000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmsub2hfr 0,b,c 00110bbb000000110BBBCCCCCC111110. */
+{ "vmsub2hfr", 0x3003003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmsub2hfr<.cc> b,b,c 00110bbb110000110BBBCCCCCC0QQQQQ. */
+{ "vmsub2hfr", 0x30C30000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmsub2hfr a,b,u6 00110bbb010000110BBBuuuuuuAAAAAA. */
+{ "vmsub2hfr", 0x30430000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hfr 0,b,u6 00110bbb010000110BBBuuuuuu111110. */
+{ "vmsub2hfr", 0x3043003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hfr<.cc> b,b,u6 00110bbb110000110BBBuuuuuu1QQQQQ. */
+{ "vmsub2hfr", 0x30C30020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hfr b,b,s12 00110bbb100000110BBBssssssSSSSSS. */
+{ "vmsub2hfr", 0x30830000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmsub2hfr a,limm,c 00110110000000110111CCCCCCAAAAAA. */
+{ "vmsub2hfr", 0x36037000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmsub2hfr a,b,limm 00110bbb000000110BBB111110AAAAAA. */
+{ "vmsub2hfr", 0x30030F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmsub2hfr 0,limm,c 00110110000000110111CCCCCC111110. */
+{ "vmsub2hfr", 0x3603703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmsub2hfr 0,b,limm 00110bbb000000110BBB111110111110. */
+{ "vmsub2hfr", 0x30030FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmsub2hfr<.cc> b,b,limm 00110bbb110000110BBB1111100QQQQQ. */
+{ "vmsub2hfr", 0x30C30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmsub2hfr<.cc> 0,limm,c 00110110110000110111CCCCCC0QQQQQ. */
+{ "vmsub2hfr", 0x36C37000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmsub2hfr a,limm,u6 00110110010000110111uuuuuuAAAAAA. */
+{ "vmsub2hfr", 0x36437000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hfr 0,limm,u6 00110110010000110111uuuuuu111110. */
+{ "vmsub2hfr", 0x3643703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hfr<.cc> 0,limm,u6 00110110110000110111uuuuuu1QQQQQ. */
+{ "vmsub2hfr", 0x36C37020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hfr 0,limm,s12 00110110100000110111ssssssSSSSSS. */
+{ "vmsub2hfr", 0x36837000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmsub2hfr a,limm,limm 00110110000000110111111110AAAAAA. */
+{ "vmsub2hfr", 0x36037F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hfr 0,limm,limm 00110110000000110111111110111110. */
+{ "vmsub2hfr", 0x36037FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hfr<.cc> 0,limm,limm 001101101100001101111111100QQQQQ. */
+{ "vmsub2hfr", 0x36C37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vmsub2hnfr a,b,c 00110bbb000100011BBBCCCCCCAAAAAA. */
+{ "vmsub2hnfr", 0x30118000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vmsub2hnfr 0,b,c 00110bbb000100011BBBCCCCCC111110. */
+{ "vmsub2hnfr", 0x3011803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vmsub2hnfr<.cc> b,b,c 00110bbb110100011BBBCCCCCC0QQQQQ. */
+{ "vmsub2hnfr", 0x30D18000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vmsub2hnfr a,b,u6 00110bbb010100011BBBuuuuuuAAAAAA. */
+{ "vmsub2hnfr", 0x30518000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hnfr 0,b,u6 00110bbb010100011BBBuuuuuu111110. */
+{ "vmsub2hnfr", 0x3051803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vmsub2hnfr<.cc> b,b,u6 00110bbb110100011BBBuuuuuu1QQQQQ. */
+{ "vmsub2hnfr", 0x30D18020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hnfr b,b,s12 00110bbb100100011BBBssssssSSSSSS. */
+{ "vmsub2hnfr", 0x30918000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vmsub2hnfr a,limm,c 00110110000100011111CCCCCCAAAAAA. */
+{ "vmsub2hnfr", 0x3611F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vmsub2hnfr a,b,limm 00110bbb000100011BBB111110AAAAAA. */
+{ "vmsub2hnfr", 0x30118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vmsub2hnfr 0,limm,c 00110110000100011111CCCCCC111110. */
+{ "vmsub2hnfr", 0x3611F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vmsub2hnfr 0,b,limm 00110bbb000100011BBB111110111110. */
+{ "vmsub2hnfr", 0x30118FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vmsub2hnfr<.cc> b,b,limm 00110bbb110100011BBB1111100QQQQQ. */
+{ "vmsub2hnfr", 0x30D18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vmsub2hnfr<.cc> 0,limm,c 00110110110100011111CCCCCC0QQQQQ. */
+{ "vmsub2hnfr", 0x36D1F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vmsub2hnfr a,limm,u6 00110110010100011111uuuuuuAAAAAA. */
+{ "vmsub2hnfr", 0x3651F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hnfr 0,limm,u6 00110110010100011111uuuuuu111110. */
+{ "vmsub2hnfr", 0x3651F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vmsub2hnfr<.cc> 0,limm,u6 00110110110100011111uuuuuu1QQQQQ. */
+{ "vmsub2hnfr", 0x36D1F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vmsub2hnfr 0,limm,s12 00110110100100011111ssssssSSSSSS. */
+{ "vmsub2hnfr", 0x3691F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vmsub2hnfr a,limm,limm 00110110000100011111111110AAAAAA. */
+{ "vmsub2hnfr", 0x3611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hnfr 0,limm,limm 00110110000100011111111110111110. */
+{ "vmsub2hnfr", 0x3611FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vmsub2hnfr<.cc> 0,limm,limm 001101101101000111111111100QQQQQ. */
+{ "vmsub2hnfr", 0x36D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vneg2h b,c 00101bbb001011110BBBCCCCCC101010. */
+{ "vneg2h", 0x282F002A, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vneg2h 0,c 00101110001011110111CCCCCC101010. */
+{ "vneg2h", 0x2E2F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vneg2h b,u6 00101bbb011011110BBBuuuuuu101010. */
+{ "vneg2h", 0x286F002A, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vneg2h 0,u6 00101110011011110111uuuuuu101010. */
+{ "vneg2h", 0x2E6F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vneg2h b,limm 00101bbb001011110BBB111110101010. */
+{ "vneg2h", 0x282F0FAA, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vneg2h 0,limm 00101110001011110111111110101010. */
+{ "vneg2h", 0x2E2F7FAA, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vnegs2h b,c 00101bbb001011110BBBCCCCCC101011. */
+{ "vnegs2h", 0x282F002B, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vnegs2h 0,c 00101110001011110111CCCCCC101011. */
+{ "vnegs2h", 0x2E2F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vnegs2h b,u6 00101bbb011011110BBBuuuuuu101011. */
+{ "vnegs2h", 0x286F002B, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vnegs2h 0,u6 00101110011011110111uuuuuu101011. */
+{ "vnegs2h", 0x2E6F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vnegs2h b,limm 00101bbb001011110BBB111110101011. */
+{ "vnegs2h", 0x282F0FAB, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vnegs2h 0,limm 00101110001011110111111110101011. */
+{ "vnegs2h", 0x2E2F7FAB, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vnorm2h b,c 00101bbb001011110BBBCCCCCC101100. */
+{ "vnorm2h", 0x282F002C, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vnorm2h 0,c 00101110001011110111CCCCCC101100. */
+{ "vnorm2h", 0x2E2F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vnorm2h b,u6 00101bbb011011110BBBuuuuuu101100. */
+{ "vnorm2h", 0x286F002C, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vnorm2h 0,u6 00101110011011110111uuuuuu101100. */
+{ "vnorm2h", 0x2E6F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vnorm2h b,limm 00101bbb001011110BBB111110101100. */
+{ "vnorm2h", 0x282F0FAC, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vnorm2h 0,limm 00101110001011110111111110101100. */
+{ "vnorm2h", 0x2E2F7FAC, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vpack2hbl b,c 00101bbb001011110BBBCCCCCC011100. */
+{ "vpack2hbl", 0x282F001C, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vpack2hbl 0,c 00101110001011110111CCCCCC011100. */
+{ "vpack2hbl", 0x2E2F701C, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vpack2hbl b,u6 00101bbb011011110BBBuuuuuu011100. */
+{ "vpack2hbl", 0x286F001C, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vpack2hbl 0,u6 00101110011011110111uuuuuu011100. */
+{ "vpack2hbl", 0x2E6F701C, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vpack2hbl b,limm 00101bbb001011110BBB111110011100. */
+{ "vpack2hbl", 0x282F0F9C, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vpack2hbl 0,limm 00101110001011110111111110011100. */
+{ "vpack2hbl", 0x2E2F7F9C, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vpack2hblf b,c 00101bbb001011110BBBCCCCCC011110. */
+{ "vpack2hblf", 0x282F001E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vpack2hblf 0,c 00101110001011110111CCCCCC011110. */
+{ "vpack2hblf", 0x2E2F701E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vpack2hblf b,u6 00101bbb011011110BBBuuuuuu011110. */
+{ "vpack2hblf", 0x286F001E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vpack2hblf 0,u6 00101110011011110111uuuuuu011110. */
+{ "vpack2hblf", 0x2E6F701E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vpack2hblf b,limm 00101bbb001011110BBB111110011110. */
+{ "vpack2hblf", 0x282F0F9E, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vpack2hblf 0,limm 00101110001011110111111110011110. */
+{ "vpack2hblf", 0x2E2F7F9E, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vpack2hbm b,c 00101bbb001011110BBBCCCCCC011101. */
+{ "vpack2hbm", 0x282F001D, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vpack2hbm 0,c 00101110001011110111CCCCCC011101. */
+{ "vpack2hbm", 0x2E2F701D, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vpack2hbm b,u6 00101bbb011011110BBBuuuuuu011101. */
+{ "vpack2hbm", 0x286F001D, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vpack2hbm 0,u6 00101110011011110111uuuuuu011101. */
+{ "vpack2hbm", 0x2E6F701D, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vpack2hbm b,limm 00101bbb001011110BBB111110011101. */
+{ "vpack2hbm", 0x282F0F9D, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vpack2hbm 0,limm 00101110001011110111111110011101. */
+{ "vpack2hbm", 0x2E2F7F9D, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vpack2hbmf b,c 00101bbb001011110BBBCCCCCC011111. */
+{ "vpack2hbmf", 0x282F001F, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vpack2hbmf 0,c 00101110001011110111CCCCCC011111. */
+{ "vpack2hbmf", 0x2E2F701F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vpack2hbmf b,u6 00101bbb011011110BBBuuuuuu011111. */
+{ "vpack2hbmf", 0x286F001F, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vpack2hbmf 0,u6 00101110011011110111uuuuuu011111. */
+{ "vpack2hbmf", 0x2E6F701F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vpack2hbmf b,limm 00101bbb001011110BBB111110011111. */
+{ "vpack2hbmf", 0x282F0F9F, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vpack2hbmf 0,limm 00101110001011110111111110011111. */
+{ "vpack2hbmf", 0x2E2F7F9F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vpack4hl a,b,c 00101bbb001010010BBBCCCCCCAAAAAA. */
+{ "vpack4hl", 0x28290000, 0xF8FF8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vpack4hl 0,b,c 00101bbb001010010BBBCCCCCC111110. */
+{ "vpack4hl", 0x2829003E, 0xF8FF803F, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vpack4hl<.cc> b,b,c 00101bbb111010010BBBCCCCCC0QQQQQ. */
+{ "vpack4hl", 0x28E90000, 0xF8FF8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vpack4hl a,b,u6 00101bbb011010010BBBuuuuuuAAAAAA. */
+{ "vpack4hl", 0x28690000, 0xF8FF8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vpack4hl 0,b,u6 00101bbb011010010BBBuuuuuu111110. */
+{ "vpack4hl", 0x2869003E, 0xF8FF803F, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vpack4hl<.cc> b,b,u6 00101bbb111010010BBBuuuuuu1QQQQQ. */
+{ "vpack4hl", 0x28E90020, 0xF8FF8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vpack4hl b,b,s12 00101bbb101010010BBBssssssSSSSSS. */
+{ "vpack4hl", 0x28A90000, 0xF8FF8000, ARC_OPCODE_ARC64, MOVE, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vpack4hl a,limm,c 00101110001010010111CCCCCCAAAAAA. */
+{ "vpack4hl", 0x2E297000, 0xFFFFF000, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vpack4hl a,b,limm 00101bbb001010010BBB111110AAAAAA. */
+{ "vpack4hl", 0x28290F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vpack4hl 0,limm,c 00101110011010010111CCCCCC111110. */
+{ "vpack4hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vpack4hl 0,b,limm 00101bbb001010010BBB111110111110. */
+{ "vpack4hl", 0x28290FBE, 0xF8FF8FFF, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vpack4hl<.cc> b,b,limm 00101bbb111010010BBB1111100QQQQQ. */
+{ "vpack4hl", 0x28E90F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, MOVE, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vpack4hl<.cc> 0,limm,c 00101110111010010111CCCCCC0QQQQQ. */
+{ "vpack4hl", 0x2EE97000, 0xFFFFF020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vpack4hl a,limm,u6 00101110011010010111uuuuuuAAAAAA. */
+{ "vpack4hl", 0x2E697000, 0xFFFFF000, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vpack4hl 0,limm,u6 00101110011010010111uuuuuu111110. */
+{ "vpack4hl", 0x2E69703E, 0xFFFFF03F, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vpack4hl<.cc> 0,limm,u6 00101110111010010111uuuuuu1QQQQQ. */
+{ "vpack4hl", 0x2EE97020, 0xFFFFF020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vpack4hl 0,limm,s12 00101110101010010111ssssssSSSSSS. */
+{ "vpack4hl", 0x2EA97000, 0xFFFFF000, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vpack4hl a,limm,limm 00101110001010010111111110AAAAAA. */
+{ "vpack4hl", 0x2E297F80, 0xFFFFFFC0, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vpack4hl 0,limm,limm 00101110001010010111111110111110. */
+{ "vpack4hl", 0x2E297FBE, 0xFFFFFFFF, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vpack4hl<.cc> 0,limm,limm 001011101110100101111111100QQQQQ. */
+{ "vpack4hl", 0x2EE97F80, 0xFFFFFFE0, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vpack4hm a,b,c 00101bbb001010011BBBCCCCCCAAAAAA. */
+{ "vpack4hm", 0x28298000, 0xF8FF8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vpack4hm 0,b,c 00101bbb001010011BBBCCCCCC111110. */
+{ "vpack4hm", 0x2829803E, 0xF8FF803F, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vpack4hm<.cc> b,b,c 00101bbb111010011BBBCCCCCC0QQQQQ. */
+{ "vpack4hm", 0x28E98000, 0xF8FF8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vpack4hm a,b,u6 00101bbb011010011BBBuuuuuuAAAAAA. */
+{ "vpack4hm", 0x28698000, 0xF8FF8000, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vpack4hm 0,b,u6 00101bbb011010011BBBuuuuuu111110. */
+{ "vpack4hm", 0x2869803E, 0xF8FF803F, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vpack4hm<.cc> b,b,u6 00101bbb111010011BBBuuuuuu1QQQQQ. */
+{ "vpack4hm", 0x28E98020, 0xF8FF8020, ARC_OPCODE_ARC64, MOVE, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vpack4hm b,b,s12 00101bbb101010011BBBssssssSSSSSS. */
+{ "vpack4hm", 0x28A98000, 0xF8FF8000, ARC_OPCODE_ARC64, MOVE, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vpack4hm a,limm,c 00101110001010011111CCCCCCAAAAAA. */
+{ "vpack4hm", 0x2E29F000, 0xFFFFF000, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vpack4hm a,b,limm 00101bbb001010011BBB111110AAAAAA. */
+{ "vpack4hm", 0x28298F80, 0xF8FF8FC0, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vpack4hm 0,limm,c 00101110011010011111CCCCCC111110. */
+{ "vpack4hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vpack4hm 0,b,limm 00101bbb001010011BBB111110111110. */
+{ "vpack4hm", 0x28298FBE, 0xF8FF8FFF, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vpack4hm<.cc> b,b,limm 00101bbb111010011BBB1111100QQQQQ. */
+{ "vpack4hm", 0x28E98F80, 0xF8FF8FE0, ARC_OPCODE_ARC64, MOVE, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vpack4hm<.cc> 0,limm,c 00101110111010011111CCCCCC0QQQQQ. */
+{ "vpack4hm", 0x2EE9F000, 0xFFFFF020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vpack4hm a,limm,u6 00101110011010011111uuuuuuAAAAAA. */
+{ "vpack4hm", 0x2E69F000, 0xFFFFF000, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vpack4hm 0,limm,u6 00101110011010011111uuuuuu111110. */
+{ "vpack4hm", 0x2E69F03E, 0xFFFFF03F, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vpack4hm<.cc> 0,limm,u6 00101110111010011111uuuuuu1QQQQQ. */
+{ "vpack4hm", 0x2EE9F020, 0xFFFFF020, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vpack4hm 0,limm,s12 00101110101010011111ssssssSSSSSS. */
+{ "vpack4hm", 0x2EA9F000, 0xFFFFF000, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vpack4hm a,limm,limm 00101110001010011111111110AAAAAA. */
+{ "vpack4hm", 0x2E29FF80, 0xFFFFFFC0, ARC_OPCODE_ARC64, MOVE, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vpack4hm 0,limm,limm 00101110001010011111111110111110. */
+{ "vpack4hm", 0x2E29FFBE, 0xFFFFFFFF, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vpack4hm<.cc> 0,limm,limm 001011101110100111111111100QQQQQ. */
+{ "vpack4hm", 0x2EE9FF80, 0xFFFFFFE0, ARC_OPCODE_ARC64, MOVE, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vperm a,b,c 00101bbb001011100BBBCCCCCCAAAAAA. */
+{ "vperm", 0x282E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vperm 0,b,c 00101bbb001011100BBBCCCCCC111110. */
+{ "vperm", 0x282E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vperm<.cc> b,b,c 00101bbb111011100BBBCCCCCC0QQQQQ. */
+{ "vperm", 0x28EE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vperm a,b,u6 00101bbb011011100BBBuuuuuuAAAAAA. */
+{ "vperm", 0x286E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vperm 0,b,u6 00101bbb011011100BBBuuuuuu111110. */
+{ "vperm", 0x286E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vperm<.cc> b,b,u6 00101bbb111011100BBBuuuuuu1QQQQQ. */
+{ "vperm", 0x28EE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vperm b,b,s12 00101bbb101011100BBBssssssSSSSSS. */
+{ "vperm", 0x28AE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vperm a,limm,c 00101110001011100111CCCCCCAAAAAA. */
+{ "vperm", 0x2E2E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vperm a,b,limm 00101bbb001011100BBB111110AAAAAA. */
+{ "vperm", 0x282E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vperm 0,limm,c 00101110011011100111CCCCCC111110. */
+{ "vperm", 0x2E6E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vperm 0,b,limm 00101bbb001011100BBB111110111110. */
+{ "vperm", 0x282E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vperm<.cc> b,b,limm 00101bbb111011100BBB1111100QQQQQ. */
+{ "vperm", 0x28EE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vperm<.cc> 0,limm,c 00101110111011100111CCCCCC0QQQQQ. */
+{ "vperm", 0x2EEE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vperm a,limm,u6 00101110011011100111uuuuuuAAAAAA. */
+{ "vperm", 0x2E6E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vperm 0,limm,u6 00101110011011100111uuuuuu111110. */
+{ "vperm", 0x2E6E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vperm<.cc> 0,limm,u6 00101110111011100111uuuuuu1QQQQQ. */
+{ "vperm", 0x2EEE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vperm 0,limm,s12 00101110101011100111ssssssSSSSSS. */
+{ "vperm", 0x2EAE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vperm a,limm,limm 00101110001011100111111110AAAAAA. */
+{ "vperm", 0x2E2E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vperm 0,limm,limm 00101110001011100111111110111110. */
+{ "vperm", 0x2E2E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vperm<.cc> 0,limm,limm 001011101110111001111111100QQQQQ. */
+{ "vperm", 0x2EEE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vrep2hl b,c 00101bbb001011110BBBCCCCCC100010. */
+{ "vrep2hl", 0x282F0022, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vrep2hl 0,c 00101110001011110111CCCCCC100010. */
+{ "vrep2hl", 0x2E2F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vrep2hl b,u6 00101bbb011011110BBBuuuuuu100010. */
+{ "vrep2hl", 0x286F0022, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vrep2hl 0,u6 00101110011011110111uuuuuu100010. */
+{ "vrep2hl", 0x2E6F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vrep2hl b,limm 00101bbb001011110BBB111110100010. */
+{ "vrep2hl", 0x282F0FA2, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vrep2hl 0,limm 00101110001011110111111110100010. */
+{ "vrep2hl", 0x2E2F7FA2, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vrep2hm b,c 00101bbb001011110BBBCCCCCC100011. */
+{ "vrep2hm", 0x282F0023, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vrep2hm 0,c 00101110001011110111CCCCCC100011. */
+{ "vrep2hm", 0x2E2F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vrep2hm b,u6 00101bbb011011110BBBuuuuuu100011. */
+{ "vrep2hm", 0x286F0023, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vrep2hm 0,u6 00101110011011110111uuuuuu100011. */
+{ "vrep2hm", 0x2E6F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vrep2hm b,limm 00101bbb001011110BBB111110100011. */
+{ "vrep2hm", 0x282F0FA3, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vrep2hm 0,limm 00101110001011110111111110100011. */
+{ "vrep2hm", 0x2E2F7FA3, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vsext2bhl b,c 00101bbb001011110BBBCCCCCC100110. */
+{ "vsext2bhl", 0x282F0026, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vsext2bhl 0,c 00101110001011110111CCCCCC100110. */
+{ "vsext2bhl", 0x2E2F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vsext2bhl b,u6 00101bbb011011110BBBuuuuuu100110. */
+{ "vsext2bhl", 0x286F0026, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vsext2bhl 0,u6 00101110011011110111uuuuuu100110. */
+{ "vsext2bhl", 0x2E6F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vsext2bhl b,limm 00101bbb001011110BBB111110100110. */
+{ "vsext2bhl", 0x282F0FA6, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vsext2bhl 0,limm 00101110001011110111111110100110. */
+{ "vsext2bhl", 0x2E2F7FA6, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vsext2bhm b,c 00101bbb001011110BBBCCCCCC100111. */
+{ "vsext2bhm", 0x282F0027, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RC }, { 0 }},
+
+/* vsext2bhm 0,c 00101110001011110111CCCCCC100111. */
+{ "vsext2bhm", 0x2E2F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RC }, { 0 }},
+
+/* vsext2bhm b,u6 00101bbb011011110BBBuuuuuu100111. */
+{ "vsext2bhm", 0x286F0027, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, UIMM6_20 }, { 0 }},
+
+/* vsext2bhm 0,u6 00101110011011110111uuuuuu100111. */
+{ "vsext2bhm", 0x2E6F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, UIMM6_20 }, { 0 }},
+
+/* vsext2bhm b,limm 00101bbb001011110BBB111110100111. */
+{ "vsext2bhm", 0x282F0FA7, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, LIMM }, { 0 }},
+
+/* vsext2bhm 0,limm 00101110001011110111111110100111. */
+{ "vsext2bhm", 0x2E2F7FA7, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM }, { 0 }},
+
+/* vsub2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA. */
+{ "vsub2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsub2 0,b,c 00101bbb001111010BBBCCCCCC111110. */
+{ "vsub2", 0x283D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsub2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ. */
+{ "vsub2", 0x28FD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsub2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA. */
+{ "vsub2", 0x287D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2 0,b,u6 00101bbb011111010BBBuuuuuu111110. */
+{ "vsub2", 0x287D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ. */
+{ "vsub2", 0x28FD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub2 b,b,s12 00101bbb101111010BBBssssssSSSSSS. */
+{ "vsub2", 0x28BD0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub2 a,limm,c 00101110001111010111CCCCCCAAAAAA. */
+{ "vsub2", 0x2E3D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsub2 a,b,limm 00101bbb001111010BBB111110AAAAAA. */
+{ "vsub2", 0x283D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsub2 0,limm,c 00101110001111010111CCCCCC111110. */
+{ "vsub2", 0x2E3D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub2 0,b,limm 00101bbb001111010BBB111110111110. */
+{ "vsub2", 0x283D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ. */
+{ "vsub2", 0x28FD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsub2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ. */
+{ "vsub2", 0x2EFD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub2 a,limm,u6 00101110011111010111uuuuuuAAAAAA. */
+{ "vsub2", 0x2E7D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2 0,limm,u6 00101110011111010111uuuuuu111110. */
+{ "vsub2", 0x2E7D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ. */
+{ "vsub2", 0x2EFD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub2 0,limm,s12 00101110101111010111ssssssSSSSSS. */
+{ "vsub2", 0x2EBD7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub2 a,limm,limm 00101110001111010111111110AAAAAA. */
+{ "vsub2", 0x2E3D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2 0,limm,limm 00101110001111010111111110111110. */
+{ "vsub2", 0x2E3D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ. */
+{ "vsub2", 0x2EFD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsub2h a,b,c 00101bbb000101010BBBCCCCCCAAAAAA. */
+{ "vsub2h", 0x28150000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsub2h 0,b,c 00101bbb000101010BBBCCCCCC111110. */
+{ "vsub2h", 0x2815003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vsub2h<.cc> b,b,c 00101bbb110101010BBBCCCCCC0QQQQQ. */
+{ "vsub2h", 0x28D50000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsub2h a,b,u6 00101bbb010101010BBBuuuuuuAAAAAA. */
+{ "vsub2h", 0x28550000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2h 0,b,u6 00101bbb010101010BBBuuuuuu111110. */
+{ "vsub2h", 0x2855003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub2h<.cc> b,b,u6 00101bbb110101010BBBuuuuuu1QQQQQ. */
+{ "vsub2h", 0x28D50020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub2h b,b,s12 00101bbb100101010BBBssssssSSSSSS. */
+{ "vsub2h", 0x28950000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub2h a,limm,c 00101110000101010111CCCCCCAAAAAA. */
+{ "vsub2h", 0x2E157000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsub2h a,b,limm 00101bbb000101010BBB111110AAAAAA. */
+{ "vsub2h", 0x28150F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsub2h 0,limm,c 00101110000101010111CCCCCC111110. */
+{ "vsub2h", 0x2E15703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub2h 0,b,limm 00101bbb000101010BBB111110111110. */
+{ "vsub2h", 0x28150FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub2h<.cc> b,b,limm 00101bbb110101010BBB1111100QQQQQ. */
+{ "vsub2h", 0x28D50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsub2h<.cc> 0,limm,c 00101110110101010111CCCCCC0QQQQQ. */
+{ "vsub2h", 0x2ED57000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub2h a,limm,u6 00101110010101010111uuuuuuAAAAAA. */
+{ "vsub2h", 0x2E557000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2h 0,limm,u6 00101110010101010111uuuuuu111110. */
+{ "vsub2h", 0x2E55703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub2h<.cc> 0,limm,u6 00101110110101010111uuuuuu1QQQQQ. */
+{ "vsub2h", 0x2ED57020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub2h 0,limm,s12 00101110100101010111ssssssSSSSSS. */
+{ "vsub2h", 0x2E957000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub2h a,limm,limm 00101110000101010111111110AAAAAA. */
+{ "vsub2h", 0x2E157F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2h 0,limm,limm 00101110000101010111111110111110. */
+{ "vsub2h", 0x2E157FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub2h<.cc> 0,limm,limm 001011101101010101111111100QQQQQ. */
+{ "vsub2h", 0x2ED57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsub4b a,b,c 00101bbb001001010BBBCCCCCCAAAAAA. */
+{ "vsub4b", 0x28250000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsub4b 0,b,c 00101bbb001001010BBBCCCCCC111110. */
+{ "vsub4b", 0x2825003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vsub4b<.cc> b,b,c 00101bbb111001010BBBCCCCCC0QQQQQ. */
+{ "vsub4b", 0x28E50000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsub4b a,b,u6 00101bbb011001010BBBuuuuuuAAAAAA. */
+{ "vsub4b", 0x28650000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsub4b 0,b,u6 00101bbb011001010BBBuuuuuu111110. */
+{ "vsub4b", 0x2865003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub4b<.cc> b,b,u6 00101bbb111001010BBBuuuuuu1QQQQQ. */
+{ "vsub4b", 0x28E50020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub4b b,b,s12 00101bbb101001010BBBssssssSSSSSS. */
+{ "vsub4b", 0x28A50000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub4b a,limm,c 00101110001001010111CCCCCCAAAAAA. */
+{ "vsub4b", 0x2E257000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsub4b a,b,limm 00101bbb001001010BBB111110AAAAAA. */
+{ "vsub4b", 0x28250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsub4b 0,limm,c 00101110011001010111CCCCCC111110. */
+{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub4b 0,b,limm 00101bbb001001010BBB111110111110. */
+{ "vsub4b", 0x28250FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub4b<.cc> b,b,limm 00101bbb111001010BBB1111100QQQQQ. */
+{ "vsub4b", 0x28E50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsub4b<.cc> 0,limm,c 00101110111001010111CCCCCC0QQQQQ. */
+{ "vsub4b", 0x2EE57000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub4b a,limm,u6 00101110011001010111uuuuuuAAAAAA. */
+{ "vsub4b", 0x2E657000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub4b 0,limm,u6 00101110011001010111uuuuuu111110. */
+{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub4b<.cc> 0,limm,u6 00101110111001010111uuuuuu1QQQQQ. */
+{ "vsub4b", 0x2EE57020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub4b 0,limm,s12 00101110101001010111ssssssSSSSSS. */
+{ "vsub4b", 0x2EA57000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub4b a,limm,limm 00101110001001010111111110AAAAAA. */
+{ "vsub4b", 0x2E257F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsub4b 0,limm,limm 00101110001001010111111110111110. */
+{ "vsub4b", 0x2E257FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub4b<.cc> 0,limm,limm 001011101110010101111111100QQQQQ. */
+{ "vsub4b", 0x2EE57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsub4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA. */
+{ "vsub4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsub4h 0,b,c 00101bbb001110010BBBCCCCCC111110. */
+{ "vsub4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsub4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ. */
+{ "vsub4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsub4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA. */
+{ "vsub4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsub4h 0,b,u6 00101bbb011110010BBBuuuuuu111110. */
+{ "vsub4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsub4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ. */
+{ "vsub4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsub4h b,b,s12 00101bbb101110010BBBssssssSSSSSS. */
+{ "vsub4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsub4h a,limm,c 00101110001110010111CCCCCCAAAAAA. */
+{ "vsub4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsub4h a,b,limm 00101bbb001110010BBB111110AAAAAA. */
+{ "vsub4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsub4h 0,limm,c 00101110001110010111CCCCCC111110. */
+{ "vsub4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsub4h 0,b,limm 00101bbb001110010BBB111110111110. */
+{ "vsub4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsub4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ. */
+{ "vsub4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsub4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ. */
+{ "vsub4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsub4h a,limm,u6 00101110011110010111uuuuuuAAAAAA. */
+{ "vsub4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub4h 0,limm,u6 00101110011110010111uuuuuu111110. */
+{ "vsub4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsub4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ. */
+{ "vsub4h", 0x2EF97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsub4h 0,limm,s12 00101110101110010111ssssssSSSSSS. */
+{ "vsub4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsub4h a,limm,limm 00101110001110010111111110AAAAAA. */
+{ "vsub4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsub4h 0,limm,limm 00101110001110010111111110111110. */
+{ "vsub4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsub4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ. */
+{ "vsub4h", 0x2EF97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadd a,b,c 00101bbb001111110BBBCCCCCCAAAAAA. */
+{ "vsubadd", 0x283F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubadd 0,b,c 00101bbb001111110BBBCCCCCC111110. */
+{ "vsubadd", 0x283F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadd<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ. */
+{ "vsubadd", 0x28FF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubadd a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA. */
+{ "vsubadd", 0x287F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd 0,b,u6 00101bbb011111110BBBuuuuuu111110. */
+{ "vsubadd", 0x287F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ. */
+{ "vsubadd", 0x28FF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadd b,b,s12 00101bbb101111110BBBssssssSSSSSS. */
+{ "vsubadd", 0x28BF0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadd a,limm,c 00101110001111110111CCCCCCAAAAAA. */
+{ "vsubadd", 0x2E3F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubadd a,b,limm 00101bbb001111110BBB111110AAAAAA. */
+{ "vsubadd", 0x283F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubadd 0,limm,c 00101110001111110111CCCCCC111110. */
+{ "vsubadd", 0x2E3F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadd 0,b,limm 00101bbb001111110BBB111110111110. */
+{ "vsubadd", 0x283F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadd<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ. */
+{ "vsubadd", 0x28FF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubadd<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ. */
+{ "vsubadd", 0x2EFF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadd a,limm,u6 00101110011111110111uuuuuuAAAAAA. */
+{ "vsubadd", 0x2E7F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd 0,limm,u6 00101110011111110111uuuuuu111110. */
+{ "vsubadd", 0x2E7F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ. */
+{ "vsubadd", 0x2EFF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadd 0,limm,s12 00101110101111110111ssssssSSSSSS. */
+{ "vsubadd", 0x2EBF7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadd a,limm,limm 00101110001111110111111110AAAAAA. */
+{ "vsubadd", 0x2E3F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd 0,limm,limm 00101110001111110111111110111110. */
+{ "vsubadd", 0x2E3F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd<.cc> 0,limm,limm 001011101111111101111111100QQQQQ. */
+{ "vsubadd", 0x2EFF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadd2h a,b,c 00101bbb000101110BBBCCCCCCAAAAAA. */
+{ "vsubadd2h", 0x28170000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubadd2h 0,b,c 00101bbb000101110BBBCCCCCC111110. */
+{ "vsubadd2h", 0x2817003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadd2h<.cc> b,b,c 00101bbb110101110BBBCCCCCC0QQQQQ. */
+{ "vsubadd2h", 0x28D70000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubadd2h a,b,u6 00101bbb010101110BBBuuuuuuAAAAAA. */
+{ "vsubadd2h", 0x28570000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h 0,b,u6 00101bbb010101110BBBuuuuuu111110. */
+{ "vsubadd2h", 0x2857003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h<.cc> b,b,u6 00101bbb110101110BBBuuuuuu1QQQQQ. */
+{ "vsubadd2h", 0x28D70020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadd2h b,b,s12 00101bbb100101110BBBssssssSSSSSS. */
+{ "vsubadd2h", 0x28970000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadd2h a,limm,c 00101110000101110111CCCCCCAAAAAA. */
+{ "vsubadd2h", 0x2E177000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubadd2h a,b,limm 00101bbb000101110BBB111110AAAAAA. */
+{ "vsubadd2h", 0x28170F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubadd2h 0,limm,c 00101110000101110111CCCCCC111110. */
+{ "vsubadd2h", 0x2E17703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadd2h 0,b,limm 00101bbb000101110BBB111110111110. */
+{ "vsubadd2h", 0x28170FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadd2h<.cc> b,b,limm 00101bbb110101110BBB1111100QQQQQ. */
+{ "vsubadd2h", 0x28D70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubadd2h<.cc> 0,limm,c 00101110110101110111CCCCCC0QQQQQ. */
+{ "vsubadd2h", 0x2ED77000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadd2h a,limm,u6 00101110010101110111uuuuuuAAAAAA. */
+{ "vsubadd2h", 0x2E577000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h 0,limm,u6 00101110010101110111uuuuuu111110. */
+{ "vsubadd2h", 0x2E57703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd2h<.cc> 0,limm,u6 00101110110101110111uuuuuu1QQQQQ. */
+{ "vsubadd2h", 0x2ED77020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadd2h 0,limm,s12 00101110100101110111ssssssSSSSSS. */
+{ "vsubadd2h", 0x2E977000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadd2h a,limm,limm 00101110000101110111111110AAAAAA. */
+{ "vsubadd2h", 0x2E177F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd2h 0,limm,limm 00101110000101110111111110111110. */
+{ "vsubadd2h", 0x2E177FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd2h<.cc> 0,limm,limm 001011101101011101111111100QQQQQ. */
+{ "vsubadd2h", 0x2ED77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadd4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA. */
+{ "vsubadd4h", 0x283B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubadd4h 0,b,c 00101bbb001110110BBBCCCCCC111110. */
+{ "vsubadd4h", 0x283B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadd4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ. */
+{ "vsubadd4h", 0x28FB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubadd4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA. */
+{ "vsubadd4h", 0x287B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h 0,b,u6 00101bbb011110110BBBuuuuuu111110. */
+{ "vsubadd4h", 0x287B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ. */
+{ "vsubadd4h", 0x28FB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadd4h b,b,s12 00101bbb101110110BBBssssssSSSSSS. */
+{ "vsubadd4h", 0x28BB0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadd4h a,limm,c 00101110001110110111CCCCCCAAAAAA. */
+{ "vsubadd4h", 0x2E3B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubadd4h a,b,limm 00101bbb001110110BBB111110AAAAAA. */
+{ "vsubadd4h", 0x283B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubadd4h 0,limm,c 00101110001110110111CCCCCC111110. */
+{ "vsubadd4h", 0x2E3B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadd4h 0,b,limm 00101bbb001110110BBB111110111110. */
+{ "vsubadd4h", 0x283B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadd4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ. */
+{ "vsubadd4h", 0x28FB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubadd4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ. */
+{ "vsubadd4h", 0x2EFB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadd4h a,limm,u6 00101110011110110111uuuuuuAAAAAA. */
+{ "vsubadd4h", 0x2E7B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h 0,limm,u6 00101110011110110111uuuuuu111110. */
+{ "vsubadd4h", 0x2E7B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadd4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ. */
+{ "vsubadd4h", 0x2EFB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadd4h 0,limm,s12 00101110101110110111ssssssSSSSSS. */
+{ "vsubadd4h", 0x2EBB7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadd4h a,limm,limm 00101110001110110111111110AAAAAA. */
+{ "vsubadd4h", 0x2E3B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd4h 0,limm,limm 00101110001110110111111110111110. */
+{ "vsubadd4h", 0x2E3B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadd4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ. */
+{ "vsubadd4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadds a,b,c 00101bbb001111110BBBCCCCCCAAAAAA. */
+{ "vsubadds", 0x283F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubadds 0,b,c 00101bbb001111110BBBCCCCCC111110. */
+{ "vsubadds", 0x283F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadds<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ. */
+{ "vsubadds", 0x28FF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubadds a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA. */
+{ "vsubadds", 0x287F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadds 0,b,u6 00101bbb011111110BBBuuuuuu111110. */
+{ "vsubadds", 0x287F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadds<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ. */
+{ "vsubadds", 0x28FF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadds b,b,s12 00101bbb101111110BBBssssssSSSSSS. */
+{ "vsubadds", 0x28BF0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadds a,limm,c 00101110001111110111CCCCCCAAAAAA. */
+{ "vsubadds", 0x2E3F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubadds a,b,limm 00101bbb001111110BBB111110AAAAAA. */
+{ "vsubadds", 0x283F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubadds 0,limm,c 00101110001111110111CCCCCC111110. */
+{ "vsubadds", 0x2E3F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadds 0,b,limm 00101bbb001111110BBB111110111110. */
+{ "vsubadds", 0x283F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadds<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ. */
+{ "vsubadds", 0x28FF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubadds<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ. */
+{ "vsubadds", 0x2EFF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadds a,limm,u6 00101110011111110111uuuuuuAAAAAA. */
+{ "vsubadds", 0x2E7F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadds 0,limm,u6 00101110011111110111uuuuuu111110. */
+{ "vsubadds", 0x2E7F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadds<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ. */
+{ "vsubadds", 0x2EFF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadds 0,limm,s12 00101110101111110111ssssssSSSSSS. */
+{ "vsubadds", 0x2EBF7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadds a,limm,limm 00101110001111110111111110AAAAAA. */
+{ "vsubadds", 0x2E3F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadds 0,limm,limm 00101110001111110111111110111110. */
+{ "vsubadds", 0x2E3F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadds<.cc> 0,limm,limm 001011101111111101111111100QQQQQ. */
+{ "vsubadds", 0x2EFF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadds2h a,b,c 00101bbb000101111BBBCCCCCCAAAAAA. */
+{ "vsubadds2h", 0x28178000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubadds2h 0,b,c 00101bbb000101111BBBCCCCCC111110. */
+{ "vsubadds2h", 0x2817803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vsubadds2h<.cc> b,b,c 00101bbb110101111BBBCCCCCC0QQQQQ. */
+{ "vsubadds2h", 0x28D78000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubadds2h a,b,u6 00101bbb010101111BBBuuuuuuAAAAAA. */
+{ "vsubadds2h", 0x28578000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadds2h 0,b,u6 00101bbb010101111BBBuuuuuu111110. */
+{ "vsubadds2h", 0x2857803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadds2h<.cc> b,b,u6 00101bbb110101111BBBuuuuuu1QQQQQ. */
+{ "vsubadds2h", 0x28D78020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadds2h b,b,s12 00101bbb100101111BBBssssssSSSSSS. */
+{ "vsubadds2h", 0x28978000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadds2h a,limm,c 00101110000101111111CCCCCCAAAAAA. */
+{ "vsubadds2h", 0x2E17F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubadds2h a,b,limm 00101bbb000101111BBB111110AAAAAA. */
+{ "vsubadds2h", 0x28178F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubadds2h 0,limm,c 00101110000101111111CCCCCC111110. */
+{ "vsubadds2h", 0x2E17F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadds2h 0,b,limm 00101bbb000101111BBB111110111110. */
+{ "vsubadds2h", 0x28178FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadds2h<.cc> b,b,limm 00101bbb110101111BBB1111100QQQQQ. */
+{ "vsubadds2h", 0x28D78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubadds2h<.cc> 0,limm,c 00101110110101111111CCCCCC0QQQQQ. */
+{ "vsubadds2h", 0x2ED7F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadds2h a,limm,u6 00101110010101111111uuuuuuAAAAAA. */
+{ "vsubadds2h", 0x2E57F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadds2h 0,limm,u6 00101110010101111111uuuuuu111110. */
+{ "vsubadds2h", 0x2E57F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadds2h<.cc> 0,limm,u6 00101110110101111111uuuuuu1QQQQQ. */
+{ "vsubadds2h", 0x2ED7F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadds2h 0,limm,s12 00101110100101111111ssssssSSSSSS. */
+{ "vsubadds2h", 0x2E97F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadds2h a,limm,limm 00101110000101111111111110AAAAAA. */
+{ "vsubadds2h", 0x2E17FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadds2h 0,limm,limm 00101110000101111111111110111110. */
+{ "vsubadds2h", 0x2E17FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadds2h<.cc> 0,limm,limm 001011101101011111111111100QQQQQ. */
+{ "vsubadds2h", 0x2ED7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubadds4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA. */
+{ "vsubadds4h", 0x283B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubadds4h 0,b,c 00101bbb001110110BBBCCCCCC111110. */
+{ "vsubadds4h", 0x283B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsubadds4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ. */
+{ "vsubadds4h", 0x28FB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubadds4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA. */
+{ "vsubadds4h", 0x287B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadds4h 0,b,u6 00101bbb011110110BBBuuuuuu111110. */
+{ "vsubadds4h", 0x287B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubadds4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ. */
+{ "vsubadds4h", 0x28FB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubadds4h b,b,s12 00101bbb101110110BBBssssssSSSSSS. */
+{ "vsubadds4h", 0x28BB0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubadds4h a,limm,c 00101110001110110111CCCCCCAAAAAA. */
+{ "vsubadds4h", 0x2E3B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubadds4h a,b,limm 00101bbb001110110BBB111110AAAAAA. */
+{ "vsubadds4h", 0x283B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubadds4h 0,limm,c 00101110001110110111CCCCCC111110. */
+{ "vsubadds4h", 0x2E3B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubadds4h 0,b,limm 00101bbb001110110BBB111110111110. */
+{ "vsubadds4h", 0x283B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubadds4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ. */
+{ "vsubadds4h", 0x28FB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubadds4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ. */
+{ "vsubadds4h", 0x2EFB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubadds4h a,limm,u6 00101110011110110111uuuuuuAAAAAA. */
+{ "vsubadds4h", 0x2E7B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadds4h 0,limm,u6 00101110011110110111uuuuuu111110. */
+{ "vsubadds4h", 0x2E7B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubadds4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ. */
+{ "vsubadds4h", 0x2EFB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubadds4h 0,limm,s12 00101110101110110111ssssssSSSSSS. */
+{ "vsubadds4h", 0x2EBB7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubadds4h a,limm,limm 00101110001110110111111110AAAAAA. */
+{ "vsubadds4h", 0x2E3B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadds4h 0,limm,limm 00101110001110110111111110111110. */
+{ "vsubadds4h", 0x2E3B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubadds4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ. */
+{ "vsubadds4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubs2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA. */
+{ "vsubs2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubs2 0,b,c 00101bbb001111010BBBCCCCCC111110. */
+{ "vsubs2", 0x283D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsubs2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ. */
+{ "vsubs2", 0x28FD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubs2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA. */
+{ "vsubs2", 0x287D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubs2 0,b,u6 00101bbb011111010BBBuuuuuu111110. */
+{ "vsubs2", 0x287D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubs2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ. */
+{ "vsubs2", 0x28FD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubs2 b,b,s12 00101bbb101111010BBBssssssSSSSSS. */
+{ "vsubs2", 0x28BD0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubs2 a,limm,c 00101110001111010111CCCCCCAAAAAA. */
+{ "vsubs2", 0x2E3D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubs2 a,b,limm 00101bbb001111010BBB111110AAAAAA. */
+{ "vsubs2", 0x283D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubs2 0,limm,c 00101110001111010111CCCCCC111110. */
+{ "vsubs2", 0x2E3D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubs2 0,b,limm 00101bbb001111010BBB111110111110. */
+{ "vsubs2", 0x283D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubs2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ. */
+{ "vsubs2", 0x28FD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubs2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ. */
+{ "vsubs2", 0x2EFD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubs2 a,limm,u6 00101110011111010111uuuuuuAAAAAA. */
+{ "vsubs2", 0x2E7D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubs2 0,limm,u6 00101110011111010111uuuuuu111110. */
+{ "vsubs2", 0x2E7D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubs2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ. */
+{ "vsubs2", 0x2EFD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubs2 0,limm,s12 00101110101111010111ssssssSSSSSS. */
+{ "vsubs2", 0x2EBD7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubs2 a,limm,limm 00101110001111010111111110AAAAAA. */
+{ "vsubs2", 0x2E3D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubs2 0,limm,limm 00101110001111010111111110111110. */
+{ "vsubs2", 0x2E3D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubs2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ. */
+{ "vsubs2", 0x2EFD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubs2h a,b,c 00101bbb000101011BBBCCCCCCAAAAAA. */
+{ "vsubs2h", 0x28158000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubs2h 0,b,c 00101bbb000101011BBBCCCCCC111110. */
+{ "vsubs2h", 0x2815803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, RC }, { 0 }},
+
+/* vsubs2h<.cc> b,b,c 00101bbb110101011BBBCCCCCC0QQQQQ. */
+{ "vsubs2h", 0x28D58000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubs2h a,b,u6 00101bbb010101011BBBuuuuuuAAAAAA. */
+{ "vsubs2h", 0x28558000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubs2h 0,b,u6 00101bbb010101011BBBuuuuuu111110. */
+{ "vsubs2h", 0x2855803E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubs2h<.cc> b,b,u6 00101bbb110101011BBBuuuuuu1QQQQQ. */
+{ "vsubs2h", 0x28D58020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubs2h b,b,s12 00101bbb100101011BBBssssssSSSSSS. */
+{ "vsubs2h", 0x28958000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubs2h a,limm,c 00101110000101011111CCCCCCAAAAAA. */
+{ "vsubs2h", 0x2E15F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubs2h a,b,limm 00101bbb000101011BBB111110AAAAAA. */
+{ "vsubs2h", 0x28158F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubs2h 0,limm,c 00101110000101011111CCCCCC111110. */
+{ "vsubs2h", 0x2E15F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubs2h 0,b,limm 00101bbb000101011BBB111110111110. */
+{ "vsubs2h", 0x28158FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubs2h<.cc> b,b,limm 00101bbb110101011BBB1111100QQQQQ. */
+{ "vsubs2h", 0x28D58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubs2h<.cc> 0,limm,c 00101110110101011111CCCCCC0QQQQQ. */
+{ "vsubs2h", 0x2ED5F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubs2h a,limm,u6 00101110010101011111uuuuuuAAAAAA. */
+{ "vsubs2h", 0x2E55F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubs2h 0,limm,u6 00101110010101011111uuuuuu111110. */
+{ "vsubs2h", 0x2E55F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubs2h<.cc> 0,limm,u6 00101110110101011111uuuuuu1QQQQQ. */
+{ "vsubs2h", 0x2ED5F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubs2h 0,limm,s12 00101110100101011111ssssssSSSSSS. */
+{ "vsubs2h", 0x2E95F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubs2h a,limm,limm 00101110000101011111111110AAAAAA. */
+{ "vsubs2h", 0x2E15FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubs2h 0,limm,limm 00101110000101011111111110111110. */
+{ "vsubs2h", 0x2E15FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubs2h<.cc> 0,limm,limm 001011101101010111111111100QQQQQ. */
+{ "vsubs2h", 0x2ED5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* vsubs4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA. */
+{ "vsubs4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, RC }, { 0 }},
+
+/* vsubs4h 0,b,c 00101bbb001110010BBBCCCCCC111110. */
+{ "vsubs4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, RC }, { 0 }},
+
+/* vsubs4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ. */
+{ "vsubs4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, RC }, { C_CC }},
+
+/* vsubs4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA. */
+{ "vsubs4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, UIMM6_20 }, { 0 }},
+
+/* vsubs4h 0,b,u6 00101bbb011110010BBBuuuuuu111110. */
+{ "vsubs4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }},
+
+/* vsubs4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ. */
+{ "vsubs4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, UIMM6_20 }, { C_CC }},
+
+/* vsubs4h b,b,s12 00101bbb101110010BBBssssssSSSSSS. */
+{ "vsubs4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, SIMM12_20 }, { 0 }},
+
+/* vsubs4h a,limm,c 00101110001110010111CCCCCCAAAAAA. */
+{ "vsubs4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, RC }, { 0 }},
+
+/* vsubs4h a,b,limm 00101bbb001110010BBB111110AAAAAA. */
+{ "vsubs4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, RB, LIMM }, { 0 }},
+
+/* vsubs4h 0,limm,c 00101110001110010111CCCCCC111110. */
+{ "vsubs4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { 0 }},
+
+/* vsubs4h 0,b,limm 00101bbb001110010BBB111110111110. */
+{ "vsubs4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, RB, LIMM }, { 0 }},
+
+/* vsubs4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ. */
+{ "vsubs4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RB_CHK, RBdup, LIMM }, { C_CC }},
+
+/* vsubs4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ. */
+{ "vsubs4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, RC }, { C_CC }},
+
+/* vsubs4h a,limm,u6 00101110011110010111uuuuuuAAAAAA. */
+{ "vsubs4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubs4h 0,limm,u6 00101110011110010111uuuuuu111110. */
+{ "vsubs4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }},
+
+/* vsubs4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ. */
+{ "vsubs4h", 0x2EF97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }},
+
+/* vsubs4h 0,limm,s12 00101110101110010111ssssssSSSSSS. */
+{ "vsubs4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }},
+
+/* vsubs4h a,limm,limm 00101110001110010111111110AAAAAA. */
+{ "vsubs4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { RA_CHK, LIMM, LIMMdup }, { 0 }},
+
+/* vsubs4h 0,limm,limm 00101110001110010111111110111110. */
+{ "vsubs4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }},
+
+/* vsubs4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ. */
+{ "vsubs4h", 0x2EF97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, MPY, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }},
+
+/* wevt c 00100000001011110001CCCCCC111111. */
+{ "wevt", 0x202F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { RC }, { 0 }},
+
+/* wevt 00100000011011110001000000111111. */
+{ "wevt", 0x206F103F, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { 0 }, { 0 }},
+
+/* wevt u6 00100000011011110001uuuuuu111111. */
+{ "wevt", 0x206F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { UIMM6_20 }, { 0 }},
+
+/* wlfc c 00100001001011110001CCCCCC111111. */
+{ "wlfc", 0x212F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { RC }, { 0 }},
+
+/* wlfc u6 00100001011011110001uuuuuu111111. */
+{ "wlfc", 0x216F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, KERNEL, NONE, { UIMM6_20 }, { 0 }},
+
+/* xbfu<.f> a,b,c 00100bbb00101101FBBBCCCCCCAAAAAA. */
+{ "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, RB, RC }, { C_F }},
+
+/* xbfu<.f> 0,b,c 00100bbb00101101FBBBCCCCCC111110. */
+{ "xbfu", 0x202D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, RB, RC }, { C_F }},
+
+/* xbfu<.f><.cc> b,b,c 00100bbb11101101FBBBCCCCCC0QQQQQ. */
+{ "xbfu", 0x20ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xbfu<.f> a,b,u6 00100bbb01101101FBBBuuuuuuAAAAAA. */
+{ "xbfu", 0x206D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f> 0,b,u6 00100bbb01101101FBBBuuuuuu111110. */
+{ "xbfu", 0x206D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f><.cc> b,b,u6 00100bbb11101101FBBBuuuuuu1QQQQQ. */
+{ "xbfu", 0x20ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbfu<.f> b,b,s12 00100bbb10101101FBBBssssssSSSSSS. */
+{ "xbfu", 0x20AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xbfu<.f> a,limm,c 0010011000101101F111CCCCCCAAAAAA. */
+{ "xbfu", 0x262D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, LIMM, RC }, { C_F }},
+
+/* xbfu<.f> a,b,limm 00100bbb00101101FBBB111110AAAAAA. */
+{ "xbfu", 0x202D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, RB, LIMM }, { C_F }},
+
+/* xbfu<.f> 0,limm,c 0010011000101101F111CCCCCC111110. */
+{ "xbfu", 0x262D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F }},
+
+/* xbfu<.f> 0,b,limm 00100bbb00101101FBBB111110111110. */
+{ "xbfu", 0x202D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, RB, LIMM }, { C_F }},
+
+/* xbfu<.f><.cc> b,b,limm 00100bbb11101101FBBB1111100QQQQQ. */
+{ "xbfu", 0x20ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* xbfu<.f><.cc> 0,limm,c 0010011011101101F111CCCCCC0QQQQQ. */
+{ "xbfu", 0x26ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* xbfu<.f> a,limm,u6 0010011001101101F111uuuuuuAAAAAA. */
+{ "xbfu", 0x266D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f> 0,limm,u6 0010011001101101F111uuuuuu111110. */
+{ "xbfu", 0x266D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xbfu<.f><.cc> 0,limm,u6 0010011011101101F111uuuuuu1QQQQQ. */
+{ "xbfu", 0x26ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbfu<.f> 0,limm,s12 0010011010101101F111ssssssSSSSSS. */
+{ "xbfu", 0x26AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* xbfu<.f> a,limm,limm 0010011000101101F111111110AAAAAA. */
+{ "xbfu", 0x262D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* xbfu<.f> 0,limm,limm 0010011000101101F111111110111110. */
+{ "xbfu", 0x262D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* xbfu<.f><.cc> 0,limm,limm 0010011011101101F1111111100QQQQQ. */
+{ "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* xbful<.f> RA,RB,RC 01011bbb00101101FBBBccccccaaaaaa. */
+{ "xbful", 0x582D0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* xbful<.f> 0,RB,RC 01011bbb00101101FBBBcccccc111110. */
+{ "xbful", 0x582D003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* xbful<.f><.cc> RB,RB,RC 01011bbb11101101FBBBcccccc0QQQQQ. */
+{ "xbful", 0x58ED0000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xbful<.f> RA,RB,u6 01011bbb01101101FBBBuuuuuuaaaaaa. */
+{ "xbful", 0x586D0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xbful<.f> 0,RB,u6 01011bbb01101101FBBBuuuuuu111110. */
+{ "xbful", 0x586D003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* xbful<.f><.cc> RB,RB,u6 01011bbb11101101FBBBuuuuuu1QQQQQ. */
+{ "xbful", 0x58ED0020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbful<.f> RB,RB,s12 01011bbb10101101FBBBssssssSSSSSS. */
+{ "xbful", 0x58AD0000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xbful<.f> RA,ximm,RC 0101110000101101F111ccccccaaaaaa. */
+{ "xbful", 0x5C2D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* xbful<.f> RA,RB,ximm 01011bbb00101101FBBB111100aaaaaa. */
+{ "xbful", 0x582D0F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* xbful<.f> 0,ximm,RC 0101110000101101F111cccccc111110. */
+{ "xbful", 0x5C2D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* xbful<.f> 0,RB,ximm 01011bbb00101101FBBB111100111110. */
+{ "xbful", 0x582D0F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* xbful<.f><.cc> 0,ximm,RC 0101110011101101F111cccccc0QQQQQ. */
+{ "xbful", 0x5CED7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* xbful<.f><.cc> RB,RB,ximm 01011bbb11101101FBBB1111000QQQQQ. */
+{ "xbful", 0x58ED0F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* xbful<.f> RA,ximm,u6 0101110001101101F111uuuuuuaaaaaa. */
+{ "xbful", 0x5C6D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* xbful<.f> 0,ximm,u6 0101110001101101F111uuuuuu111110. */
+{ "xbful", 0x5C6D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* xbful<.f><.cc> 0,ximm,u6 0101110011101101F111uuuuuu1QQQQQ. */
+{ "xbful", 0x5CED7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbful<.f> RA,limm,RC 0101111000101101F111ccccccaaaaaa. */
+{ "xbful", 0x5E2D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* xbful<.f> RA,RB,limm 01011bbb00101101FBBB111110aaaaaa. */
+{ "xbful", 0x582D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* xbful<.f> 0,limm,RC 0101111000101101F111cccccc111110. */
+{ "xbful", 0x5E2D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* xbful<.f> 0,RB,limm 01011bbb00101101FBBB111110111110. */
+{ "xbful", 0x582D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* xbful<.f><.cc> 0,limm,RC 0101111011101101F111cccccc0QQQQQ. */
+{ "xbful", 0x5EED7000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* xbful<.f><.cc> RB,RB,limm 01011bbb11101101FBBB1111100QQQQQ. */
+{ "xbful", 0x58ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* xbful<.f> RA,limm,u6 0101111001101101F111uuuuuuaaaaaa. */
+{ "xbful", 0x5E6D7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xbful<.f> 0,limm,u6 0101111001101101F111uuuuuu111110. */
+{ "xbful", 0x5E6D703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xbful<.f><.cc> 0,limm,u6 0101111011101101F111uuuuuu1QQQQQ. */
+{ "xbful", 0x5EED7020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xbful<.f> 0,ximm,s12 0101110010101101F111ssssssSSSSSS. */
+{ "xbful", 0x5CAD7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* xbful<.f> 0,limm,s12 0101111010101101F111ssssssSSSSSS. */
+{ "xbful", 0x5EAD7000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* xbful<.f> RA,ximm,ximm 0101110000101101F111111100aaaaaa. */
+{ "xbful", 0x5C2D7F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* xbful<.f> 0,ximm,ximm 0101110000101101F111111100111110. */
+{ "xbful", 0x5C2D7F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* xbful<.f><.cc> 0,ximm,ximm 0101110011101101F1111111000QQQQQ. */
+{ "xbful", 0x5CED7F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* xbful<.f> RA,limm,limm 0101111000101101F111111110aaaaaa. */
+{ "xbful", 0x5E2D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* xbful<.f> 0,limm,limm 0101111000101101F111111110111110. */
+{ "xbful", 0x5E2D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* xbful<.f><.cc> 0,limm,limm 0101111011101101F1111111100QQQQQ. */
+{ "xbful", 0x5EED7F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* xor<.f> a,b,c 00100bbb00000111FBBBCCCCCCAAAAAA. */
+{ "xor", 0x20070000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
+
+/* xor<.f> 0,b,c 00100bbb00000111FBBBCCCCCC111110. */
+{ "xor", 0x2007003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, RC }, { C_F }},
+
+/* xor<.f><.cc> b,b,c 00100bbb11000111FBBBCCCCCC0QQQQQ. */
+{ "xor", 0x20C70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xor<.f> a,b,u6 00100bbb01000111FBBBuuuuuuAAAAAA. */
+{ "xor", 0x20470000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xor<.f> 0,b,u6 00100bbb01000111FBBBuuuuuu111110. */
+{ "xor", 0x2047003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* xor<.f><.cc> b,b,u6 00100bbb11000111FBBBuuuuuu1QQQQQ. */
+{ "xor", 0x20C70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xor<.f> b,b,s12 00100bbb10000111FBBBssssssSSSSSS. */
+{ "xor", 0x20870000, 0xF8FF0000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xor<.f> a,limm,c 0010011000000111F111CCCCCCAAAAAA. */
+{ "xor", 0x26077000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* xor<.f> a,b,limm 00100bbb00000111FBBB111110AAAAAA. */
+{ "xor", 0x20070F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* xor<.f> 0,limm,c 0010011000000111F111CCCCCC111110. */
+{ "xor", 0x2607703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* xor<.f> 0,b,limm 00100bbb00000111FBBB111110111110. */
+{ "xor", 0x20070FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* xor<.f><.cc> 0,limm,c 0010011011000111F111CCCCCC0QQQQQ. */
+{ "xor", 0x26C77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* xor<.f><.cc> b,b,limm 00100bbb11000111FBBB1111100QQQQQ. */
+{ "xor", 0x20C70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* xor<.f> a,limm,u6 0010011001000111F111uuuuuuAAAAAA. */
+{ "xor", 0x26477000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xor<.f> 0,limm,u6 0010011001000111F111uuuuuu111110. */
+{ "xor", 0x2647703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xor<.f><.cc> 0,limm,u6 0010011011000111F111uuuuuu1QQQQQ. */
+{ "xor", 0x26C77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xor<.f> 0,limm,s12 0010011010000111F111ssssssSSSSSS. */
+{ "xor", 0x26877000, 0xFFFF7000, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* xor<.f> a,limm,limm 0010011000000111F111111110AAAAAA. */
+{ "xor", 0x26077F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* xor<.f> 0,limm,limm 0010011000000111F111111110111110. */
+{ "xor", 0x26077FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* xor<.f><.cc> 0,limm,limm 0010011011000111F1111111100QQQQQ. */
+{ "xor", 0x26C77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* xorl<.f> RA,RB,RC 01011bbb00000111FBBBccccccaaaaaa. */
+{ "xorl", 0x58070000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, RC }, { C_F }},
+
+/* xorl<.f> 0,RB,RC 01011bbb00000111FBBBcccccc111110. */
+{ "xorl", 0x5807003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+
+/* xorl<.f><.cc> RB,RB,RC 01011bbb11000111FBBBcccccc0QQQQQ. */
+{ "xorl", 0x58C70000, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }},
+
+/* xorl<.f> RA,RB,u6 01011bbb01000111FBBBuuuuuuaaaaaa. */
+{ "xorl", 0x58470000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+
+/* xorl<.f> 0,RB,u6 01011bbb01000111FBBBuuuuuu111110. */
+{ "xorl", 0x5847003E, 0xF8FF003F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+
+/* xorl<.f><.cc> RB,RB,u6 01011bbb11000111FBBBuuuuuu1QQQQQ. */
+{ "xorl", 0x58C70020, 0xF8FF0020, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+/* xorl<.f> RB,RB,s12 01011bbb10000111FBBBssssssSSSSSS. */
+{ "xorl", 0x58870000, 0xF8FF0000, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }},
+
+/* xorl<.f> RA,ximm,RC 0101110000000111F111ccccccaaaaaa. */
+{ "xorl", 0x5C077000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, RC }, { C_F }},
+
+/* xorl<.f> RA,RB,ximm 01011bbb00000111FBBB111100aaaaaa. */
+{ "xorl", 0x58070F00, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, XIMM }, { C_F }},
+
+/* xorl<.f> 0,ximm,RC 0101110000000111F111cccccc111110. */
+{ "xorl", 0x5C07703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F }},
+
+/* xorl<.f> 0,RB,ximm 01011bbb00000111FBBB111100111110. */
+{ "xorl", 0x58070F3E, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, XIMM }, { C_F }},
+
+/* xorl<.f><.cc> 0,ximm,RC 0101110011000111F111cccccc0QQQQQ. */
+{ "xorl", 0x5CC77000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, RC }, { C_F, C_CC }},
+
+/* xorl<.f><.cc> RB,RB,ximm 01011bbb11000111FBBB1111000QQQQQ. */
+{ "xorl", 0x58C70F00, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, XIMM }, { C_F, C_CC }},
+
+/* xorl<.f> RA,ximm,u6 0101110001000111F111uuuuuuaaaaaa. */
+{ "xorl", 0x5C477000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, UIMM6_20 }, { C_F }},
+
+/* xorl<.f> 0,ximm,u6 0101110001000111F111uuuuuu111110. */
+{ "xorl", 0x5C47703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F }},
+
+/* xorl<.f><.cc> 0,ximm,u6 0101110011000111F111uuuuuu1QQQQQ. */
+{ "xorl", 0x5CC77020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xorl<.f> RA,limm,RC 0101111000000111F111ccccccaaaaaa. */
+{ "xorl", 0x5E077000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+
+/* xorl<.f> RA,RB,limm 01011bbb00000111FBBB111110aaaaaa. */
+{ "xorl", 0x58070F80, 0xF8FF0FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+
+/* xorl<.f> 0,limm,RC 0101111000000111F111cccccc111110. */
+{ "xorl", 0x5E07703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+
+/* xorl<.f> 0,RB,limm 01011bbb00000111FBBB111110111110. */
+{ "xorl", 0x58070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+
+/* xorl<.f><.cc> 0,limm,RC 0101111011000111F111cccccc0QQQQQ. */
+{ "xorl", 0x5EC77000, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }},
+
+/* xorl<.f><.cc> RB,RB,limm 01011bbb11000111FBBB1111100QQQQQ. */
+{ "xorl", 0x58C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC64, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
+
+/* xorl<.f> RA,limm,u6 0101111001000111F111uuuuuuaaaaaa. */
+{ "xorl", 0x5E477000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xorl<.f> 0,limm,u6 0101111001000111F111uuuuuu111110. */
+{ "xorl", 0x5E47703E, 0xFFFF703F, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+
+/* xorl<.f><.cc> 0,limm,u6 0101111011000111F111uuuuuu1QQQQQ. */
+{ "xorl", 0x5EC77020, 0xFFFF7020, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }},
+
+/* xorl<.f> 0,ximm,s12 0101110010000111F111ssssssSSSSSS. */
+{ "xorl", 0x5C877000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, SIMM12_20 }, { C_F }},
+
+/* xorl<.f> 0,limm,s12 0101111010000111F111ssssssSSSSSS. */
+{ "xorl", 0x5E877000, 0xFFFF7000, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }},
+
+/* xorl<.f> RA,ximm,ximm 0101110000000111F111111100aaaaaa. */
+{ "xorl", 0x5C077F00, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, XIMM, XIMMdup }, { C_F }},
+
+/* xorl<.f> 0,ximm,ximm 0101110000000111F111111100111110. */
+{ "xorl", 0x5C077F3E, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F }},
+
+/* xorl<.f><.cc> 0,ximm,ximm 0101110011000111F1111111000QQQQQ. */
+{ "xorl", 0x5CC77F00, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, XIMM, XIMMdup }, { C_F, C_CC }},
+
+/* xorl<.f> RA,limm,limm 0101111000000111F111111110aaaaaa. */
+{ "xorl", 0x5E077F80, 0xFFFF7FC0, ARC_OPCODE_ARC64, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+
+/* xorl<.f> 0,limm,limm 0101111000000111F111111110111110. */
+{ "xorl", 0x5E077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }},
+
+/* xorl<.f><.cc> 0,limm,limm 0101111011000111F1111111100QQQQQ. */
+{ "xorl", 0x5EC77F80, 0xFFFF7FE0, ARC_OPCODE_ARC64, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
+
+/* xor_s b,b,c 01111bbbccc00111. */
+{ "xor_s", 0x00007807, 0x0000F81F, ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }},
+
--
2.31.1
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