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#include "cc2500_REG.h"
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#include "cc2500_VAL.h"
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#include <SPI.h>
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#define CC2500_SIDLE 0x36 // Exit RX / TX, turn
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#define CC2500_STX 0x35 // Enable TX. If in RX state, only enable TX if CCA passes
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#define CC2500_SFTX 0x3B // Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states
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#define CC2500_SRES 0x30
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char vertragingA = 1; // No delay is also possible
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char vertragingB = 200; // 100 doesn't work (to fast), 150 works + safety margin (empirical)
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int KNOP1;
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void WriteReg(char addr, char value){
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digitalWrite(SS,LOW);
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while (digitalRead(MISO) == HIGH) {
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};
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SPI.transfer(addr);
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delayMicroseconds(vertragingB);
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SPI.transfer(value);
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digitalWrite(SS,HIGH);
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}
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void SendStrobe(char strobe){
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digitalWrite(SS,LOW);
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while (digitalRead(MISO) == HIGH) {
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};
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SPI.transfer(strobe);
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digitalWrite(SS,HIGH);
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delayMicroseconds(vertragingB);
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}
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void init_CC2500(){
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WriteReg(REG_IOCFG2,VAL_IOCFG2);
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WriteReg(REG_IOCFG0,VAL_IOCFG0);
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WriteReg(REG_PKTLEN,VAL_PKTLEN);
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WriteReg(REG_PKTCTRL1,VAL_PKTCTRL1);
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WriteReg(REG_PKTCTRL0,VAL_PKTCTRL0);
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WriteReg(REG_ADDR,VAL_ADDR);
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WriteReg(REG_CHANNR,VAL_CHANNR);
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WriteReg(REG_FSCTRL1,VAL_FSCTRL1);
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WriteReg(REG_FSCTRL0,VAL_FSCTRL0);
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WriteReg(REG_FREQ2,VAL_FREQ2);
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WriteReg(REG_FREQ1,VAL_FREQ1);
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WriteReg(REG_FREQ0,VAL_FREQ0);
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WriteReg(REG_MDMCFG4,VAL_MDMCFG4);
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WriteReg(REG_MDMCFG3,VAL_MDMCFG3);
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WriteReg(REG_MDMCFG2,VAL_MDMCFG2);
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WriteReg(REG_MDMCFG1,VAL_MDMCFG1);
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WriteReg(REG_MDMCFG0,VAL_MDMCFG0);
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WriteReg(REG_DEVIATN,VAL_DEVIATN);
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WriteReg(REG_MCSM2,VAL_MCSM2);
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WriteReg(REG_MCSM1,VAL_MCSM1);
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WriteReg(REG_MCSM0,VAL_MCSM0);
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WriteReg(REG_FOCCFG,VAL_FOCCFG);
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WriteReg(REG_BSCFG,VAL_BSCFG);
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WriteReg(REG_AGCCTRL2,VAL_AGCCTRL2);
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WriteReg(REG_AGCCTRL1,VAL_AGCCTRL1);
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WriteReg(REG_AGCCTRL0,VAL_AGCCTRL0);
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WriteReg(REG_WOREVT1,VAL_WOREVT1);
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WriteReg(REG_WOREVT0,VAL_WOREVT0);
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WriteReg(REG_WORCTRL,VAL_WORCTRL);
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WriteReg(REG_FREND1,VAL_FREND1);
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WriteReg(REG_FREND0,VAL_FREND0);
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WriteReg(REG_FSCAL3,VAL_FSCAL3);
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WriteReg(REG_FSCAL2,VAL_FSCAL2);
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WriteReg(REG_FSCAL1,VAL_FSCAL1);
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WriteReg(REG_FSCAL0,VAL_FSCAL0);
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WriteReg(REG_RCCTRL1,VAL_RCCTRL1);
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WriteReg(REG_RCCTRL0,VAL_RCCTRL0);
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WriteReg(REG_FSTEST,VAL_FSTEST);
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WriteReg(REG_TEST2,VAL_TEST2);
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WriteReg(REG_TEST1,VAL_TEST1);
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WriteReg(REG_TEST0,VAL_TEST0);
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WriteReg(REG_DAFUQ,VAL_DAFUQ);
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}
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boolean LIGHTOFF = false; //Used for turning the light on and off
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void setup(){
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pinMode(2, INPUT_PULLUP);
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pinMode(SS,OUTPUT);
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SPI.begin();
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SPI.beginTransaction(SPISettings(6000000, MSBFIRST, SPI_MODE0)); //Faster SPI mode, maximal speed for the CC2500 without the need for extra delays
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digitalWrite(SS,HIGH);
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SendStrobe(CC2500_SRES); //0x30 SRES Reset chip.
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init_CC2500();
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// SendStrobe(CC2500_SPWD); //Enter power down mode - Not used in the prototype
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WriteReg(0x3E,0xFF); //Maximum transmit power - write 0xFF to 0x3E (PATABLE)
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}
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void loop(){
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if(LIGHTOFF){
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for(byte i=0;i<50;i++){ //Send 50 times
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SendStrobe(CC2500_SIDLE); //0x36 SIDLE Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable.
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SendStrobe(CC2500_SFTX); //0x3B SFTX Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states.
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digitalWrite(SS,LOW);
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while (digitalRead(MISO) == HIGH) { };
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SPI.transfer(0x7F);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x06);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x55);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x01);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x3E);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x94);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x03); //3 = Turn light on full power
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delayMicroseconds(vertragingA);
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SPI.transfer(0xAA);
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delayMicroseconds(vertragingA);
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SPI.transfer(0xFF);
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digitalWrite(SS,HIGH);
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SendStrobe(CC2500_STX); //0x35 STX In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: Only go to TX if channel is clear
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delayMicroseconds(vertragingA*10); //Longer delay for transmitting
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}
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LIGHTOFF=false;
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}
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else{
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for(byte i=0;i<50;i++){ //Send 50 times
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SendStrobe(CC2500_SIDLE); //0x36 SIDLE Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable.
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SendStrobe(CC2500_SFTX); //0x3B SFTX Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states.
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digitalWrite(SS,LOW);
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while (digitalRead(MISO) == HIGH) { };
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SPI.transfer(0x7F);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x06);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x55);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x01);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x3E);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x94);
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delayMicroseconds(vertragingA);
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SPI.transfer(0x01); //1 = Turn light off
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delayMicroseconds(vertragingA);
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SPI.transfer(0xAA);
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delayMicroseconds(vertragingA);
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SPI.transfer(0xFF);
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digitalWrite(SS,HIGH);
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SendStrobe(CC2500_STX); //0x35 STX In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: Only go to TX if channel is clear
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delayMicroseconds(vertragingA*10);
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}
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LIGHTOFF=true;
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}
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}
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@ -0,0 +1,72 @@
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/***************************************************************
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* SmartRF Studio(tm) Export
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*
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* Radio register settings specifed with C-code
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* compatible #define statements.
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*
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* RF device: CC2500
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*
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***************************************************************/
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#define REG_IOCFG2 0x0000
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#define REG_IOCFG1 0x0001
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#define REG_IOCFG0 0x0002
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#define REG_FIFOTHR 0x0003
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#define REG_SYNC1 0x0004
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#define REG_SYNC0 0x0005
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#define REG_PKTLEN 0x0006
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#define REG_PKTCTRL1 0x0007
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#define REG_PKTCTRL0 0x0008
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#define REG_ADDR 0x0009
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#define REG_CHANNR 0x000A
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#define REG_FSCTRL1 0x000B
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#define REG_FSCTRL0 0x000C
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#define REG_FREQ2 0x000D
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#define REG_FREQ1 0x000E
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#define REG_FREQ0 0x000F
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#define REG_MDMCFG4 0x0010
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#define REG_MDMCFG3 0x0011
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#define REG_MDMCFG2 0x0012
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#define REG_MDMCFG1 0x0013
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#define REG_MDMCFG0 0x0014
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#define REG_DEVIATN 0x0015
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#define REG_MCSM2 0x0016
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#define REG_MCSM1 0x0017
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#define REG_MCSM0 0x0018
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#define REG_FOCCFG 0x0019
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#define REG_BSCFG 0x001A
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#define REG_AGCCTRL2 0x001B
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#define REG_AGCCTRL1 0x001C
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#define REG_AGCCTRL0 0x001D
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#define REG_WOREVT1 0x001E
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#define REG_WOREVT0 0x001F
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#define REG_WORCTRL 0x0020
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#define REG_FREND1 0x0021
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#define REG_FREND0 0x0022
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#define REG_FSCAL3 0x0023
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#define REG_FSCAL2 0x0024
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#define REG_FSCAL1 0x0025
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#define REG_FSCAL0 0x0026
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#define REG_RCCTRL1 0x0027
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#define REG_RCCTRL0 0x0028
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#define REG_FSTEST 0x0029
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#define REG_PTEST 0x002A
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#define REG_AGCTEST 0x002B
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#define REG_TEST2 0x002C
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#define REG_TEST1 0x002D
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#define REG_TEST0 0x002E
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#define REG_PARTNUM 0x0030
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#define REG_VERSION 0x0031
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#define REG_FREQEST 0x0032
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#define REG_LQI 0x0033
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#define REG_RSSI 0x0034
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#define REG_MARCSTATE 0x0035
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#define REG_WORTIME1 0x0036
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#define REG_WORTIME0 0x0037
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#define REG_PKTSTATUS 0x0038
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#define REG_VCO_VC_DAC 0x0039
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#define REG_TXBYTES 0x003A
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#define REG_RXBYTES 0x003B
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#define REG_RCCTRL1_STATUS 0x003C
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#define REG_RCCTRL0_STATUS 0x003D
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#define REG_DAFUQ 0x007E
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@ -0,0 +1,52 @@
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/***************************************************************
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* SmartRF Studio(tm) Export
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*
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* Radio register settings specifed with C-code
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* compatible #define statements.
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*
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* RF device: CC2500
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*
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***************************************************************/
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#define VAL_IOCFG2 0x29
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#define VAL_IOCFG0 0x06
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#define VAL_PKTLEN 0xFF
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#define VAL_PKTCTRL1 0x04
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#define VAL_PKTCTRL0 0x05
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#define VAL_ADDR 0x01
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#define VAL_CHANNR 0x10
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#define VAL_FSCTRL1 0x09
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#define VAL_FSCTRL0 0x00
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#define VAL_FREQ2 0x5D
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#define VAL_FREQ1 0x93
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#define VAL_FREQ0 0xB1
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#define VAL_MDMCFG4 0x2D
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#define VAL_MDMCFG3 0x3B
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#define VAL_MDMCFG2 0x73 //MSK, No Manchester
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#define VAL_MDMCFG1 0xA2
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#define VAL_MDMCFG0 0xF8
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#define VAL_DEVIATN 0x01
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#define VAL_MCSM2 0x07
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#define VAL_MCSM1 0x30
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#define VAL_MCSM0 0x18
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#define VAL_FOCCFG 0x1D
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#define VAL_BSCFG 0x1C
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#define VAL_AGCCTRL2 0xC7
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#define VAL_AGCCTRL1 0x00
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#define VAL_AGCCTRL0 0xB2
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#define VAL_WOREVT1 0x87
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#define VAL_WOREVT0 0x6B
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#define VAL_WORCTRL 0xF8
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#define VAL_FREND1 0xB6
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#define VAL_FREND0 0x10
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#define VAL_FSCAL3 0xEA
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#define VAL_FSCAL2 0x0A
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#define VAL_FSCAL1 0x00
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#define VAL_FSCAL0 0x11
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#define VAL_RCCTRL1 0x41
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#define VAL_RCCTRL0 0x00
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#define VAL_FSTEST 0x59
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#define VAL_TEST2 0x88
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#define VAL_TEST1 0x31
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#define VAL_TEST0 0x0B
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#define VAL_DAFUQ 0xFF
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