1.7 KiB
RomStage <--> QcLib interface specification
Version 1
Description:
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RomStage <--> QcLib interface table is used to pass input information from RomStage to QcLib and receive information returned from QcLib to RomStage.
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Interface specification defines interface Table data structures: Table header data structure and table's entry data structure.
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RomStage populates interface table with entries for DDR (dcb) settings, DDR training data, power management IC (pmic) settings.
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RomStage passes this table to QcLib, QcLib processes this data and performs SOC clock, DDR, PMIC configuration.
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QcLib updates interface table entries for the blobs which need to be saved to storage.
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QcLib also adds ddr_information "Interface Table Entry" with DDR base_address and size of ddr and returns to RomStage.
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After returning from QcLib, RomStage processes interface table to take action for the blobs to be saved on storage and consumes returned ddr_information.
[Interface Table Header Info]
| Description | Size (bytes) | Value |
|---|---|---|
| magic | 8 | "QCLIB_CB" |
| version | 4 | 1 |
| num_entries | 4 | |
| max_entries | 4 | 16 |
| global_attributes | 4 | 0x1 : Enable Uart Logging |
| reserved | 8 | 0 |
| Interface Table Entry | 0x28 | |
| Repeat last entry n times | 0x28 | <runtime |
[Interface Table Entry Info]
| Description | Size (bytes) | Value |
|---|---|---|
| Name | 24 | "dcb_settings" OR |
| "pmic_settings" OR | ||
| "ddr_training" OR | ||
| "ddr_information" | ||
| blob_address | 8 | address of blob in memory |
| size | 4 | size of blob in memory |
| blob_attributes | 4 | 0x1 : Save to Storage |