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Coffee Lake FSP 7.0.64.40

This commit is contained in:
ClientSysFWGit 2019-05-23 13:31:30 -07:00
parent 418241751a
commit 59964173e1
6 changed files with 37933 additions and 37832 deletions
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CoffeeLakeFspBinPkg/Docs/CoffeeLake_FSP_Integration_Guide.chm
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CoffeeLakeFspBinPkg/Docs/CoffeeLake_FSP_Integration_Guide.pdf
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CoffeeLakeFspBinPkg/FSP.fd
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CoffeeLakeFspBinPkg/Fsp.bsf
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@ -427,7 +427,8 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0 $gPlatformFspPkgTokenSpaceGuid_X2ApicOptOut 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm 1 bytes $_DEFAULT_ = 0x0 $gPlatformFspPkgTokenSpaceGuid_MrcTrainOnWarm 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt 1 bytes $_DEFAULT_ = 0x2 $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt 1 bytes $_DEFAULT_ = 0x2
Skip 12 bytes $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn 1 bytes $_DEFAULT_ = 0x1
Skip 11 bytes
$gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0 $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00 $gPlatformFspPkgTokenSpaceGuid_BdatEnable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01 $gPlatformFspPkgTokenSpaceGuid_ScanExtGfxForLegacyOpRom 1 bytes $_DEFAULT_ = 0x01
@ -583,7 +584,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_PchCnviMfUart1Type 1 bytes $_DEFAULT_ = 0x00 $gPlatformFspPkgTokenSpaceGuid_PchCnviMfUart1Type 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable 1 bytes $_DEFAULT_ = 0x01 $gPlatformFspPkgTokenSpaceGuid_PchEspiLgmrEnable 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_Heci3Enabled 1 bytes $_DEFAULT_ = 0x0 $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled 1 bytes $_DEFAULT_ = 0x0
Skip 1 bytes $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_PchHotEnable 1 bytes $_DEFAULT_ = 0x00 $gPlatformFspPkgTokenSpaceGuid_PchHotEnable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_SataLedEnable 1 bytes $_DEFAULT_ = 0x00 $gPlatformFspPkgTokenSpaceGuid_SataLedEnable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert 1 bytes $_DEFAULT_ = 0x00 $gPlatformFspPkgTokenSpaceGuid_PchPmVrAlert 1 bytes $_DEFAULT_ = 0x00
@ -1159,6 +1160,11 @@ List &gPlatformFspPkgTokenSpaceGuid_SlpS0DisQForDebug
Selection 3 , "Auto" Selection 3 , "Auto"
EndList EndList
List &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn
Selection 0 , "Disable"
Selection 1 , "Enable"
EndList
List &gPlatformFspPkgTokenSpaceGuid_Peg2Enable List &gPlatformFspPkgTokenSpaceGuid_Peg2Enable
Selection 0 , "Disable" Selection 0 , "Disable"
Selection 1 , "Enable" Selection 1 , "Enable"
@ -2485,6 +2491,8 @@ Page "Memory Reference Code 1"
Help "Enables/Disable the MRC training on warm boot" Help "Enables/Disable the MRC training on warm boot"
Combo $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, "Lpddr Dram Odt", &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, Combo $gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt, "Lpddr Dram Odt", &gPlatformFspPkgTokenSpaceGuid_LpddrDramOdt,
Help "Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)" Help "Override Enable/Disable for the ODT logic for LPDDR3 memory. Default is 2 (AUTO)"
Combo $gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn, "DDR4 Skip Refresh Enable", &gPlatformFspPkgTokenSpaceGuid_Ddr4SkipRefreshEn,
Help "Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)"
Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS, Combo $gPlatformFspPkgTokenSpaceGuid_SkipExtGfxScan, "Skip external display device scanning", &EN_DIS,
Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices" Help "Enable: Do not scan for external display device, Disable (Default): Scan external display devices"
Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS, Combo $gPlatformFspPkgTokenSpaceGuid_BdatEnable, "Generate BIOS Data ACPI Table", &EN_DIS,
@ -3099,6 +3107,8 @@ Page "PCH 2"
Help "This option enables or disables espi lgmr" Help "This option enables or disables espi lgmr"
Combo $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled, "HECI3 state", &EN_DIS, Combo $gPlatformFspPkgTokenSpaceGuid_Heci3Enabled, "HECI3 state", &EN_DIS,
Help "The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable" Help "The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. 0: disable, 1: enable"
Combo $gPlatformFspPkgTokenSpaceGuid_Heci1Disabled, "HECI1 state", &EN_DIS,
Help "Determine if HECI1 is hidden prior to boot to OS. <b>0: Disable</b>; 1: Enable."
Combo $gPlatformFspPkgTokenSpaceGuid_PchHotEnable, "PCHHOT# pin", &EN_DIS, Combo $gPlatformFspPkgTokenSpaceGuid_PchHotEnable, "PCHHOT# pin", &EN_DIS,
Help "Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable" Help "Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable"
Combo $gPlatformFspPkgTokenSpaceGuid_SataLedEnable, "SATA LED", &EN_DIS, Combo $gPlatformFspPkgTokenSpaceGuid_SataLedEnable, "SATA LED", &EN_DIS,

10
CoffeeLakeFspBinPkg/Include/FspmUpd.h
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@ -2327,9 +2327,15 @@ typedef struct {
**/ **/
UINT8 LpddrDramOdt; UINT8 LpddrDramOdt;
/** Offset 0x0518 /** Offset 0x0518 - DDR4 Skip Refresh Enable
Enable/Disable of DDR4 Temperature Controlled Refresh on DRAM. Default is 1 (Enabled)
0:Disable, 1:Enable
**/ **/
UINT8 ReservedFspmUpd[7]; UINT8 Ddr4SkipRefreshEn;
/** Offset 0x0519
**/
UINT8 ReservedFspmUpd[6];
} FSP_M_CONFIG; } FSP_M_CONFIG;
/** Fsp M Test Configuration /** Fsp M Test Configuration

44
CoffeeLakeFspBinPkg/Include/FspsUpd.h
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@ -511,9 +511,11 @@ typedef struct {
**/ **/
UINT8 Heci3Enabled; UINT8 Heci3Enabled;
/** Offset 0x014E /** Offset 0x014E - HECI1 state
Determine if HECI1 is hidden prior to boot to OS. <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/ **/
UINT8 UnusedUpdSpace4; UINT8 Heci1Disabled;
/** Offset 0x014F - PCHHOT# pin /** Offset 0x014F - PCHHOT# pin
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
@ -621,7 +623,7 @@ typedef struct {
/** Offset 0x0162 /** Offset 0x0162
**/ **/
UINT8 UnusedUpdSpace5[1]; UINT8 UnusedUpdSpace4[1];
/** Offset 0x0163 - PCH PCIe root port connection type /** Offset 0x0163 - PCH PCIe root port connection type
0: built-in device, 1:slot 0: built-in device, 1:slot
@ -673,7 +675,7 @@ typedef struct {
/** Offset 0x01FD /** Offset 0x01FD
**/ **/
UINT8 UnusedUpdSpace6[3]; UINT8 UnusedUpdSpace5[3];
/** Offset 0x0200 - Enable/Disable SA CRID /** Offset 0x0200 - Enable/Disable SA CRID
Enable: SA CRID, Disable (Default): SA CRID Enable: SA CRID, Disable (Default): SA CRID
@ -729,7 +731,7 @@ typedef struct {
/** Offset 0x0219 /** Offset 0x0219
**/ **/
UINT8 UnusedUpdSpace7; UINT8 UnusedUpdSpace6;
/** Offset 0x021A - Enable or disable GNA device /** Offset 0x021A - Enable or disable GNA device
0=Disable, 1(Default)=Enable 0=Disable, 1(Default)=Enable
@ -958,7 +960,7 @@ typedef struct {
/** Offset 0x02BB /** Offset 0x02BB
**/ **/
UINT8 UnusedUpdSpace8[10]; UINT8 UnusedUpdSpace7[10];
/** Offset 0x02C5 - DcLoadline /** Offset 0x02C5 - DcLoadline
PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
@ -1026,7 +1028,7 @@ typedef struct {
/** Offset 0x0306 /** Offset 0x0306
**/ **/
UINT8 UnusedUpdSpace9[6]; UINT8 UnusedUpdSpace8[6];
/** Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization /** Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization
@deprecated SkipMpInit has been moved to FspmUpd @deprecated SkipMpInit has been moved to FspmUpd
@ -1193,7 +1195,7 @@ typedef struct {
/** Offset 0x0367 /** Offset 0x0367
**/ **/
UINT8 UnusedUpdSpace10; UINT8 UnusedUpdSpace9;
/** Offset 0x0368 - VC Type /** Offset 0x0368 - VC Type
Virtual Channel Type Select: 0: VC0, 1: VC1. Virtual Channel Type Select: 0: VC0, 1: VC1.
@ -1240,7 +1242,7 @@ typedef struct {
/** Offset 0x0378 /** Offset 0x0378
**/ **/
UINT8 UnusedUpdSpace11[5]; UINT8 UnusedUpdSpace10[5];
/** Offset 0x037D - Enable PCH Io Apic Entry 24-119 /** Offset 0x037D - Enable PCH Io Apic Entry 24-119
0: Disable; 1: Enable. 0: Disable; 1: Enable.
@ -1255,7 +1257,7 @@ typedef struct {
/** Offset 0x037F /** Offset 0x037F
**/ **/
UINT8 UnusedUpdSpace12; UINT8 UnusedUpdSpace11;
/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned /** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned
0: Disable; 1: Enable. 0: Disable; 1: Enable.
@ -1355,7 +1357,7 @@ typedef struct {
/** Offset 0x0390 /** Offset 0x0390
**/ **/
UINT8 UnusedUpdSpace13[3]; UINT8 UnusedUpdSpace12[3];
/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK /** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
@ -1461,7 +1463,7 @@ typedef struct {
/** Offset 0x04FA /** Offset 0x04FA
**/ **/
UINT8 UnusedUpdSpace14[4]; UINT8 UnusedUpdSpace13[4];
/** Offset 0x04FE - PCIE RP Pcie Speed /** Offset 0x04FE - PCIE RP Pcie Speed
Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
@ -1556,7 +1558,7 @@ typedef struct {
/** Offset 0x05BB /** Offset 0x05BB
**/ **/
UINT8 UnusedUpdSpace15[13]; UINT8 UnusedUpdSpace14[13];
/** Offset 0x05C8 - PCIE RP Aspm /** Offset 0x05C8 - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
@ -1615,7 +1617,7 @@ typedef struct {
/** Offset 0x0664 /** Offset 0x0664
**/ **/
UINT8 UnusedUpdSpace16; UINT8 UnusedUpdSpace15;
/** Offset 0x0665 - PCIE Compliance Test Mode /** Offset 0x0665 - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board. Compliance Test Mode shall be enabled when using Compliance Load Board.
@ -1763,7 +1765,7 @@ typedef struct {
/** Offset 0x067E /** Offset 0x067E
**/ **/
UINT8 UnusedUpdSpace17[2]; UINT8 UnusedUpdSpace16[2];
/** Offset 0x0680 - PCH Pm Lpc Clock Run /** Offset 0x0680 - PCH Pm Lpc Clock Run
This member describes whether or not the LPC ClockRun feature of PCH should be enabled. This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
@ -1797,7 +1799,7 @@ typedef struct {
/** Offset 0x0685 /** Offset 0x0685
**/ **/
UINT8 UnusedUpdSpace18; UINT8 UnusedUpdSpace17;
/** Offset 0x0686 - PCH Pm Disable Native Power Button /** Offset 0x0686 - PCH Pm Disable Native Power Button
Power button native mode disable. Power button native mode disable.
@ -1837,7 +1839,7 @@ typedef struct {
/** Offset 0x068C /** Offset 0x068C
**/ **/
UINT8 UnusedUpdSpace19; UINT8 UnusedUpdSpace18;
/** Offset 0x068D - PCH Sata Pwr Opt Enable /** Offset 0x068D - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side. SATA Power Optimizer on PCH side.
@ -2026,7 +2028,7 @@ typedef struct {
/** Offset 0x0700 /** Offset 0x0700
**/ **/
UINT8 UnusedUpdSpace20; UINT8 UnusedUpdSpace19;
/** Offset 0x0701 - PcdSerialIoUart0PinMuxing /** Offset 0x0701 - PcdSerialIoUart0PinMuxing
Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled. Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.
@ -2036,7 +2038,7 @@ typedef struct {
/** Offset 0x0702 /** Offset 0x0702
**/ **/
UINT8 UnusedUpdSpace21[1]; UINT8 UnusedUpdSpace20[1];
/** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines /** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines
Enables UART hardware flow control, CTS and RTS linesh. Enables UART hardware flow control, CTS and RTS linesh.
@ -2309,7 +2311,7 @@ typedef struct {
/** Offset 0x0753 /** Offset 0x0753
**/ **/
UINT8 UnusedUpdSpace22; UINT8 UnusedUpdSpace21;
/** Offset 0x0754 - Pch PCIE device override table pointer /** Offset 0x0754 - Pch PCIE device override table pointer
The PCIe device table is being used to override PCIe device ASPM settings. This The PCIe device table is being used to override PCIe device ASPM settings. This
@ -3350,7 +3352,7 @@ typedef struct {
/** Offset 0x0A61 /** Offset 0x0A61
**/ **/
UINT8 UnusedUpdSpace23[17]; UINT8 UnusedUpdSpace22[17];
/** Offset 0x0A72 - Skip POSTBOOT SAI /** Offset 0x0A72 - Skip POSTBOOT SAI
Deprecated Deprecated