Amanda Huang d925ca70d9 util: Add new memory part to LP4x list ... Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes are derived from data sheets.Also, regenerate the SPD files for ADL SoC using the newly added parts. BUG=b:181378727 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2021-03-03 15:50:47 +00:00
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acpi	soc/intel: Include gfx.asl from northbridge	2021-03-01 08:32:47 +00:00
bootblock	soc/intel: Drop `bootblock_cpu_init()` function	2021-03-01 19:43:04 +00:00
include/soc	soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devices	2021-03-03 09:03:55 +00:00
romstage	soc/intel: Drop `romstage_pch_init()` function	2021-03-01 19:41:17 +00:00
spd	util: Add new memory part to LP4x list	2021-03-03 15:50:47 +00:00
Kconfig	soc/intel: Factor out common smmrelocate.c	2021-03-03 09:06:09 +00:00
Makefile.inc	soc/intel: Factor out common smmrelocate.c	2021-03-03 09:06:09 +00:00
acpi.c	soc/intel: Factor out identical acpigen GPIO helpers	2021-03-01 19:37:56 +00:00
chip.c	soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore	2021-02-24 11:28:45 +00:00
chip.h	soc/intel: Retype `CnviBtAudioOffload` devicetree option	2021-03-03 09:02:03 +00:00
chipset.cb	soc/intel: hook up new gpio device in the soc chips	2020-12-30 00:30:04 +00:00
cpu.c	src: Remove unused <arch/cpu.h>	2021-02-11 10:25:23 +00:00
elog.c	soc/intel/alderlake: Log internal device wake events	2021-03-03 09:04:12 +00:00
espi.c	soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroring	2021-01-25 09:06:10 +00:00
finalize.c	soc/intel/*: drop useless XTAL shutdown qualification code	2020-10-19 07:09:12 +00:00
fsp_params.c	soc/intel/alderlake: Refactor PCIE port config	2021-02-05 09:39:58 +00:00
gpio.c	soc/intel/alderlake: Add GPIOs for Alder Lake SOC	2020-09-27 03:03:25 +00:00
gspi.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
i2c.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
lockdown.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
me.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
meminit.c	soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver	2021-01-25 19:14:19 +00:00
p2sb.c	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	2020-09-15 15:13:50 +00:00
pcie_rp.c	soc/intel/alderlake: Update PCH and CPU PCIe RP table	2021-01-18 07:28:51 +00:00
pmc.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
pmutil.c	soc/intel/*/pmutil.c: Align cosmetics across platforms	2021-02-24 11:34:42 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
smihandler.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
soundwire.c	mb/intel: Enable ALC711 Audio codec over SNDW0 link	2020-11-07 08:55:53 +00:00
spi.c	soc/intel/alderlake: Add SPI DMI Destination ID	2020-12-23 03:28:47 +00:00
systemagent.c	soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig options	2021-01-30 23:14:08 +00:00
uart.c	soc/intel: Remove unused <console/console.h>	2021-02-15 10:50:09 +00:00
xhci.c	soc/intel/alderlake: Add soc_get_xhci_usb_info() for elog support	2021-02-24 11:27:51 +00:00